JPH07135220A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance a GaAs field-effect transistor of high output power in output characteristics without deteriorating it in drain breakdown strength. CONSTITUTION:A source electrode 7 and a gate electrode 4 are formed on an operating layer 2 on the same plane, and a drain electrode 8 is formed in a groove made in the surface of the operating layer 2, whereby a GaAs field effect transistor of high output power of this constitution can be enhanced in output characteristics without deteriorating in drain breakdown strength due to a channel constriction on a source side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a GaAs field effect transistor and its manufacturing method.

[0002]

2. Description of the Related Art A field effect transistor having a GaAs semiconductor layer as an operating layer is used as a high-power element in a high frequency region. In such an element, it is extremely important to increase breakdown voltage in order to operate at a high voltage. Has become a problem. The breakdown points during high voltage operation are:
Particularly, there are many drain electrode edges, and it is required to relax the electric field in this portion.

FIG. 4 is a sectional view of a semiconductor chip showing a first example of a conventional semiconductor device.

As shown in FIG. 4, an operating layer 2 formed by epitaxially growing an n-type GaAs layer on a semi-insulating GaAs substrate 1, a gate electrode 4, a source electrode 7, and a gate electrode 4 provided on the surface of the operating layer 2. The drain electrode 8 is provided, and the groove 9 is formed on the surface of the operating layer 2 in the vicinity of the source electrode 7 and the drain electrode 8. With such a structure, the electric field applied to the end of the ohmic electrode on the drain side at the time of high voltage operation is relaxed, and the drain breakdown voltage can be improved.

FIG. 5 is a sectional view of a semiconductor chip showing a second example of a conventional semiconductor device.

As shown in FIG. 5, shallow trenches 10 are formed in the source and drain electrode forming regions on the surface of the operating layer 2 formed on the semi-insulating GaAs substrate 1, and the source electrodes 7 are formed in the trenches 10. The structure is similar to that of the first example except that the drain electrode 8 is formed, and like the first example, the electric field applied to the end of the drain electrode is relaxed to improve the drain breakdown voltage. ing.

[0007]

In this conventional semiconductor device, a groove is formed on the source electrode side similarly to the drain side. However, with such a structure, the channel on the source side is constricted and the parasitic resistance is reduced. There is a problem in that a high output cannot be obtained because it becomes a factor that limits the drain current especially during a large amplitude operation.

An object of the present invention is to provide a semiconductor device having improved output characteristics while maintaining the drain breakdown voltage.

[0009]

The semiconductor device of the present invention comprises:
An operating layer formed on a semi-insulating GaAs substrate, a gate electrode formed on the operating layer, a source electrode formed on the operating layer on the same plane as the operating layer provided with the gate electrode, and the operating layer And a drain electrode formed in the groove provided in.

The method of manufacturing the present semiconductor device uses the semi-insulating Ga
A step of forming an insulating film on the surface of the operating layer formed on the As substrate; a step of forming an opening for forming a gate electrode using the photoresist film formed and patterned on the insulating film as a mask; Depositing a metal film on a photoresist film including an opening and removing the photoresist film and the metal film on the photoresist film by a lift-off method to form a gate electrode; and an upper portion of the insulating film and the operating layer. Selectively and sequentially etching to form a groove for forming a drain electrode; and, after removing the insulating film, the source electrode and the groove of the operating layer on the same plane as the plane where the gate electrode is provided by a lift-off method. And a drain electrode inside thereof are formed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1D are cross-sectional views of a semiconductor chip showing the order of steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG. 1A, an n-type GaAs layer having an impurity concentration of about 2 × 10 ¹⁷ cm ^-3 is formed on a semi-insulating GaAs substrate 1 by MBE (molecular beam epitaxial growth). 0.3 μm thick or Si
Ion acceleration energy 100 keV, dose 4 × 1
The ^active layer 2 is formed by ion implantation at 0 ¹² cm ^-2 . Next, a mesa etch or oxygen is selectively ion-implanted into the operating layer 2 to form an element isolation region (not shown). Next, a SiO ₂ film 3 as an insulating film is formed on the surface including the operating layer 2 by 300 times.
After depositing to a thickness of 400 nm, a photoresist film is applied on the SiO ₂ film 3 and patterned, and SiO ₂ is buffered with hydrofluoric acid using this photoresist film as a mask.
_{2 The} film 3 is removed by etching to form an opening for forming a gate electrode.

Next, an aluminum film having a thickness of 500 nm is vapor-deposited on the photoresist film including the openings, and the aluminum film on the photoresist film is removed by a lift-off method to form the gate electrode 4.

Next, as shown in FIG. 1B, a photoresist film 5 is applied on the SiO ₂ film 3 including the gate electrode 4 and patterned to open a drain electrode forming region.

Next, as shown in FIG. 1C, SiO ₂ is buffered with hydrofluoric acid using the photoresist film 5 as a mask.
After the film 3 is removed by etching, the surface of the operating layer 2 is further etched with a mixed solution of sulfuric acid and hydrogen peroxide solution to a depth of about 10 to 50 nm to form a groove 6 and the photoresist film 5 Remove.

Next, as shown in FIG. 1D, SiO ₂
After removing the film 3, a photoresist film is applied to the surface including the gate electrode 4 and patterned to form openings for forming source and drain electrodes. Next, an AuGe / Ni film is deposited on the surface including the opening by an evaporation method and lifted off to form each of the source electrode 7 and the drain electrode 8. Here, the drain electrode 8 is formed in the groove 6.

2 (a) to 2 (d) are sectional views of a semiconductor chip showing the order of steps for explaining the manufacturing method of the second embodiment of the present invention.

First, as shown in FIG. 2A, an operating layer 2 is formed on a semi-insulating GaAs substrate 1 by the same process as in the first embodiment to form an element isolation layer (not shown). After forming
The SiO ₂ film 3 is formed on the surface including the active layer 2, SiO ₂
Patterning the photoresist film provided on the film 3,
An opening is formed in the SiO ₂ film 3 by using this photoresist film as a mask. Next, an aluminum film is deposited on the photoresist film including the opening and lifted off to form the gate electrode 4. Next, a photoresist film 5 is applied on the SiO ₂ film 3 including the gate electrode 4 and patterned to open a drain electrode formation region.

Next, as shown in FIG. 2B, the SiO ₂ film 3 is removed by etching using the photoresist film 5 as a mask, and then the surface of the operating layer is further etched to form a groove 6.

Next, as shown in FIG. 2B, the SiO ₂ film 3 is etched and removed using the photoresist film 5 as a mask, and then the surface of the operating layer is further etched to form a groove 6.

Next, as shown in FIG. 2C, an ohmic metal film is deposited on the photoresist film 5 including the groove 6 and lifted off to form a drain electrode 8 in the groove 6.

Next, as shown in FIG. 2D, SiO ₂
After removing the film 3, an ohmic metal film is selectively formed on the operating layer 2 to form the source electrode 7.

The second embodiment has an advantage that the accuracy of alignment between the drain electrode 8 and the groove 6 can be improved.

FIG. 3 is a diagram showing the input-output characteristics of the field effect transistor according to the present invention in comparison with the conventional example.

As shown in FIG. 3, according to the present invention, high output characteristics can be improved without degrading the drain breakdown voltage.

[0027]

As described above, according to the present invention, the output characteristics can be improved without deteriorating the drain breakdown voltage by forming only the drain electrode in the groove provided on the surface of the operating layer. Have an effect.

[Brief description of drawings]

1A to 1C are cross-sectional views of a semiconductor chip in the order of steps for explaining a manufacturing method according to a first embodiment of the present invention.

2A to 2D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to a second embodiment of the present invention.

FIG. 3 is a diagram showing input-output characteristics of the present invention and a conventional example.

FIG. 4 is a sectional view of a semiconductor chip showing a first example of a conventional semiconductor device.

FIG. 5 is a sectional view of a semiconductor chip showing a second example of a conventional semiconductor device.

[Explanation of symbols]

1 semi-insulating GaAs substrate 2 n-type GaAs layer 3 SiO ₂ film 4 gate electrode 5 photoresist film 6, 9, 10 groove 7 source electrode 8 drain electrode

Claims (2)

[Claims] 1. An operating layer formed on a semi-insulating GaAs substrate, a gate electrode formed on the operating layer, and a source electrode formed on the operating layer on the same plane as the operating layer provided with the gate electrode. And a drain electrode formed in the groove provided in the operating layer. 2. A step of forming an insulating film on a surface of an operating layer formed on a semi-insulating GaAs substrate, and an opening for forming a gate electrode using a photoresist film formed on the insulating film and patterned as a mask. A step of forming a portion, a step of depositing a metal film on the photoresist film including the opening and removing the photoresist film and the metal film on the photoresist film by a lift-off method to form a gate electrode, Forming a groove for forming a drain electrode by selectively sequentially etching the insulating film and the upper portion of the operating layer; and removing the insulating film and then performing a lift-off method on the same plane as the plane where the gate electrode is provided. And a step of forming a source electrode of the operating layer and a drain electrode in the groove, respectively.