JPH0684846A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To achieve that the good characteristic of an ultrathin-film SOI transistor is displayed and to form a gate electrode with good controllability by installing a process wherein impurities are introduced into only a region down to a prescribed depth from the surface of an SOI layer. CONSTITUTION:A first photoresist pattern(PP) 15 is formed on an SOI layer 3, the SOI layer is etched and separated by making use of the pattern as a mask, the first PP 15 is removed, and the difference in level of the SOI layer 13 is flattened by an insulating film 16. Then, a second PP 18 is formed on the insulating film 16, the insulating film 16 is etched by making use of the PP as a mask, a groove 17 is formed, and impurities are introduced, from the groove 17, into only a region 19 down to a prescribed depth from the surface of the SOI layer 13. Then, the second PP 18 is removed, only the region 19 into which the impurities have been introduced in the SOI layer 13 is removed selectively, a doped polysilicon film 22 is formed, and the doped polysilicon film 22 is etched back. Thereby, a gate electrode 14 is formed in a self-aligned manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device,
More specifically, the present invention relates to a method for manufacturing a semiconductor device, which is preferably implemented in a high-speed large-scale integrated circuit or the like.

[0002]

2. Description of the Related Art SOIMO manufactured using an SOI substrate
It is known that the characteristics of the S transistor exceed the characteristics of the MOS transistor formed on the bulk silicon by improving the mobility and the current driving capacity by reducing the SOI film thickness.

An example of a conventional method of manufacturing this kind of ultra-thin film SOI transistor will be described with reference to FIG. Figure 5 (a)
8D to 8D are schematic cross-sectional views showing the manufacturing process of the ultrathin film SOI transistor as the first conventional example.

First, an oxide film 42 is formed on a silicon substrate 41.
The SOI substrate 40 in which the SOI layer 43 is sequentially formed is manufactured (FIG. 5A). This SOI substrate 40 is SIMOX
(Separation by IMplanted OXygen) method, ZMR (Zone
It is manufactured by the Melting Recrystalization) method, the bonding method, or the like.

Next, the SOI layer 43 is thinned to a thickness of 1000 Å or less by etching by RIE or thermal oxidation and removal of the oxide film (FIG. 5B).

Further, the thinned SOI layer 43 is etched by RIE using the photoresist 45 as a mask (FIG. 5C).

Thereafter, a gate oxide film 51 is formed on the SOI layer 43, a gate electrode 44 is formed on the gate oxide film 51, and an oxide film 53 is formed on the entire surface of the silicon substrate 41 by a normal MOS transistor manufacturing process. After that, the oxide film 53 is etched by a photomask or the like (not shown), the metal wiring 54 is formed at the etched position, and the ultrathin film SOI transistor is manufactured (FIG. 5D).

In addition to this, in this type of thin film transistor, there is a thin film SOI transistor in which a gate electrode is formed so as to surround a silicon region which becomes a channel. By setting the film thickness so that the silicon region serving as the channel is completely depleted, the control power of the gate electrode with respect to the channel is increased, and the same excellent characteristics as the ultra-thin film SOI transistor shown in the above-mentioned conventional example are exhibited. Not only that, it is known that the depletion of the channel region is achieved at a lower gate voltage and the speed can be further increased.

FIGS. 6A to 6F are schematic sectional views showing a manufacturing process of the thin film SOI transistor in which a gate electrode is formed so as to surround a silicon region which becomes a channel as a second conventional example. .

First, on the silicon substrate 61, an oxide film 62,
After manufacturing the SOI substrate 60 in which the SOI layer 63 is sequentially formed, the SOI layer 63 of the SOI substrate 60 is etched by RIE or thermally oxidized and oxide film is removed to 1000 Å.
The thickness is reduced to the following thickness (FIG. 6A). The SOI
The substrate is manufactured by, for example, the SIMOX method, the ZMR method, the bonding method, or the like.

Next, using the photoresist 65 as a mask, S
The OI layer 63 is etched (FIG. 6B).

Further, using the photoresist 67 as a mask, the oxide film 62 in the region where the gate electrode is to be formed is etched with hydrofluoric acid to form a cavity 75 (FIG. 6C).

Subsequently, a gate oxide film 71 is formed on the surface of the SOI layer 63 not in contact with the oxide film 62, a doped polysilicon 72 is formed on the entire surface, and the cavity 75 is also filled with the doped polysilicon 72. (FIG.6 (d)).

Next, the doped polysilicon 72 is etched by using the photoresist 76 as a mask to etch the gate electrode 6.
4 is formed (FIG. 6E).

After removing the photoresist 76, impurities are introduced into the SOI layer 63 to be the source / drain (FIG. 6 (f)), and metal wirings (not shown) and the like are formed according to the usual procedure. Make a MOSFET.

[0016]

In the first conventional example, the film thickness of the SOI layer 43 is set to 100 because of the gate voltage relationship.
The thickness of the source / drain diffusion layer must be reduced to 0 Å or less. When the thickness of the source / drain diffusion layer is reduced, the resistance in the source / drain diffusion layer increases, which causes a problem of deteriorating the electrical characteristics. Further, since the source / drain diffusion layer is thin, there is a problem that the diffusion layer may disappear due to etching when the contact hole is opened.

Further, in the second conventional example, the SOI layer 6
The cavity 75 under 3 is formed by wet etching of the oxide film 62. However, since it is isotropic etching, variations in etching are large and it is difficult to control the line width.
There is a problem that it is difficult to form the fine gate electrode 64.

The present invention is a method invented in view of the above problems, which is a method for manufacturing a semiconductor device capable of exhibiting excellent characteristics of an ultrathin film SOI transistor and forming a gate electrode with good controllability. It is intended to be provided.

[0019]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first photoresist pattern on an SOI layer, and a step of forming the first photoresist pattern.
A step of etching and separating the SOI layer using a photoresist pattern as a mask; a step of removing the first photoresist pattern and planarizing a step of the SOI layer by etching with an insulating film; and a second step on the insulating film. Forming a photoresist pattern, etching the insulating film using the second photoresist pattern as a mask to form a groove, and introducing impurities from the groove to a region from the surface of the SOI layer to a predetermined depth A step of selectively removing only the impurity-doped region of the SOI layer after removing the second photoresist pattern, forming a doped polysilicon film, and then removing the doped polysilicon film. By etching back the SO
And (1) the step of forming a gate electrode by self-alignment in the selectively etched region of the I layer and inside the groove formed in the insulating film (1), and the semiconductor device according to the present invention. The manufacturing method includes a step of forming a first photoresist pattern on the SOI layer, a step of etching and separating the SOI layer using the first photoresist pattern as a mask, and an etching after removing the first photoresist pattern. A step of flattening the step of the SOI layer with an insulating film by the method, and a step of forming a second photoresist pattern on the insulating film and etching the insulating film using the second photoresist pattern as a mask to form a groove. And a step of introducing impurities from the groove into a region from a predetermined depth of the SOI layer to a bottom surface of the SOI layer, the second
After the photoresist pattern is removed, only the impurity-doped region of the SOI layer is selectively removed by etching, and after the doped polysilicon film is formed, the doped polysilicon film is etched back to remove the impurities. The method further comprises the step of forming a gate electrode by self-alignment in the selectively etched region of the SOI layer and the inside of the groove formed in the insulating film (2), and the above (1) and (). The method 2) is characterized in that phosphorus / arsenic ions are used as impurities to be introduced into the SOI at a predetermined depth.

[0020]

According to the method described in the above (1), the impurity is SO
Since the step of introducing into the region from the surface of the I layer to a predetermined depth is included, only the silicon region to be the channel can be selectively thinned by using the substrate having the thick SOI layer. By increasing the thickness of the drain diffusion layers, the resistance of these diffusion layers is reduced. In addition, the gate electrode is accurately formed by self-alignment only in the selectively etched region of the SOI layer, that is, just above the silicon region which becomes the channel.

Further, according to the method described in (2) above, the method includes the step of introducing an impurity into a region from a predetermined depth of the SOI layer to the bottom surface of the SOI layer, and thins only a silicon region to be a channel. Therefore, the silicon regions to be the source / drain can be formed thick. Further, a gate electrode is formed so as to surround the silicon region which will be the channel. Therefore, the silicon region serving as the channel is accurately thinned, and the resistance of the source / drain layer is prevented from increasing and the source / drain layer is prevented from disappearing when the contact hole is formed. In addition, the line width controllability of the gate electrode formed below the SOI layer is improved, and the gate power is also improved.

In the methods described in (1) and (2) above, when phosphorus or arsenic ions are used as impurities to be introduced into the SOI at a predetermined depth, it is desired to adjust the impurity implantation conditions such as implantation energy. It becomes easy to form the impurity-implanted layer at the depth of.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

1A to 1I are a sectional view and a plan view showing each step of the method for manufacturing a semiconductor device according to the embodiment. FIG. 2 is a schematic perspective view showing a semiconductor device manufactured by the method of FIG. First, an oxide film 12 having a film thickness of 1 μm and an SOI layer 13 having a film thickness of 3000 Å are formed on a silicon substrate 11.
The SOI substrate 10 in which the layers are sequentially formed is manufactured (FIG. 1).
(A)). The SOI substrate 10 is, for example, SIMOX method, ZM
It is produced by the R method, the laminating method, or the like.

Subsequently, a photoresist pattern 15 is formed on the SOI layer 13, and the SOI layer 13 is etched by RIE using the photoresist pattern 15 as a mask to separate the elements (FIG. 1B).

Subsequently, after removing the photoresist pattern 15, the oxide film 12 on which the SOI layer 13 is not formed is formed.
An oxide film 16 is formed on the SOI layer 13 and the SOI layer 13 as shown in FIG.
The step generated in the etching step of the SOI layer 13 in (b) is flattened by using, for example, an etch back method (FIG. 1C).

Next, a photoresist pattern 18 is formed on the oxide film 16, and the flattened oxide film 16 is etched by RIE using the photoresist pattern 18 as a mask to form a groove 17 (FIG. 1 (d)).

The photoresist pattern 18 at this time is a pattern of a gate electrode formed in a later step, and is shown in FIG.
A plan view of (d) is shown in FIG. As shown in FIG. 1D ', the pattern of the gate electrode is the SOI layer 1
It is formed so as to intersect with 3.

Then, the SOI layer 13 is patterned, for example, with a thickness of 80 k using the photoresist pattern 18 and the oxide film 16 as a mask.
Phosphorus ions are implanted as an n-type impurity under the conditions of eV and 4 × 10 ¹⁵ cm ⁻² . Then, heat treatment is performed to obtain S
An n-type impurity is diffused in the OI layer 13 to form an n-type impurity injection layer 19 from the surface of the SOI layer 13 to a depth of 2000Å (FIG. 1E).

Next, after the photoresist 18 is removed, n is removed by using an etching solution containing a mixture of hydrofluoric acid, acetic acid and nitric acid.
The type impurity implantation layer 19 is selectively removed by etching to form a cavity 20 (FIG. 1 (f)). As a result, the silicon region serving as the channel of the SOI layer 13 is thinned to a thickness of 1000Å.

Subsequently, the gate oxide film 21 is formed on the SOI layer 13
Then, a doped polysilicon film 22 having n-type impurities introduced therein is formed on the bottom and side walls of the cavity 20 to form 5000 Å (FIG. 1 (g)). At this time, the doped polysilicon film 22 is also formed in the cavity 20.

Further, the doped polysilicon film 22 is RI
The entire surface is etched by E, and the etching is stopped when the oxide film 16 is exposed. As a result, the doped polysilicon film 22 is left only in the cavity 20 and the gate electrode 14 is formed (FIG. 1 (h)).

Then, only the oxide film 16 is etched by RIE to expose the surface of the SOI layer 13 (FIG. 1).
(I), FIG. 2). After that, it is manufactured in the same manner as a normal MOS transistor.

In the method of manufacturing the semiconductor device according to the present embodiment described above, the n-type impurity is introduced only into the region from the surface of the SOI layer 13 to a depth of 2000 Å to form the source / drain regions of the SOI. Although the entire layer 13 can be formed thick, only the silicon region to be the channel can be accurately thinned, and the resistance in the source / drain diffusion layer can be reduced.
Further, the gate electrode 14 can be formed with high accuracy by self-alignment only directly above the silicon region which becomes the thinned channel, the electrical characteristics can be improved, and a high-quality SOIMOS transistor can be manufactured.

FIGS. 3A to 3I are a sectional view and a plan view showing another manufacturing process of the semiconductor device according to the present invention.
FIG. 4 is a schematic perspective view showing a semiconductor device manufactured by the method of FIG. First, the silicon substrate 31 has a film thickness of 1
An SOI substrate 30 in which an oxide film 32 having a thickness of μm and an SOI layer 33 having a film thickness of 3000 Å are successively formed (FIG.
(A)).

Subsequently, a photoresist pattern 35 is formed, and the SOI layer 33 is etched by RIE using the photoresist pattern 35 as a mask to separate elements (FIG. 3).
(B)).

Subsequently, after removing the photoresist pattern 35, the step generated by etching the SOI layer 33 is flattened by an oxide film 36 formed by using, for example, an etch back method (FIG. 3C). ).

Subsequently, a photoresist pattern 38 is formed on the oxide film 36, and the oxide film 36 is etched by RIE using the photoresist pattern 38 as a mask to form a groove 37 (FIG. 3D). At this time, the photoresist pattern 38 is the pattern of the gate electrode.
A plan view of (d) is shown in FIG. As shown in FIG. 3D ', the groove 37 is formed so as to intersect with the SOI layer 33, and the oxide film 36 not masked by the photoresist pattern 38 is etched.

Then, using the photoresist pattern 38 and the oxide film 36 as a mask, phosphorus ions are implanted into the SOI layer 33 as n-type impurities under the conditions of 200 keV and 4 × 10 ¹⁵ cm ^-2. By performing heat treatment, the n-type impurity implantation layer 39 is formed. At this time, the upper surface of the n-type impurity implantation layer 39 is located 1000 Å from the surface of the SOI layer 33, and the bottom surface of the n-type impurity implantation layer 39 is S.
The OI layer 33 is formed so as to reach the bottom surface (FIG. 3).
(E)).

Next, after removing the photoresist 38, n is removed by using an etching solution in which fluorine, acetic acid and nitric acid are mixed.
The type impurity implantation layer 39 is selectively removed by etching to form a cavity 40 (FIG. 3F). At this time, the etching solution is the oxide film 36 when the etching is performed in the process of FIG.
Is etched into the groove 37 formed in the oxide film 36, and the n-type impurity implantation layer 39 of the SOI layer 33 is etched from the side surface. As a result, the silicon region serving as the channel of the SOI layer 33 is thinned to a thickness of 1000Å.

Subsequently, a gate oxide film 41 is formed on the entire surface of the exposed SOI layer 33, and then, a doped polysilicon 42 having an n-type impurity introduced therein is formed in a thickness of 5000 .ANG. (FIG. 3 (g)). At this time, the low pressure CVD is performed so that the doped polysilicon 42 extends into the cavity 40 through the groove 37.
Method is used to form the doped polysilicon 42 in the cavity 40 existing below the SOI layer 33.

Further, the doped polysilicon 42 is subjected to RIE.
Then, the entire surface is etched, and the etching is stopped when the oxide film 36 is exposed. As a result, the doped polysilicon 32 remains only in the cavity 40 and the groove 37, and the gate electrode 34 is formed (FIG. 3 (h)).

Then, the oxide film 36 is etched by RIE to expose the surface of the SOI layer 33 (FIG. 3).
(I), FIG. 4). After that, it is manufactured in the same manner as a normal MOS transistor.

As described above, in the method of manufacturing the semiconductor device according to the above-described embodiment, the n-type impurity is introduced into the region from the surface of the SOI layer 33 to a depth of 1000Å to the bottom surface of the SOI layer 33. As a result, the entire SOI layer 33 serving as the source / drain region can be formed thick, but only the silicon region serving as the channel can be accurately thinned, and the gate electrode 34 surrounds the silicon region serving as the channel. Can be formed. Therefore, in addition to the effects of the first embodiment described above, depletion of the channel region is achieved with a lower gate voltage, and an SOIMOS transistor with a higher speed can be manufactured.

[0045]

As described above in detail, in the method of manufacturing a semiconductor device according to the present invention, the step of forming a first photoresist pattern on the SOI layer, and the step of forming the SOI layer using the first photoresist pattern as a mask. A step of etching and separating, a step of removing the first photoresist pattern and planarizing a step of the SOI layer by etching with an insulating film, a second photoresist pattern formed on the insulating film, 2 a step of forming a groove by etching the insulating film using the photoresist pattern as a mask, a step of introducing impurities from the groove only into a region from the surface of the SOI layer to a predetermined depth, and the second photoresist pattern And then removing only the impurity-doped region of the SOI layer by etching, and forming a doped polysilicon film. And then etching back the doped polysilicon film to form a gate electrode by self-alignment in the selectively etched region of the SOI layer and inside the trench formed in the insulating film. Therefore, only the silicon region to be the channel can be thinned with good control, and the resistance of the source / drain layer can be reduced by increasing the thickness of the source / drain diffusion layer. Further, the gate electrode having good controllability can be formed without the diffusion layer disappearing due to etching when forming the contact hole.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a first photoresist pattern on the SOI layer, a step of etching and separating the SOI layer using the first photoresist pattern as a mask, Removing the first photoresist pattern and planarizing the step of the SOI layer by etching with an insulating film; forming a second photoresist pattern on the insulating film;
A step of forming a groove by etching the insulating film using a photoresist pattern as a mask;
Introducing into a region from a predetermined depth of the OI layer to the bottom surface of the SOI layer; and removing the second photoresist pattern and selectively etching away only the region of the SOI layer into which impurities have been introduced. After forming the doped polysilicon film, the gate electrode is self-aligned in the selectively etched region of the SOI layer and inside the trench formed in the insulating film by etching back the doped polysilicon film. In the case of including the step of forming, the entire SOI layer to be the source / drain region can be formed thick, but only the silicon region to be the channel can be accurately thinned, and the silicon region to be the channel can be formed. A gate electrode can be formed to surround the. Therefore, in addition to the effects of the first embodiment described above, depletion of the channel region is achieved with a lower gate voltage, and an SOIMOS transistor with a higher speed can be manufactured.

Further, in the above method, when phosphorus or arsenic ions are used as impurities to be introduced at a predetermined depth of SOI, an impurity implantation layer is formed at a desired depth by adjusting impurity implantation conditions such as energy. You can

[Brief description of drawings]

1A to 1I are schematic cross-sectional views sequentially showing steps in an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic perspective view showing a semiconductor device in an example.

3 (a) to 3 (i) are schematic cross-sectional views sequentially showing steps in another embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a schematic perspective view showing a semiconductor device in an example.

5A to 5D are schematic cross-sectional views sequentially showing an example of steps of a conventional method for manufacturing a semiconductor device.

6A to 6F are schematic cross-sectional views sequentially showing an example of steps of another conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

13, 33 SOI layer 14, 32 Gate electrode 15, 35 Photoresist pattern (first photoresist pattern) 16, 36 Oxide film 17, 37 Groove 18, 38 Photoresist pattern (second photoresist pattern) 20, 40 Cavity (selectively etched region) 22, 42 Doped polysilicon film

Claims (3)

[Claims] 1. A step of forming a first photoresist pattern on an SOI (Silicon On Insulator) layer, a step of etching and separating the SOI layer using the first photoresist pattern as a mask, and the first photoresist. After the pattern is removed, a step of flattening the step of the SOI layer by etching with an insulating film, a second photoresist pattern is formed on the insulating film, and the insulating film is etched using the second photoresist pattern as a mask. Forming a groove by introducing the impurity into the region from the surface of the SOI layer to a predetermined depth from the groove, and removing the second photoresist pattern from the region into which the impurity is introduced. A step of selectively etching away only
After forming a doped polysilicon film, the doped polysilicon film is etched back to form a gate electrode in the selectively etched region of the SOI layer and inside the trench formed in the insulating film by self-alignment. A method of manufacturing a semiconductor device, comprising: 2. A step of forming a first photoresist pattern on the SOI layer, a step of etching and separating the SOI layer using the first photoresist pattern as a mask, and a step of removing the first photoresist pattern. A step of flattening the step of the SOI layer by etching with an insulating film, and forming a second photoresist pattern on the insulating film, and etching the insulating film using the second photoresist pattern as a mask to form a groove A step of introducing impurities from the groove to a region from a predetermined depth of the SOI layer to a bottom surface of the SOI layer, and a step of removing impurities of the second photoresist pattern only in a region of the SOI layer having impurities introduced. A step of selectively removing the doped polysilicon film, and after forming the doped polysilicon film, etching back the doped polysilicon film. And a step of forming a gate electrode by self-alignment in the selectively etched region of the SOI layer and inside the trench formed in the insulating film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein phosphorus or arsenic ions are used as impurities introduced to a predetermined depth of SOI.