JPH09129877A - Manufacture of semiconductor device, manufacture of insulated gate semiconductor device, and insulated gate semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a source contact region in a self-matching manner without using photolithography, and realize a high level of integration. SOLUTION: By using a first film 12 which was used for forming a trench, a second film 14 covering the trench surface is formed. By etching back the whole surfaces of the first film 12 and the second film 14, and using the difference of the etching rate, only the first film 12 is eliminated, and a contact hole is automatically formed adjacently to the trench. Since the contact hole is formed in an self-matching manner, working precision of the minimum pattern size in photolithography can be realized. As to the second film 14, sufficient film thickness for functioning as an interlayer insulating film can be ensured. The first film 12 and the second film 14 are positioned above the semiconductor substrate surface, so that the stress at the time of film formation and its working is not applied to the semiconductor substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, a method for manufacturing an insulated gate semiconductor device, and an insulated gate semiconductor device.

The present invention is directed to an extremely fine vertical MOS transistor and an IGBT (Insulator) using a U-groove.
ed Gate Bipolar Transisto
It can be applied to the production of r).

[0003]

BACKGROUND ART Vertical MOS transistors and IGBTs are one of the devices that can be expected in the future because they have a high driving ability, occupy a small area on a substrate, and can easily obtain a high degree of integration. Research is being conducted to reduce the size of the device.

A manufacturing process of a vertical MOS transistor using a U groove (hereinafter referred to as a UMOS transistor), which has been studied by the inventors of the present application before the present invention, will be briefly described with reference to FIGS. 37 to 45. 37 to 45 show the cross-sectional structure of the device in each step.

First, as shown in FIG. 37, an n + ^layer 50 is formed.
An oxide film 5 is formed on the surface of a semiconductor substrate having a 0, n ^- layer 510.
40 is formed, and then the body p layer 520 and the source layer 530 are formed by introducing impurities by ion implantation and heat treatment.
Are sequentially formed.

Next, as shown in FIG. 38, the CVD-SiOx film 5 is used as an etching prevention mask during trench processing.
50 is deposited.

Next, as shown in FIG. 39, an opening 560 is formed by patterning the CVD-SiOx film by using the photolithography technique.

Thereafter, as shown in FIG. 40, the silicon substrate is etched by RIE (reactive ion etching) to form a trench 570.

Next, as shown in FIG. 41, the inner wall surface of the trench is thermally oxidized to form a gate oxide film 580, and then an impurity-doped polysilicon film 580 is formed to form R.
Etching and CVD of doped polysilicon by IE
By removing the -SiOx film, the doped polysilicon layer 580 is buried in the trench.

Next, as shown in FIG. 42, an interlayer insulating film 590 is formed by the CVD method.

Next, as shown in FIG. 43, the photoresist 600 is patterned.

Next, as shown in FIG. 44, a source contact is formed by processing the interlayer insulating film 590 by RIE, and subsequently, as shown in FIG. 45, a source electrode 620 and a drain electrode are formed on the front and back surfaces of the semiconductor substrate. 630 is formed.

[0013]

According to the studies made by the present inventors, it has been found that the above-described process has a limit to the miniaturization of the source contact region in the UMOS transistor.

The source contact is formed by forming a contact pattern on the interlayer insulating film by photolithography and then processing by RIE. Therefore, the size of the source region is determined by the processing accuracy of the contact pattern. That is, the degree of miniaturization is determined by the processing accuracy of the photoresist 600 in FIG. 43 described above.

In reality, when forming the source contact, it is necessary to provide an alignment margin (layout margin) so that the gate region is surely protected by the interlayer insulating film in the photolithography. This means that processing can only be performed with a size twice or more the minimum processing size of lithography.

Focusing on such problems, the present invention is directed to a method for manufacturing a semiconductor device in which a source contact region is formed in a self-aligned manner without using photolithography, and further higher integration can be realized, and an insulated gate type semiconductor device. And a insulated gate semiconductor device manufactured by such a method.

[0017]

[Means for Solving the Problems]

(1) In the method of manufacturing a semiconductor device according to the present invention of claim 1, the first film is selectively formed in a desired region on the semiconductor substrate,
A step of etching the semiconductor substrate to form a groove by using the first film as a mask; and a step of forming an insulating layer inside the groove while leaving the first film remaining.
The step of burying the conductive material layer and the etching rate of the first film so as to cover the surface of the first conductive material layer embedded in the groove with reference to the first film. Forming a second film having a small
Common etching is performed on the second film and the second film, and by utilizing the difference in etching rate, the first film is completely removed and the first film is removed while the second film remains. Exposing the surface of the semiconductor substrate located under the first film, and forming a second conductive material layer on the remaining second film and the exposed surface of the semiconductor substrate. And a step of realizing connection between the exposed surface of the semiconductor substrate and the second conductive material layer.

According to the invention of the present claim, a novel element process technology using continuous self-alignment is provided.

That is, by forming a second film that covers the surface of the groove using the first film used for forming the groove, and etching back the entire surface of the first film and the second film. Using the difference in etching rate, only the first film is removed, and a contact hole is automatically opened adjacent to the groove. Since the contact hole is formed in a self-aligning manner, it can be formed with the processing accuracy of the minimum pattern size in photolithography. Therefore, further miniaturization of the device is possible.

Further, if the difference between the etching rates of the first film and the second film is made large, only the first film is completely removed even if the film thicknesses of the first and second films are made thick. There is no problem to remove it. In this case, the second film has a sufficient film thickness to function as an interlayer insulating film, and the device has high reliability.

Furthermore, since the first film and the second film are located above the surface of the semiconductor substrate, stress during film formation and processing is not directly applied to the semiconductor substrate. As a result, the occurrence of crystal defects is suppressed, and the reliability of the device can be secured.

(2) A method of manufacturing a semiconductor device according to a second aspect of the present invention is the method according to the first aspect, wherein the first film is at least a layered film of a silicon nitride film as an upper layer and a polysilicon film as a lower layer. It is characterized in that it is formed by including the second film, and the second film is a silicon oxide film.

In the present invention, the first film is a laminated film including a stacked film of a polysilicon film / Si ₃ N ₄ film, and the second film is Si ₃ N ₄ forming the first film. It is a silicon oxide film (field oxide film) formed by selective oxidation (LOCOS) using the film as a mask.

When etching is performed by RIE, the selection ratio of the polysilicon film to the silicon oxide film is extremely large (for example, 1:50). Therefore, when the entire surface is etched back, the etching of the first film proceeds quickly. The contact hole can be formed by self-alignment.

Further, the thickness of the first film can be adjusted by adjusting the thickness of the polysilicon film, and the film thickness of the field oxide film by LOCOS can be secured within the range of the film thickness of the first film. Therefore, if the thickness of the first film is increased, a field oxide film having a sufficient thickness can be obtained, and the stress at the time of forming the field oxide film does not reach the underlying semiconductor substrate (groove portion) directly. Therefore, the reliability of the interlayer insulating film can be secured and the occurrence of crystal defects can be suppressed.

(3) According to a third aspect of the present invention, there is provided a method of manufacturing an insulated gate semiconductor device, wherein a voltage applied to an insulated gate formed by being electrically insulated from the semiconductor substrate by an insulating film is applied to the inside of the semiconductor substrate. An insulated gate structure is provided to control the induction of charges in the channel formation region to control the formation / non-formation of the channel, and the insulated gate structure is formed so as to cover the inner wall surface of the groove provided in the semiconductor substrate. And a gate layer made of a conductive material embedded in the groove, the method comprising: forming a gate insulating film formed on the surface of the semiconductor substrate; A first-conductivity-type first semiconductor layer, a second-conductivity-type second semiconductor layer provided below the first-semiconductor layer so as to be in contact with the first-semiconductor layer, and a second-conductivity-type second semiconductor layer A first film is selectively formed in a desired region on the surface of a semiconductor substrate having a third semiconductor layer of the first conductivity type provided so as to contact the second semiconductor layer below the semiconductor layer. Forming the groove, etching the semiconductor substrate using the first film as a mask to form a groove penetrating the first and second semiconductor layers and reaching the third semiconductor layer; A step of forming a gate insulating film so as to cover an inner wall surface of the gate, a step of burying polysilicon serving as a gate layer in the groove with the first film left, and the first film. Is used as a mask to selectively oxidize the surface of the polysilicon embedded in the groove, whereby a second film adjacent to the first film and having an etching rate smaller than that of the first film is formed. Before the step of forming the film By performing common etching on the first film and the second film and utilizing the difference in etching rate, the first film is completely removed with the second film remaining. Exposing the surface of the semiconductor substrate located under the first film, and forming an electrode layer on the remaining second film and the exposed surface of the semiconductor substrate, The first semiconductor layer provided on the surface part of the semiconductor substrate while ensuring electrical insulation between the electrode layer and the polysilicon that becomes the gate layer and is buried in the groove by the second film. And a step of realizing connection with the electrode layer.

According to the invention of this claim, the source contact can be formed in a self-aligned manner by utilizing the difference in the etching rate of the material at the time of thickening the interlayer insulating film and processing the multilayer laminated film by RIE. . As a result, since the source contact region can be formed with the processing accuracy of the minimum pattern size in photolithography, the device can be highly integrated, the area of the source region can be reduced, and the resistance component of the substrate can be reduced.

The interlayer insulating film on the surface of the trench gate is formed by oxidizing the surface of the doped polysilicon filling the trench. The film thickness of the interlayer insulating film can be formed within the range of the total film thickness of the multilayer laminated film, so that the film thickness can be increased, and since the silicon substrate is not oxidized, the oxidation-induced stress does not occur in the silicon substrate. That is, when the source contact is processed in a self-aligned manner, the loss of the interlayer insulating film on the gate can be secured, and the generation of crystal defects can be suppressed. As a result, it is possible to manufacture a UMOS that is extremely fine, consumes less power, and has high reliability.

(4) A method of manufacturing an insulated gate semiconductor device according to a fourth aspect of the present invention is the method according to the third aspect.
This film is formed by including at least a layered film of a silicon nitride film as an upper layer and a polysilicon film as a lower layer, and the second film is a silicon oxide film.

With the same operation as the second aspect, the source contact can be formed by self-alignment.

(5) In the method for manufacturing an insulated gate semiconductor device according to a fifth aspect of the present invention, the step of selectively forming the first film in a desired region on the surface of the semiconductor substrate according to the third aspect. After that, a side wall film is formed so as to cover the semiconductor substrate and the first film, and the side wall film is processed by anisotropic etching to expose a part of the surface of the semiconductor substrate. A step of forming a sidewall by leaving the sidewall film on a side surface of the first film, and a step of removing a portion of the surface of the semiconductor substrate by removing the sidewall film A step of performing etching based on the anisotropy of the semiconductor substrate with an alkali etching solution to form a groove including an inclined surface, and thereafter, the first film and the side wall. Is used as a mask to dry-etch the semiconductor substrate, thereby forming a groove connected to the groove including the inclined surface and penetrating the first and second semiconductor layers to reach the third semiconductor layer. And then, the insulated gate semiconductor device is manufactured by each step including the step of forming a gate insulating film according to claim 3.

According to the manufacturing method of the present invention, in addition to the advantages of the manufacturing methods of the third and fourth embodiments, the lateral stress at the time of forming the second film is alleviated by forming the side wall. Moreover, since the upper part of the groove has a taper, it is easy to introduce a film forming gas for burying polysilicon into the groove.

In particular, when the second film is formed by LOCOS, the side walls reduce bird's beaks (extension in the lateral direction), so that the source contact area can be prevented from being reduced.

(6) The insulated gate semiconductor device according to claim 6 of the present invention is the first semiconductor manufactured by the method for manufacturing an insulated gate semiconductor device according to any one of claims 3 to 5. Layer as a source layer, the second semiconductor layer as a channel forming layer, the polysilicon embedded in the trench as a gate layer, and the first conductive layer provided on the semiconductor back surface at a position opposite to the semiconductor front surface. Is a vertical insulated gate semiconductor device in which a fourth type semiconductor layer is used as a drain layer.

An extremely fine vertical MOS transistor of low power consumption and high reliability manufactured by the self-alignment process of claims 3 to 5.

(7) An insulated gate semiconductor device according to a seventh aspect of the present invention is a first semiconductor manufactured by the method for manufacturing an insulated gate semiconductor device according to any one of the third to fifth aspects. The second conductive layer provided on the semiconductor back surface at a position opposite to the semiconductor front surface, the layer serving as an emitter layer, the second semiconductor layer serving as a channel forming layer, the polysilicon embedded in the trench serving as a gate layer. Is a vertical insulated gate semiconductor device having a fourth semiconductor layer of the mold as a collector layer.

An extremely fine, low power consumption and highly reliable IGBT (vertical type bipolar-MOS composite inverted Darlington transistor) manufactured by the self-alignment process according to any one of claims 3 to 5. .

[0038]

Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIGS. 2 to 9 are views for explaining a method (element process technology) for manufacturing a semiconductor device of the present invention, each showing a sectional structure of a device in each step. ing.

First, as shown in FIG. 2, a semiconductor substrate (S
The first film 12 is formed on the (i substrate). As this film, a film having a sufficiently higher etching rate by RIE than a second film described later is used (one example of which is shown in FIG.
This is shown in (a), which will be described later).

Subsequently, as shown in FIG. 3, the first film 12 is formed.
Using the as a mask, the U-grooves 22 and 24 are formed.

Next, as shown in FIG. 4, the inner wall surface of the U groove is oxidized to form oxide films 26 and 28.

Next, as shown in FIG. 5, a polysilicon layer 30 is formed in the U groove and on the first film 12.

Next, as shown in FIG. 6, the polysilicon is etched back to fill the U-grooves with the polysilicon layers 32 and 34.

Next, as shown in FIG. 7, selective oxidation (LOCOS) is performed using the first film 12 as a mask to form a second film (field oxide film) 14. This second
This film has the property that the progress of etching by RIE is much slower than that of the first film.

Next, as shown in FIG. 8, the first film 12 and the second film 14 are simultaneously etched by RIE, and the second film 14 is left by utilizing the difference in etching rate, while The first film 12 is completely removed. As a result, a contact hole for the semiconductor substrate 10 is automatically formed.

Next, as shown in FIG. 9, an electrode 40 is formed and electrically connected to the semiconductor substrate 10. At this time,
The second film 14 functions as an interlayer insulating film. The above is the outline of the process.

Next, the specific contents of the step of automatically forming a contact hole in a semiconductor substrate by RIE utilizing the difference in etching rate (selection ratio) will be described with reference to FIG.

As shown in FIG. 1A, the first film is S
The i ₃ N ₄ film 17 / polysilicon layer 18 / SiO ₂ film 19 is formed of a laminated body (laminated film).
The Si ₃ N ₄ film 17 serves as a mask for forming the second film (field oxide film) by LOCOS of FIG. 7.

In the case of RIE using an etchant for etching silicon, the etching rate of the polysilicon layer 18 is about 50 times the etching rate of the second film (field oxide film). Therefore, it contributes to end the etching of the first film quickly.

Meanwhile, the etching rate of the Si ₃ N ₄ film 17, although the second film (field oxide film) and there is no much difference, the thickness of the Si ₃ N ₄ film 17, the second film (field oxide film ) Is sufficiently thinner than the thickness of. Similarly, the thickness of the lowermost SiO ₂ film 19 forming the first film is sufficiently smaller than the thickness of the second film (field oxide film).

Therefore, when the entire surface of the first and second films is etched back by RIE, the result shown in FIG.
As shown on the left side of (b), for the first film 12,
While the etching proceeds to 1-a, 1-b and 1-c to completely remove it, as shown on the right side of FIG.
The film 14 is etched by 2-a, 2-b, and 2-c (corresponding to 1-a, 1-b, and 1-c, respectively), but the first film 12 is reduced. Even when it is completely removed, it remains with a considerable thickness.

In this manner, the second film 14 having a sufficient thickness as an interlayer insulating film is left, and the contact hole for the semiconductor substrate can be automatically formed at the position closest to the U groove.

As described above, according to the present embodiment, since the contact hole is formed in self-alignment, it is possible to form the contact hole with the processing accuracy of the minimum pattern dimension in photolithography. Therefore, further miniaturization of the device is possible.

Further, if the difference between the etching rates of the first film and the second film is made large, only the first film will be completely removed even if the film thicknesses of the first and second films are made large. There is no problem to remove it. In this case, the second film has a sufficient film thickness to function as an interlayer insulating film, and the device has high reliability.

Further, since the first film and the second film are located above the surface of the semiconductor substrate, stress during film formation and processing is not directly applied to the semiconductor substrate. As a result, the occurrence of crystal defects is suppressed, and the reliability of the device can be secured.

(Second Embodiment) Next, an example of a method of manufacturing an insulated gate semiconductor device (UMOS transistor) using the present invention will be described.

FIG. 10 shows an insulated gate semiconductor device (UMO).
11 is a plan layout view of a main part of the (S transistor), and FIG. 11 is a diagram showing a cross-sectional structure of the device taken along the line AA and the line BB in FIG. 10. 11, the left side view is a cross-sectional view around the gate along the line AA, and the right side view is a cross-sectional view near the U groove along the line BB. Also,
The positions of (A) to (E) of FIG.
It corresponds to each position of (e).

FIG. 12 shows how the UMOS transistor having the structure shown in FIG. 11 is manufactured.
This will be described with reference to FIGS. 12 to 21 are similar to FIG.
22 shows the cross-sectional structure of the device along the line AA, and FIGS. 22 to 27 show the cross-sectional structure of the device along the line BB in FIG.

First, as shown in FIG. 12, an n ⁺ layer 10 is formed.
After forming a thermal oxide film (SiO ₂ film) 130 having a thickness of about 50 nm on the Si substrate having the 0, n ⁻ layer 120, the source layer (n ⁺ ) 290 is formed by impurity implantation by ion implantation and heat treatment.
And a body p layer 280 is formed.

Next, as shown in FIG. 13, a SiO ₂ film 1 is formed.
A polysilicon layer 140 on top of 30 for example about 500 nm
And a Si ₃ N ₄ film 150 of about 200
nm, a CVD-SiOx film 160 of about 250 nm is sequentially stacked and formed. Thereby, the multilayer laminated film (Si
Ox / Si ₃ N ₄ / PolySi / SiO ₂ ) is formed.

Next, as shown in FIG. 14, a pattern is formed with the minimum line width of photolithography, and a multilayer laminated film (SiOx / Si ₃ N ₄ / PolySi / SiO ₂ ) is formed by RIE.
The opening 300 is formed by etching.

Then, as shown in FIG. 15, a trench (U groove) 320 is formed by RIE using the patterned multilayer film as a mask.

Next, as shown in FIG. 16, the trench 32 is formed.
0 is thermally oxidized on the inner wall surface of the gate oxide film 200.
To form

Thereafter, as shown in FIG. 17, an impurity-doped polysilicon layer (doped polysilicon layer) 1
70 is formed. At this time, the cross-sectional structure of the main part of the portion along the line AA in FIG. 10 (partial cross-sectional structure around the gate)
Is as shown in FIG. That is, the doped polysilicon layer 170 is formed so as to cover the upper part of the multilayer laminated film (SiOx film 160, Si ₃ N ₄ film 150, polysilicon 150, SiO ₂ film 130).

Next, as shown in FIG. 23, at the gate portion, the Si ₃ N ₄ film 260 and the CVD-SiOx film 2 are formed.
A laminated film of 70 is formed in a predetermined pattern.

Next, as shown in FIG. 18 and FIG.
Etch back the doped polysilicon layer 170 to form trench 3
Embed the doped polysilicon layer in 20. FIG.
As shown in FIG. 8, Si ₃ N ₄ is formed on the surface of the semiconductor substrate.
The film 150 remains. Also, as shown in FIG.
At the gate portion, a step (L) is generated due to this etch back.

Next, as shown in FIGS. 19 and 25,
A field oxide film 210 is formed with a thickness of about 600 nm by LOCOS using the Si ₃ N ₄ film 150 as a mask.
This field oxide film 210 functions as an interlayer insulating film. . Next, the entire surface is etched by RIE, and the difference in etching rate between the multi-layered film (150, 140, 130) and the field oxide film 210 is utilized to obtain the structure shown in FIG.
As described above, the surface of the silicon substrate immediately below the multilayer laminated film is exposed. As a result, the source contact is automatically formed. That is, the source contact is formed by using the multilayer laminated film formed on the source region without performing mask alignment.
It can be formed in a self-aligned manner by removing with IE.

That is, the field oxide film 210 and Si
Selectivity to the ₃ N ₄ film 150 is about "5", a field oxide film (SiO ₂₎ selectivity between 210 and polysilicon layer 140 is about "70", the field oxide film (SiO ₂₎ 210 and the SiO ₂ film Since the selectivity with respect to 130 is about “1”, the thickness of the thick field oxide film (SiO ₂ ) 210 is reduced by about 100 nm during etching of the three-layer film, and as a result, the thickness of about 500 nm is reduced. At the same time as the etching is completed, the source contact is formed in a self-aligned manner.

Next, as shown in FIG. 26, a gate contact 250 is opened in the gate portion.

Next, as shown in FIGS. 21 and 27,
A gate electrode 220 and a source electrode 230 made of aluminum or the like are formed. Further, the drain electrode 240 is formed on the back surface of the semiconductor substrate.

In this way, the structure shown in FIGS. 10 and 11 is completed. As is clear from FIGS. 11 and 27, the completed device has a multilayer film laminated structure (Si ₃ N ₄ / PolySi / SiO ₂ ) immediately below the gate electrode portion.
However, the structure remains as it is without being removed in the subsequent source contact formation process.

As described above, according to the present embodiment, the source contact is formed by increasing the thickness of the interlayer insulating film and the multilayer laminated film RI.
By utilizing the etching rate difference of the material at E,
Since the source contact region can be formed in a self-aligning manner with high processing accuracy of the minimum pattern dimension in photolithography, high integration of the device and reduction of the area of the source region can be achieved, and the resistance component of the substrate can be reduced. it can.

The interlayer insulating film on the surface of the trench gate is formed by oxidizing the surface of the doped polysilicon filling the trench. The film thickness of the interlayer insulating film can be formed within the range of the total film thickness of the multilayer laminated film, so that the film thickness can be increased, and since the silicon substrate is not oxidized, the oxidation-induced stress does not occur in the silicon substrate. That is, when the source contact is processed in a self-aligned manner, the loss of the interlayer insulating film on the gate can be secured, and the generation of crystal defects can be suppressed. As a result, a highly reliable UMOS transistor with high reliability and low power consumption can be manufactured.

(Third Embodiment) Next, another example of a method of manufacturing an insulated gate semiconductor device (UMOS transistor) according to the present invention will be described with reference to FIGS.

In this embodiment, when a process similar to that of the second embodiment is performed using a (100) plane Si substrate, a sidewall made of a CVD film is formed on the side surface after the processing of the multilayer laminated film. And a step of forming a V groove by silicon anisotropic etching using an alkali etching solution.

A detailed description will be given below.

After the semiconductor substrate is processed by the steps shown in FIGS. 12 to 14, first, as shown in FIG. 28, a CVD-SiOx film 400 for sidewalls is formed.

Next, as shown in FIG. 29, etching by RIE is performed to form sidewalls 410.

Next, as shown in FIG. 30, a V groove 420 is formed by alkali etching.

Next, as shown in FIG. 31, a trench 440 is formed by RIE.

Next, as shown in FIG. 32, the doped polysilicon 170 is embedded in the U groove.

Next, as shown in FIG. 33, the surface of the doped polysilicon 170 is locally oxidized to form the field oxide film 2.
Form 10.

Next, as shown in FIG. 34, the entire surface is etched back by RIE to form the source contact while leaving the field oxide film 210.

Next, as shown in FIG. 35, the source electrode 230 and the drain electrode 240 are formed on the front and back surfaces of the semiconductor substrate, respectively, and the device is completed.

In the device of this embodiment, in particular, the presence of the sidewalls 410 alleviates the lateral stress (generation of bird's beaks) when the field oxide film 210 is formed by LOCOS, so that sufficient source contact is achieved. In addition to being able to secure the area, the V groove formed by alkali etching has a taper, so that a film forming gas for burying polysilicon is easily introduced into the groove.

(Fourth Embodiment) FIG. 36A shows an IGBT (Insulator) according to a fourth embodiment of the present invention.
ed Gate Bipolar Transisto
r) shows a sectional structure of the device, and (b) shows an equivalent circuit thereof.

[0088] IGBT is the lowest layer of the n ⁺ -type semiconductor layer 100 of the semiconductor substrate shown in FIG. 11 or the like, P ⁺ semiconductor layer 1
It is formed by replacing with 05, and as shown in FIG. 36B, in terms of a circuit, an inverted Darlington transistor having a MOS top is formed.

As shown in FIG. 36A, the doped polysilicon layer 170 formed in the groove serves as a gate (G), the electrode 232 formed on the front surface of the substrate serves as an emitter electrode, and is formed on the back surface of the substrate. The electrode 242 serving as a collector electrode.

Such an IGBT can be formed in the same manner as the MOSFET by the above-described process, and the manufactured device has high integration, low consumption electrodes, and high reliability.

[0091]

[Brief description of the drawings]

1A and 1B are views for explaining the features of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a sectional view of a device showing a first step of the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a sectional view of a device showing a second step of the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a sectional view of a device showing a third step of the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a sectional view of a device showing a fourth step of the method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a device sectional view showing a fifth step of the method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a sectional view of a device showing a sixth step of the method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a device sectional view showing a seventh step of the method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a sectional view of a device showing an eighth step of the method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a plan layout view of a main part of the insulated gate semiconductor device of the present invention.

11 is a diagram showing an example of a cross-sectional structure of the device taken along the line AA and the line BB in FIG.

12 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA of FIG. 10 in the first step. is there.

13 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA in FIG. 10 in the second step. FIG. is there.

14 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA in FIG. 10 in the third step. FIG. is there.

15 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, showing the cross-sectional structure of the device along the line AA in FIG. 10 in the fourth step. is there.

16 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, and is a diagram showing a cross-sectional structure of the device along the line AA in FIG. 10 in a fifth step. FIG. is there.

FIG. 17 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA in FIG. 10 in a sixth step. is there.

FIG. 18 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, showing the cross-sectional structure of the device along the line AA in FIG. 10 in the seventh step. is there.

FIG. 19 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, showing the cross-sectional structure of the device along the line AA in FIG. 10 in the eighth step. is there.

20 is a diagram for explaining an example of the method of manufacturing the device shown in FIGS. 10 and 11, and is a diagram showing a cross-sectional structure of the device along the line AA in FIG. 10 in a ninth step. FIG. is there.

FIG. 21 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA in FIG. 10 in the tenth step. is there.

22 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, and a diagram showing a cross-sectional structure of the device along the line BB in FIG. 10 in the step shown in FIG. Is.

23 is a diagram for explaining an example of the method of manufacturing the device shown in FIGS. 10 and 11, and is a cross-sectional view taken along the line BB of FIG. 10 in a step intermediate between the step of FIG. 17 and the step of FIG.
It is a figure which shows the cross-section of a device along a line.

24 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, and a diagram showing a cross-sectional structure of the device along the line BB in FIG. 10 in the step shown in FIG. 18; Is.

25 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, and a diagram showing a cross-sectional structure of the device along the line BB in FIG. 10 in the step shown in FIG. 19; Is.

FIG. 26 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, and in a step intermediate between the step of FIG. 20 and the step of FIG.
It is a figure which shows the cross-section of a device along a B line.

27 is a diagram for explaining an example of the method for manufacturing the device shown in FIGS. 10 and 11, and a diagram showing a cross-sectional structure of the device along the line BB in FIG. 10 in the step shown in FIG. 21. FIG. Is.

28 is a diagram for explaining another example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA of FIG. 10 in the first step. FIG. It is a figure.

29 is a diagram for explaining another example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA of FIG. 10 in the second step. FIG. It is a figure.

30 is a diagram for explaining another example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA in FIG. 10 in the third step. FIG. It is a figure.

31 is a diagram for explaining another example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA in FIG. 10 in the fourth step. FIG. It is a figure.

32 is a diagram for explaining another example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA of FIG. 10 in the fifth step. It is a figure.

FIG. 33 is a diagram for explaining another example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA in FIG. 10 in the sixth step. It is a figure.

34 is a diagram for explaining another example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA of FIG. 10 in the seventh step. FIG. It is a figure.

FIG. 35 is a diagram for explaining another example of the method for manufacturing the device shown in FIGS. 10 and 11, showing a cross-sectional structure of the device along the line AA in FIG. 10 in the eighth step. It is a figure.

FIG. 36 (a) is a sectional view of an IGBT device manufactured by the manufacturing method of the present invention, and FIG. 36 (b) is an equivalent circuit diagram thereof.

FIG. 37: UM examined by the present inventor before the present invention
It is a figure which shows the manufacturing method of OS, and is sectional drawing of the device in a 1st process.

FIG. 38: UM examined by the present inventor before the present invention
It is a figure which shows the manufacturing method of OS, and is sectional drawing of the device in a 2nd process.

FIG. 39: UM examined by the present inventor before the present invention
It is a figure which shows the manufacturing method of OS, and is sectional drawing of the device in a 3rd process.

FIG. 40: UM examined by the present inventor before the present invention
It is a figure which shows the manufacturing method of OS, and is sectional drawing of the device in a 4th process.

FIG. 41: UM examined by the present inventor before the present invention
It is a figure which shows the manufacturing method of OS, and is sectional drawing of the device in a 5th process.

FIG. 42: UM examined by the inventor before the present invention
It is a figure which shows the manufacturing method of OS, and is sectional drawing of the device in a 6th process.

FIG. 43: UM examined by the inventor before the present invention
It is a figure which shows the manufacturing method of OS, and is sectional drawing of the device in a 7th process.

FIG. 44: UM examined by the present inventor before the present invention
It is a figure which shows the manufacturing method of OS, and is sectional drawing of the device in an 8th process.

FIG. 45: UM examined by the present inventor before the present invention
It is a figure which shows the manufacturing method of OS, and is sectional drawing of the device in a 9th process.

[Explanation of symbols]

10 Silicon Substrate 12 First Film (Si ₃ N ₄ Film / Polysilicon Film / Oxide Film Stacked Film) 14 Second Film (SiO ₂ Film) 17 Si ₃ N ₄ Film 18 Polysilicon Layer 19 SiO ₂ Film

Claims (7)

[Claims] 1. A step of selectively forming a first film in a desired region on a semiconductor substrate and etching the semiconductor substrate using the first film as a mask to form a groove, The step of forming an insulating layer inside the groove and burying a first conductive material layer in the state where the film of FIG. 2 remains, and the step of filling the inside of the groove with the first film as a reference. Forming a second film having an etching rate smaller than that of the first film so as to cover the surface of the first conductive material layer; and etching common to the first film and the second film. Of the semiconductor substrate located below the first film by removing the first film with the second film left by using the difference in etching rate. Exposing the surface, and the remaining on the second film and the A step of forming a second conductive material layer on the exposed surface of the semiconductor substrate and realizing a connection between the exposed surface of the semiconductor substrate and the second conductive material layer. And a method for manufacturing a semiconductor device. 2. The first film according to claim 1, wherein the first film is formed to include at least a stacked film of a silicon nitride film which is an upper layer and a polysilicon film which is a lower layer, and the second film is a silicon oxide film. A method of manufacturing a semiconductor device, comprising: 3. A voltage applied to an insulated gate formed by being electrically insulated from a semiconductor substrate by an insulating film,
The semiconductor device comprises an insulated gate structure for controlling charge induction in a channel formation region in the semiconductor substrate to control channel formation / non-formation, and the insulated gate structure is an inner wall surface of a groove provided in the semiconductor substrate. A method of manufacturing an insulated gate semiconductor device, comprising: a gate insulating film formed so as to cover the gate; and a gate layer made of a conductive material buried in the trench, the method comprising: And a second semiconductor layer of the second conductivity type provided under the first semiconductor layer so as to be in contact with the first semiconductor layer. The first semiconductor layer provided under the second semiconductor layer so as to be in contact with the second semiconductor layer.
A step of selectively forming a first film in a desired region of a surface of a semiconductor substrate having a conductive third semiconductor layer; and etching the semiconductor substrate using the first film as a mask, Forming a groove penetrating the first and second semiconductor layers to reach the third semiconductor layer; forming a gate insulating film so as to cover the inner wall surface of the groove; and the first film. In a state of remaining, the step of filling the inside of the groove with polysilicon to be a gate layer, and using the first film as a mask, selectively select the surface of the polysilicon filled in the inside of the groove. To form a second film adjacent to the first film and having an etching rate smaller than that of the first film, and for the first film and the second film. Perform common etching and Difference is used to remove the first film entirely and expose the surface of the semiconductor substrate located under the first film while leaving the second film remaining. And a step of forming an electrode layer on the remaining second film and on the exposed surface of the semiconductor substrate, thereby forming the gate layer filled with the second film in the groove. While ensuring electrical insulation between the electrode layer and
And a step of realizing connection between the first semiconductor layer provided on the surface portion of the semiconductor substrate and the electrode layer, the method for manufacturing an insulated gate semiconductor device. 4. The third film according to claim 3, wherein the first film includes at least a layered film of a silicon nitride film which is an upper layer and a polysilicon film which is a lower layer, and the second film is a silicon oxide film. And a method of manufacturing an insulated gate semiconductor device. 5. The film for sidewalls which covers the semiconductor substrate and the first film after the step of selectively forming the first film in a desired region of the surface of the semiconductor substrate according to claim 3. Is formed and the film for the sidewall is processed by anisotropic etching to expose a part of the surface of the semiconductor substrate, while leaving the film for the sidewall on the side surface of the first film. The step of forming a wall, and the portion where the film for the sidewall is removed and a part of the surface of the semiconductor substrate is exposed is etched based on the anisotropy of the semiconductor substrate with an alkali etching solution to form a slope And a step of forming a groove containing the same, and thereafter, the semiconductor substrate is etched by dry etching using the first film and the sidewall as a mask. And thereby connecting to the groove including the inclined surface and penetrating the first and second semiconductor layers to form a third groove.
Forming a groove reaching the semiconductor layer, and thereafter producing an insulated gate type semiconductor device by each step including the step of forming a gate insulating film according to claim 3. Type semiconductor device manufacturing method. 6. A method for manufacturing an insulated gate semiconductor device according to any one of claims 3 to 5,
The first semiconductor layer is used as a source layer, the second semiconductor layer is used as a channel formation layer, polysilicon embedded in the trench is used as a gate layer, and the semiconductor back surface is provided at a position opposite to the semiconductor front surface. A vertical insulated gate semiconductor device having a fourth semiconductor layer of the first conductivity type as a drain layer. 7. An insulating gate type semiconductor device manufacturing method according to claim 3,
The first semiconductor layer is used as an emitter layer, the second semiconductor layer is used as a channel formation layer, the polysilicon embedded in the trench is used as a gate layer, and the semiconductor layer is provided on the semiconductor back surface opposite to the semiconductor front surface. A vertical insulated gate semiconductor device having a second conductive fourth semiconductor layer as a collector layer.