JPH0669408A - Semiconductor device for high-frequency power amplification - Google Patents

Semiconductor device for high-frequency power amplification

Info

Publication number
JPH0669408A
JPH0669408A JP22125192A JP22125192A JPH0669408A JP H0669408 A JPH0669408 A JP H0669408A JP 22125192 A JP22125192 A JP 22125192A JP 22125192 A JP22125192 A JP 22125192A JP H0669408 A JPH0669408 A JP H0669408A
Authority
JP
Japan
Prior art keywords
semiconductor device
frequency power
power amplification
high frequency
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22125192A
Other languages
Japanese (ja)
Inventor
Iwamichi Kamishiro
岩道 神代
Masahito Numanami
雅仁 沼波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP22125192A priority Critical patent/JPH0669408A/en
Publication of JPH0669408A publication Critical patent/JPH0669408A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Microwave Amplifiers (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To facilitate circuit pattern design on a circuit board by disposing at multidirectional positions lead terminals which have been drawn in one direction. CONSTITUTION:A circuit board 3 is mounted on a beat dissipation plate 4 4. Mounted on the circuit board 3 are the inner portions of lead terminals 2, a semiconductor chip 5 for amplification, a circuit element 6, connecting tabs 7 and the like, which are electrically connected to the circuit board 3. The circuit board 3 is sealed by the board 4 and a sealing cap 9. In addition, the semiconductor chip 5 is electrically connected to the connecting tabs 7 through bonding wires 8. Furthermore, lead terminals 2 of different functions are disposed at multidirectional portions. Since this construction can facilitate the design of a circuit pattern 10 of a semiconductor device for high-frequency power amplification 1 and obviate cross wirings such as bias lines, the circuit pattern 10 can be simplified.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高周波電力増幅用半導
体装置(増幅用混成集積回路装置)に関し、特に、小型
化、高密度化が可能な高周波電力増幅用半導体装置に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for high frequency power amplification (a hybrid integrated circuit device for amplification), and more particularly to a semiconductor device for high frequency power amplification which can be miniaturized and increased in density.

【0002】[0002]

【従来の技術】従来、高周波電力増幅用半導体装置(増
幅用混成集積回路装置)101は、図5(外観構成を示す
斜視図)に示すように、放熱板に取り付ける必要上、単
一方向にリード端子102を配設している。尚、リード
端子102(Pin)は入力ピン、リード端子102(Vap
c)はコントロールピン、リード端子102(Vdd)は電
源ピン、リード端子102(Pout)は出力ピンである。
そして、高周波電力増幅用半導体装置101は、図6
(回路構成を示す模式図)に示すように、リード端子1
02を一方向から引き出しているため、配線基板上の回
路パターン103にクロス配線(交差配線)104を有す
る。尚、図6中、105は増幅用半導体素子である。
2. Description of the Related Art Conventionally, a semiconductor device for high frequency power amplification (hybrid integrated circuit device for amplification) 101 needs to be attached to a heat sink as shown in FIG. Lead terminals 102 are provided. The lead terminal 102 (Pin) is an input pin, and the lead terminal 102 (Vap)
c) is a control pin, lead terminal 102 (Vdd) is a power supply pin, and lead terminal 102 (Pout) is an output pin.
The semiconductor device 101 for high frequency power amplification is shown in FIG.
As shown in (schematic diagram showing circuit configuration), the lead terminal 1
Since 02 is drawn from one direction, the circuit pattern 103 on the wiring substrate has a cross wiring (cross wiring) 104. In FIG. 6, reference numeral 105 is an amplifying semiconductor element.

【0003】[0003]

【発明が解決しようとする課題】本発明者は、前述の高
周波電力増幅用半導体装置(増幅用混成集積回路装置)1
01について検討した結果、以下の問題点を見い出し
た。
SUMMARY OF THE INVENTION The present inventor has made the above-mentioned semiconductor device for high frequency power amplification (amplification hybrid integrated circuit device) 1
As a result of examining No. 01, the following problems were found.

【0004】(1)クロス配線104による浮遊容量が
生じて発振したり、信号の歪みを生じたりするという問
題があった。
(1) There has been a problem that stray capacitance is generated by the cross wiring 104, causing oscillation and signal distortion.

【0005】(2)パワーアップのため多段にする必要
があるが、その際に、浮遊容量を考慮すると、多段にす
ることができない。したがって、半導体素子、リード端
子、抵抗体等の配設面積に制限があり、小型化を図るこ
とができないという問題があった。
(2) It is necessary to have multiple stages for power-up, but in that case, if the stray capacitance is taken into consideration, it is not possible to have multiple stages. Therefore, there is a problem that the layout area of the semiconductor element, the lead terminal, the resistor, etc. is limited, and the size cannot be reduced.

【0006】本発明の目的は、高周波電力増幅用半導体
装置の配線基板上の回路パターンを簡略化することが可
能な技術を提供することにある。
An object of the present invention is to provide a technique capable of simplifying a circuit pattern on a wiring board of a semiconductor device for high frequency power amplification.

【0007】本発明の他の目的は、高周波電力増幅用半
導体装置の小型化を図ることが可能な技術を提供するこ
とにある。
Another object of the present invention is to provide a technique capable of reducing the size of a semiconductor device for high frequency power amplification.

【0008】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0009】[0009]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。
Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

【0010】すなわち、高周波電力増幅用半導体装置に
おいて、機能の異なるリード端子を多方向の位置に配設
した高周波電力増幅用半導体装置である。
That is, it is a semiconductor device for high frequency power amplification in which lead terminals having different functions are arranged at positions in multiple directions.

【0011】[0011]

【作用】前述した手段によれば、一方向から引き出して
いたリード端子を多方向の位置に配設することにより、
回路基板(アートワーク)上の回路パターンの設計を容易
にし、バイアスライン等のクロス配線(交差配線)を廃止
できるので、配線基板上の回路パターンを簡略化するこ
とができると共に、高周波電力増幅用半導体装置の小型
化を図ることができる。
According to the above-mentioned means, by arranging the lead terminals drawn from one direction at the positions in multiple directions,
Since the circuit pattern on the circuit board (artwork) can be easily designed and cross wiring (cross wiring) such as bias lines can be eliminated, the circuit pattern on the wiring board can be simplified and used for high frequency power amplification. It is possible to reduce the size of the semiconductor device.

【0012】[0012]

【実施例】以下、図面を参照して、本発明の実施例を詳
細に説明する。
Embodiments of the present invention will now be described in detail with reference to the drawings.

【0013】図1は、本発明の一実施例である高周波電
力増幅用半導体装置の外観構成を示す斜視図、図2は、
図1に示すA−A切断線で切った断面図、図3は、前記
高周波電力増幅用半導体装置の回路構成を示す模式図で
ある。
FIG. 1 is a perspective view showing the external configuration of a semiconductor device for high frequency power amplification which is an embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view taken along the line AA shown in FIG. 1, and FIG. 3 is a schematic view showing a circuit configuration of the semiconductor device for high frequency power amplification.

【0014】図1及び図2において、1は高周波電力増
幅用半導体装置、2はリード端子、3は回路基板、4は
放熱板、5は増幅用半導体素子、6はコンデンサー、抵
抗、コイル等の回路素子、7は複数個の電極パッドを配
置した接続用タブ、8はボンディングワイヤ、9は封止
用キャップである。尚、リード端子2(Pin)は入力ピ
ン、リード端子2(Vapc)はコントロールピン、リード
端子2(Vdd)は電源ピン、リード端子2(Pout)は出力
ピンである。
In FIGS. 1 and 2, 1 is a semiconductor device for high frequency power amplification, 2 is a lead terminal, 3 is a circuit board, 4 is a heat sink, 5 is an amplification semiconductor element, 6 is a capacitor, a resistor, a coil or the like. A circuit element, 7 is a connection tab in which a plurality of electrode pads are arranged, 8 is a bonding wire, and 9 is a sealing cap. The lead terminal 2 (Pin) is an input pin, the lead terminal 2 (Vapc) is a control pin, the lead terminal 2 (Vdd) is a power supply pin, and the lead terminal 2 (Pout) is an output pin.

【0015】図1及び図2に示すように、本実施例の高
周波電力増幅用半導体装置1は、放熱板4上に回路基板
3を塔載している。この回路基板3上にはリード端子2
のインナー部、増幅用半導体素子5、回路素子6、接続
用タブ7等が塔載され、これらは回路基板3に電気的に
接続される。回路基板3は、放熱板4及び封止用キャッ
プ9で封止される。尚、増幅用半導体素子5は、ボンデ
ィングワイヤ8を介して接続用タブ7に電気的に接続さ
れる。
As shown in FIGS. 1 and 2, in the semiconductor device 1 for high frequency power amplification of this embodiment, a circuit board 3 is mounted on a heat dissipation plate 4. The lead terminals 2 are provided on the circuit board 3.
The inner part, the amplification semiconductor element 5, the circuit element 6, the connection tab 7 and the like are mounted on the tower, and these are electrically connected to the circuit board 3. The circuit board 3 is sealed with the heat dissipation plate 4 and the sealing cap 9. The amplification semiconductor element 5 is electrically connected to the connection tab 7 via the bonding wire 8.

【0016】前記高周波電力増幅用半導体装置1は、機
能の異なるリード端子2を多方向の位置に配設してい
る。
In the semiconductor device 1 for amplifying high frequency power, the lead terminals 2 having different functions are arranged in multiple directions.

【0017】このように構成することにより、図3に示
すように、高周波電力増幅用半導体装置1の回路パター
ン10の設計を容易にし、バイアスライン等のクロス配
線を廃止できるので、回路基板3上の回路パターン10
を簡略化することができると共に、高周波電力増幅用半
導体装置1の小型化を図ることができる。
With this structure, as shown in FIG. 3, the circuit pattern 10 of the semiconductor device 1 for high frequency power amplification can be easily designed, and cross wiring such as bias lines can be eliminated. Circuit pattern 10
Can be simplified, and the semiconductor device 1 for high frequency power amplification can be downsized.

【0018】図4は、本発明の応用例であるADCシス
テムの概略構成を説明するための図であり、(a)は多
段式高周波電力増幅用半導体装置の回路構成を示す模式
図、(b)はADCシステムの概略構成を示す模式図であ
る。
FIG. 4 is a diagram for explaining a schematic configuration of an ADC system which is an application example of the present invention. FIG. 4A is a schematic diagram showing a circuit configuration of a semiconductor device for multistage high frequency power amplification, and FIG. ) Is a schematic diagram showing a schematic configuration of an ADC system.

【0019】図4において、11は多段式の回路パター
ン、11Aはアナログ用の多段式高周波電力増幅用半導
体装置、11Bはデジタル用の多段式高周波電力増幅用
半導体装置、12はリード端子、13は増幅用半導体素
子、14はマザーボードである。尚、リード端子12
(Pin)は入力ピン、リード端子12(Vapc)はコントロ
ールピン、リード端子12(Vdd)は電源ピン、リード端
子12(Pout)は出力ピンである。
In FIG. 4, 11 is a multistage circuit pattern, 11A is a multistage high frequency power amplification semiconductor device for analog, 11B is a multistage high frequency power amplification semiconductor device for digital, 12 is a lead terminal, and 13 is The amplifying semiconductor element 14 is a mother board. The lead terminal 12
(Pin) is an input pin, the lead terminal 12 (Vapc) is a control pin, the lead terminal 12 (Vdd) is a power supply pin, and the lead terminal 12 (Pout) is an output pin.

【0020】例えばADCシステムのようにアナログ用
の高周波電力増幅用半導体装置11Aとデジタル用の高
周波電力増幅用半導体装置11Bとが必要な場合には、
図4に示すように、高周波電力増幅用半導体装置11A
のリード端子12と高周波電力増幅用半導体装置11A
のリード端子12とのリード配置を逆くにしてマザーボ
ード13に実装し、マザーボード13の実装効率を向上
することができる。
For example, when an analog high frequency power amplifying semiconductor device 11A and a digital high frequency power amplifying semiconductor device 11B are required as in an ADC system,
As shown in FIG. 4, the semiconductor device 11A for high frequency power amplification
Lead terminal 12 and semiconductor device 11A for high frequency power amplification
It is possible to improve the mounting efficiency of the motherboard 13 by reversing the lead arrangement with respect to the lead terminal 12 and mounting it on the motherboard 13.

【0021】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。
As described above, the inventions made by the present inventor are
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

【0022】[0022]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。
The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【0023】一方向から引き出していたリード端子を多
方向の位置に配設することにより、高周波電力増幅用半
導体装置の回路パターンの設計を容易にし、バイアスラ
イン等のクロス配線を廃止できるので、回路基板上の回
路パターンを簡略化することができると共に、高周波電
力増幅用半導体装置の小型化を図ることができる。
By arranging the lead terminals drawn out from one direction at positions in many directions, the circuit pattern of the semiconductor device for high frequency power amplification can be easily designed and the cross wiring such as the bias line can be eliminated. The circuit pattern on the substrate can be simplified and the semiconductor device for high frequency power amplification can be downsized.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の一実施例である高周波電力増幅用半
導体装置の外観構成を示す斜視図、
FIG. 1 is a perspective view showing an external configuration of a semiconductor device for high frequency power amplification which is an embodiment of the present invention,

【図2】 図1に示すA−A切断線で切った断面図、FIG. 2 is a sectional view taken along the line AA shown in FIG.

【図3】 前記高周波電力増幅用半導体装置の回路構成
を示す模式図、
FIG. 3 is a schematic diagram showing a circuit configuration of the semiconductor device for high frequency power amplification,

【図4】 本発明の応用例であるADCシステムの概略
構成を説明するための図、
FIG. 4 is a diagram for explaining a schematic configuration of an ADC system that is an application example of the present invention;

【図5】 従来の高周波電力増幅用半導体装置の外観構
成を示す斜視図、
FIG. 5 is a perspective view showing an external configuration of a conventional semiconductor device for high frequency power amplification,

【図6】 従来の高周波電力増幅用半導体装置の回路構
成を示す模式図。
FIG. 6 is a schematic diagram showing a circuit configuration of a conventional semiconductor device for high frequency power amplification.

【符号の説明】[Explanation of symbols]

1…高周波電力増幅用半導体装置、2…リード端子、3
…回路基板、4…放熱板、5…増幅用半導体素子、6…
回路素子、7…接続用タブ、8…ボンディングワイヤ、
9…封止用キャップ、10回路パターン、多段式回路パ
ターン、11A…アナログ用の多段式高周波電力増幅用
半導体装置、11B…デジタル用の多段式高周波電力増
幅用半導体装置、12…リード端子、13…増幅用半導
体素子、14…マザーボード。
1 ... Semiconductor device for high frequency power amplification, 2 ... Lead terminal, 3
... Circuit board, 4 ... Heat sink, 5 ... Amplifying semiconductor element, 6 ...
Circuit element, 7 ... Connection tab, 8 ... Bonding wire,
9 ... Sealing cap, 10 circuit pattern, multistage circuit pattern, 11A ... Analog multistage high frequency power amplification semiconductor device, 11B ... Digital multistage high frequency power amplification semiconductor device, 12 ... Lead terminal, 13 ... semiconductor element for amplification, 14 ... motherboard.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 高周波電力増幅用半導体装置において、
機能の異なるリード端子を多方向の位置に配設したこと
を特徴とする高周波電力増幅用半導体装置。
1. A semiconductor device for high frequency power amplification, comprising:
A semiconductor device for high frequency power amplification, characterized in that lead terminals having different functions are arranged at positions in multiple directions.
JP22125192A 1992-08-20 1992-08-20 Semiconductor device for high-frequency power amplification Pending JPH0669408A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22125192A JPH0669408A (en) 1992-08-20 1992-08-20 Semiconductor device for high-frequency power amplification

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22125192A JPH0669408A (en) 1992-08-20 1992-08-20 Semiconductor device for high-frequency power amplification

Publications (1)

Publication Number Publication Date
JPH0669408A true JPH0669408A (en) 1994-03-11

Family

ID=16763846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22125192A Pending JPH0669408A (en) 1992-08-20 1992-08-20 Semiconductor device for high-frequency power amplification

Country Status (1)

Country Link
JP (1) JPH0669408A (en)

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US11388984B2 (en) 2017-12-20 2022-07-19 The Gillette Company Llc Oral care implement
US11399622B2 (en) 2017-12-20 2022-08-02 The Gillette Company Llc Oral care implement
US11400627B2 (en) 2018-02-09 2022-08-02 The Gillette Company Llc Method for manufacturing an oral care implement
US11553782B2 (en) 2018-02-09 2023-01-17 The Gillette Company Llc Manual oral care implement
US11388985B2 (en) 2018-02-09 2022-07-19 The Gillette Company Llc Connector for a manual oral care implement
US11865748B2 (en) 2018-02-09 2024-01-09 The Gillette Company Llc Connector
US11382409B2 (en) 2018-02-09 2022-07-12 The Gillette Company Llc Connector for a manual oral care implement
US11571060B2 (en) 2018-09-03 2023-02-07 The Gillette Company Llc Head for an oral-care implement and a kit comprising such head
US11659922B2 (en) 2018-09-03 2023-05-30 The Gillette Company, LLC. Head for an oral-care implement and a kit comprising such head
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US11672633B2 (en) 2019-11-06 2023-06-13 The Gillette Company, LLC. Handle for an electrically operated personal care implement

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