JP2001102460A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a chip of a power amplifier for a dual band portable terminal. SOLUTION: On a single chip, first and second power amplifiers are formed, and they comprise a multi-emitter bipolar transistor, respectively. A first unit transistor of the first power amplifier and a second unit transistor of the second power amplifier are substantially alternately placed in a plane.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier using a bipolar transistor.

[0002]

2. Description of the Related Art With the globalization of portable terminals, a dual band (Dual Ban) operating at two kinds of frequencies has been developed.
d) The demands of the terminals are increasing. In such a terminal, usually, two types of transmission power amplifiers are separately incorporated and used separately for respective frequencies. However, with recent demands for miniaturization and cost reduction of terminals, power amplifiers are also required to have miniaturization and low cost. Conventionally, in response to such demands, two types of power amplifier chips are integrated into one module or molded package, and further, two types of power amplifiers are integrated on the same chip. I have. However, such a power amplifier is effective for reducing the size and mounting cost of the module, but the size of the semiconductor chip is as shown in FIG.
Even if the power amplifiers are separated as shown in FIG.
Even when the same chip is used, the total chip size does not change, so that the chip cost cannot be reduced. That is, FIG. 9A shows an example in which the upper 800 MHz power amplifier and the lower 1900 MHz power amplifier are configured as separate chips. These figures also show that the last transistor portion occupies a large area on each chip. On the other hand, FIG. 9B shows an example in which the two power amplifiers are incorporated on one chip. However, it cannot be said that the chip size of (b) is smaller than that of (a).

The arrangement of transistors in the last stage in the related art will be described below. The transistors at the last stage in both the 800 and 1900 MHz power amplifiers were arranged as shown in FIGS. That is, the transistors Tr are multi-emitter bipolar transistors, and are arranged, for example, at a horizontal interval of 80 μm and a vertical interval of 100 μm as shown in FIG. This is from the viewpoint of suppressing heat generation. That is, thermal interference between transistors is suppressed, and the overall thermal resistance is reduced. Thus, the overall area is considerably larger than the size of each transistor Tr. The bases B of these transistors Tr are commonly connected in a horizontal row, and the collectors C as outputs are all connected to the output Pout as common. The emitters E of these transistors Tr are commonly connected as shown in FIG. 10 and are connected to the ground GND. As mentioned above, this arrangement is for 800 and 1900 MHz,
The same applies to the case of being formed on two chips and the case of being formed on one chip, so that the area as a whole does not change. In particular, when a compound semiconductor such as GaAs is used as an amplifier, it is important to reduce the chip cost.

[0004]

As described above, as described above,
Although it is required to reduce the chip cost by downsizing the chip as a whole of the power amplifiers of the two types of frequencies, it has not been achieved in practice.

[0005] The present invention has been made in view of the above,
The purpose is Dual Ba operating at two different frequencies.
It is an object of the present invention to provide a method for realizing a reduction in chip cost in a power amplifier for nd portable terminals.

[0006]

According to the present invention, there is provided a semiconductor device comprising:
A first power amplifier and a second power amplifier are formed on a single chip, and the first and second power amplifiers are each formed by a multi-emitter bipolar transistor. And the second unit transistors in the second power amplifier are arranged substantially alternately in a plane.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention are simply as follows. Two multi-emitter bipolar transistor high frequency power amplifiers connected in parallel are integrated in the same semiconductor chip. Then, the individual unit transistors of the two types of power amplifiers are alternately arranged as shown in FIGS. 1 and 2, their emitter electrodes are electrically connected in common, and the base and the collector are connected separately. This allows
When one power amplifier is operating, the other power amplifier assists in heat dissipation. And with this configuration, the chip size of the dual band power amplifier was reduced.

Hereinafter, embodiments will be described in more detail.

FIG. 3 shows a circuit diagram of a 1-W class two-stage dual band power amplifier using an InGaP / GaAs heterojunction multi-emitter bipolar transistor.

The upper part shows an 800 MHz band power amplifier, and the lower part shows a 1900 MHz band power amplifier. In the lower power amplifier, the input side is an input matching circuit 11.
Through to the circuitry on the chip. That is, it is connected to the front-stage (first-stage) transistor 12, the inter-stage matching circuit 13, and the rear-stage (last-stage) transistor 14. The interstage transistor 14 is connected to an output matching circuit 15 outside the chip. The power amplifier circuit in the upper stage has substantially the same configuration as that in the lower stage. Furthermore, chip 1
0, the external voltage Vp (for 800 MHz), V
From the base voltage bias circuit 16 operating at p (for 1900 MHz), the front-stage transistors 12, 12, the rear-stage transistors 14,
14 are each supplied with a bias voltage. Since this bias circuit is well known, a detailed description is omitted here. That is, on this chip 10, 800M
In each of the Hz band and the 1900 MHz band, the front-stage transistors 12, 12, the inter-stage matching circuits 13, 13, the rear-stage transistors 14, 14, and the base voltage bias circuit 1
6 are integrated. The input matching circuits 11, 11 and the output matching circuits 15, 15 are externally provided. FIG.
Is an example of the circuit of FIG.

The circuit of FIG. 3 is realized in the first embodiment of the present invention as shown in FIG. That is, in the present embodiment, the entire area of the last-stage transistor in the two-band power amplifier is obtained as having approximately the same area as the power amplifier of one band of the conventional last-stage transistor shown in FIG. ing. In other words, the area is about half that of the conventional one.

Details of the last-stage transistor shown in FIG. 5 are shown in FIGS. That is, as can be seen particularly from FIG. 2, the transistors (unit transistors) Tr (1) for 800 MHz and the transistors (unit transistors) Tr (2) for 1900 MHz are alternately arranged in the horizontal direction. Therefore, although the interval between the two transistors Tr (1) and Tr (2) in different bands is only 40 μm, the transistors Tr (1) and Tr
(1) The interval between Tr (2) and Tr (2) is 2
It is twice as large as 80 μm, and there is no problem of heat generation.
That is, the transistors Tr (1) and Tr
(2) does not operate at the same time, and only the transistor in one of the bands operates. Therefore, even if the transistors in different bands are attached to each other, there is no problem in operation if the interval between the transistors in the same band is sufficient. The present invention has independently learned this fact and has accomplished the present invention.

As can be seen from FIG. 2, the bases and the collectors of transistors in the same band are commonly connected. As can be seen from FIG.
Regarding the emitter, it is not necessary to distinguish any of the transistors in the two bands, so that they are connected in common and connected to the ground GND.

FIG. 5 is a plan view of a final stage transistor of a power amplifier according to a second embodiment of the present invention. In this example, two transistors in the same band are set close to 40 μm in the horizontal direction in FIG.
In the vertical direction, the distance is as large as 200 μm. Therefore,
As in the case of the first embodiment, the final transistor as a whole has a large spread area, and the thermal resistance can be reduced. The second embodiment has an advantage that the crossover of the wiring can be reduced as compared with the first embodiment.

FIG. 7 is a circuit diagram of a dual-stage dual-band power amplifier corresponding to a third embodiment of the present invention. In this example, the collector output of the last-stage transistor is set to 800
MHz and 1900 MHz. In this case, the external output matching circuit 15 is matched in both frequency bands. FIG. 8 is a plan pattern diagram of the last-stage transistor. In this example, the output wiring through which a high current flows can be shared, so that the output wiring loss can be reduced and the output pad can be reduced to half the size.

The case where the output ratio of the power amplifier of the two bands is 1: 1 has been described above, but the output ratio is 1: 2, 1: 2.
.. Or 2: 1, 3: 1,..., The ratio of the number of unit transistors is not 1: 1. In these cases, the same operation and effect as in the case of 1: 1 can be obtained by appropriately arranging a number of transistors having different ratios.

In the above example, two types of unit transistors Tr (1) and Tr (2) are alternately arranged in one direction as shown in FIGS. 2 and 7, or as shown in FIG. An example is shown in which rows of types of transistors are alternately arranged. However,
The arrangement of the two types of unit transistors Tr (1) and Tr (2) alternately is not limited to this, and the two types of transistors Tr (1) and Tr (2) may be arranged in various modes so as to satisfy the requirement of suppressing heat generation as described above. (1) and Tr (2) can also be arranged. That is, the two types of unit transistors Tr (1) and Tr (2) may be arranged substantially alternately.

[0018]

As described above, according to the present invention,
The chip size of the dual band power amplifier can be greatly reduced, and the chip cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a final-stage transistor of a power amplifier realized by using the structure of the first embodiment of the present invention.

FIG. 2 is a plan pattern diagram of a last-stage transistor of a power amplifier when realized using the structure of the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a dual-stage dual-band power amplifier.

FIG. 4 is an example of the circuit of FIG. 3;

FIG. 5 is a chip of a dual-band power amplifier using the last-stage transistor of the present invention.

FIG. 6 is a plan pattern diagram of a final-stage transistor of the power amplifier according to the second embodiment of the present invention.

FIG. 7 is a circuit diagram of a dual-stage dual-band power amplifier corresponding to a third embodiment of the present invention.

FIG. 8 is a plan pattern diagram of a final-stage transistor according to a third embodiment of the present invention.

FIG. 9 is a chip diagram of a conventional dual-band power amplifier realizing this circuit.

FIG. 10 is a cross-sectional view of a final-stage transistor of a power amplifier of a conventional example.

FIG. 11 is a plan pattern diagram of a transistor in a final stage of a power amplifier of a conventional example.

[Explanation of symbols]

 Tr (1) Transistor for 800MHz Tr (2) Transistor for 1900MHz

Continued on the front page F-term (reference) FA16 FR01 HA07 HA24 HA25 HA29 HA33 KA29 KA48 MA08 MA19 MA22 QA02 QA03 QA04 SA14 TA01

Claims (5)

[Claims] 1. A first power amplifier and a second power amplifier on a single chip.
A power amplifier is formed, each of the first and second power amplifiers is constituted by a multi-emitter bipolar transistor, and a first unit transistor in the first power amplifier and a second unit transistor in the second power amplifier. A semiconductor device, wherein unit transistors are arranged substantially alternately in a plane. 2. The semiconductor device according to claim 1, wherein said first and second unit transistors are substantially alternately arranged in a certain direction. 3. A plurality of first unit transistors are arranged in a certain direction to form a first transistor row, and a plurality of second unit transistors are arranged in a certain direction to form a second transistor row. 2. The semiconductor device according to claim 1, wherein the first and second transistor rows are substantially alternately arranged along another direction substantially orthogonal to the certain direction. . 4. The power amplifier according to claim 1, wherein emitters of said first and second power amplifiers are electrically connected in common, and bases and collectors of said first and second power amplifiers are separately connected. 4. The semiconductor device according to any one of 1 to 3. 5. The power amplifier according to claim 1, wherein the emitter and the collector of the first and second power amplifiers are electrically connected in common, and the bases of the first and second power amplifiers are separately connected. Item 4. The semiconductor device according to any one of Items 1 to 3.