JPH0660895B2 - Ultrasonic flaw detector - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital ultrasonic flaw detector for performing flaw detection inside an object.

[Conventional technology]

The ultrasonic flaw detector is well known as an apparatus for inspecting the presence or absence of a scratch inside an object, a large size, etc. without destroying the object. Conventionally, as such an ultrasonic flaw detector, an analog type has been used in which an ultrasonic reflected wave reflected from an object is displayed on an oscilloscope. On the other hand, the applicant of the present invention has proposed a digital type ultrasonic flaw detector capable of processing the reflected ultrasonic wave in a more convenient manner for flaw detection according to Japanese Patent Laid-Open No. 63-95353. The outline of this digital ultrasonic flaw detector will be described with reference to the drawings.

FIG. 4 is a block diagram of a digital ultrasonic flaw detector. In the figure, 1 indicates an object to be inspected and 1f indicates a defect existing in the object to be inspected 1. Reference numeral 2 denotes an ultrasonic probe that radiates ultrasonic waves into the inspection object 1 and outputs an electric signal proportional to the reflected ultrasonic waves. Reference numeral 4 is a timing circuit for generating a pulse that gives time regulation to the operation of the ultrasonic flaw detector, and 5 is an ultrasonic probe 2 according to a signal from the timing circuit 4.
It is a transmitter that outputs a pulse for ultrasonic wave generation.
Reference numeral 6 is a receiving unit that receives a signal from the ultrasonic probe 2, and is composed of an attenuation circuit 6a and an amplification circuit 6b.

7 is an A / which converts the output signal of the receiving unit 6 into a digital value.
A D conversion unit, 8 is a waveform memory that stores the values converted by the A / D conversion unit 7, and 9 is an address counter that sequentially specifies each address of the waveform memory 8. A start signal is applied from the timing circuit 4 to the A / D converter 7 and the address counter 9, respectively. A crystal oscillator is used for oscillation of the timing circuit 4.

Reference numeral 10 is a CPU (central processing unit) for performing required arithmetic operations and control, 11 is a RAM (random access memory) for temporarily storing parameters and data for arithmetic operations, 12
Is a ROM (read only memory) that stores the processing procedure of the CPU 10. Reference numeral 13 is a measurement range setting unit for inputting a desired measurement range, and 14 is a sonic velocity input unit for inputting a velocity (sonic velocity) at which an ultrasonic wave propagates in the inspected object 1. 15
Is a display unit, and 16 is a display unit controller that controls the display of the display unit 15 based on the data obtained as a result of the calculation and control of the CPU 10.

Next, the outline of the operation of the ultrasonic flaw detector will be described with reference to the waveform diagram of the reflected wave signal shown in FIG. 5 and the block diagram of the waveform memory 8 shown in FIG. First, a desired measurement range l _R (this value is shown in the inspected object 1 shown in FIG. 4) is set in the measurement range setting unit 13. The sound velocity v _S determined by the material of the object 1 to be inspected is also input to the sound velocity input unit 14. In this state, when a trigger signal is output from the timing circuit 4 to the transmitting unit 5, the transmitting unit 5 outputs a pulse to the ultrasonic probe 2 and the ultrasonic probe 2 transmits a pulse to the inside of the inspected object 1. Sound waves are emitted. The reflected wave of this ultrasonic wave is converted into an electric signal by the ultrasonic probe 2, and this signal is received by the receiving unit 6. The receiving unit 6 outputs the received reflected wave signal as a value suitable for the subsequent processing. The output reflected wave signal is A / D at a predetermined sampling cycle.
It is converted into a digital value in the conversion unit 7, and the converted value is sequentially stored in the waveform memory 8. This memory is
This is done by the address counter 9 sequentially designating the addresses of the waveform memory 8. The sampling of the reflected wave signal and the addressing of the waveform memory 8 are performed by the start signal output from the timing circuit 4. Sampling of such a reflected wave signal and accommodation of the digital value in the waveform memory 8 will be described with reference to FIGS. 5 and 6.

FIG. 5 is a waveform diagram of the reflected wave signal. In the figure, the horizontal axis represents time, and the vertical axis represents the magnitude (voltage) of the reflected wave signal. T represents a reflected wave signal from the surface of the inspected object 1, and F represents a reflected wave signal from the defect 1f. Incidentally, in FIG. 5, only the horizontal axis is drawn in an extremely enlarged manner. Next, FIG. 6 is a block diagram of the waveform memory 8. Each block shown in a column means a data storage unit in the waveform memory 8, and D ₍₀₎ , D ₍₁₎ , ... D stored in each storage unit.
_(i-1) , D _(i) , D _{(i + 1)} ... Are the data of the reflected wave signals converted into digital values by the A / D converter 7. These data are represented by D _(i) as a general form. Further, the symbols A _{M (0)} , A _{M (1)} , ... Described on the left side of each accommodation part are obtained,
The address counter 9 receives the next address A _{M (1)} A _{M (i)} , A
_{M (i + 1)} ... indicates the address of the corresponding accommodation unit. These addresses are represented by A _{M (i)} as a general form.

Now, at time t ₀ shown in FIG. 5, the timing circuit 4
When the start signal is output from the A / D converter 7 and the address counter 9 from the A / D converter 7, the voltage of the reflected wave signal T at that time is A / D converted to obtain the data D ₍₀₎ . .
Further, the address counter 9 is the address A of the waveform memory 8.
Specify _{M (0)} . As a result, the data D ₍₀₎ is stored in the address A _{M (0)} of the waveform memory 8. Next, at time t ₁ after the time τ _{s has} elapsed, the timing circuit 4 again outputs A
When the activation signal is output to the / D converter 7 and the address counter 9, the voltage of the reflected wave signal T at that time is A
The data D ₍₁₎ is obtained by being converted by the / D converter 7, and the address counter 9 designates the next address A _{M (i)} .
The data D ₍₁₎ is stored in the address A _{M (1)} of the waveform memory 8. In this case, the time τ _s becomes the sampling time (for example, 50 ns). Thereafter, similarly, the data of the reflected wave signal is stored in the waveform memory 8. The sampling time τ _s is shown extremely large in comparison with the reflected wave signal.

In this way, necessary data is extracted from the reflected wave signal data D _i stored in the waveform memory 8 and the display unit 1
It is displayed in 5. For example, when displaying a waveform within a distance l _R from the surface of the inspection object 1 as shown in FIG.
The distance l _R is set in the measurement range setting unit 13, and this distance l
Data in the range of the distance l _R is selectively fetched from the waveform memory 8 and displayed on the display unit 15 at a numerical interval calculated based on _R and the velocity V _s input to the sound velocity input unit 14. The operation for displaying these is controlled by the CPU 10.

The above-mentioned digital ultrasonic flaw detector has various types of display such as the whole display of the reflected wave of the object to be inspected 1, the display of the reflected wave in an arbitrary range, the enlarged display of an arbitrary portion of the reflected wave, the transition display of the reflected wave in the time axis direction. The function can be executed, and it is extremely effective for flaw detection of the object to be inspected.

[Problems to be Solved by the Invention]

In the above ultrasonic flaw detector, it is natural that high flaw detection accuracy, that is, high precision flaw detection at the defect position (the distance from the surface of the object to be inspected to the defect) is required. For that purpose, it is necessary to reduce the sampling time τ _s ,
To this end, the A / D converter 7 has a high-speed A / D conversion circuit,
For example, an A / D conversion circuit using an ECL (Emitter Coupled Logic) circuit may be used. By the way, when such a high-speed A / D converter circuit is used as the A / D converter 7a of the conventional apparatus shown in FIG. It is necessary to use a circuit. This will be described with reference to FIG.

FIG. 7 is a circuit diagram when an ECL circuit is used for the A / D conversion circuit. In the figure, the same parts as those in FIG. 4 are designated by the same reference numerals. The A / D converter 7 in FIG. 4 is composed of an A / D conversion circuit 7a and a latch circuit 7b which holds the output of the A / D conversion circuit 7a for a certain period of time, and the waveform memory 8 includes a memory 8a which is a storage element and an address of the memory 8a. It is composed of a multiplexer 8b for switching. Reference numerals 16 and 17 are translators for converting the voltage level between the ECL circuit and the TTL circuit.

In the above circuit, if the ECL circuit is used as the A / D conversion circuit 7a, the timing circuit 4 and the address counter 9 also become E.
The CL circuit must be used, and the latch circuit 7b, the memory 8a, and the multiplexer 8b are also ECL.
Clearly, the circuit needs to be used.

By the way, the ECL circuit consumes more power than a normal TTL circuit, and accordingly generates a large amount of heat and is expensive. On the other hand, since the memory composed of the ECL circuit has a small capacity, it is necessary to use a large number of memories in order to obtain the memory having the same capacity as the memory using the normal TTL circuit. Therefore, when the ECL circuit is used for the memory 8a as shown in FIG. 7, the number of the memories 8a becomes large, so that the power consumption and the heat generation amount become extremely large, and a large power source and a cooling device are required, As a result, the problem of increasing the cost of the ultrasonic flaw detector arises in combination with the use of many expensive memories.

The object of the present invention is to solve the above-mentioned problems in the conventional technology,
High speed A / D converter and low speed memory
An object of the present invention is to provide an ultrasonic flaw detector that can detect flaws with the same accuracy as when using a / D converter and a high-speed memory.

[Means for Solving the Problems] In order to achieve the above object, the present invention transmits an ultrasonic signal to an object to be inspected, receives an ultrasonic reflected wave from the object to be inspected, and receives the reflected wave. In an ultrasonic flaw detector that performs flaw detection on the flaw detection object by analyzing a signal, a signal having a plurality of output ends and a predetermined sampling frequency for the received signal divided by the reciprocal of the output end number is shifted for each sampling period. From each of the output terminals, a signal generating means, a multiplexer for sequentially selecting the output terminals of the signal generating means for each transmission of the ultrasonic signal, and outputting a signal of the selected output terminal, and from this multiplexer In the low-speed A / D converter that converts the received signal of the ultrasonic reflected wave into a digital value by the signal of, and the low-speed A / D converter by the signal from the multiplexer. A latch circuit for holding the converted value, each low speed memory provided with the same number of output terminals of the signal generating means for storing the data held in the latch circuit, and the low speed memory by the output signal of the multiplexer. And a demultiplexer for sequentially selecting the low-speed memories each time the ultrasonic signal is transmitted and connecting the low-speed memories to the latch circuit.

[Operation] The signal generating means divides the predetermined sampling frequency by the reciprocal of the number of the output terminals of the signal generating means, and outputs the divided signals in order from each output terminal by a sampling cycle. . The multiplexer sequentially selects each output end of the signal generating means for each transmission of the ultrasonic signal,
Output the signal at the selected output end.

On the other hand, the low-speed A / D converter operates every time the signal from the multiplexer is input to convert the ultrasonic reception signal into a digital value, and the latch circuit is converted by the A / D converter by the same signal from the multiplexer. Hold the value.

The demultiplexer sequentially selects each low-speed memory each time the ultrasonic signal is transmitted, and while one memory is being selected, the selected low-speed memory is held in the latch circuit as an operating state for each output signal from the multiplexer. The stored value is stored in the low-speed memory.

As described above, the ultrasonic signal is sampled at the same sampling cycle as the conventional one to obtain highly accurate ultrasonic data, and this can be achieved by using the low speed A / D converter and the low speed memory.

〔Example〕

 Hereinafter, the present invention will be described based on the illustrated embodiments.

FIG. 1 is a block diagram of a part of an ultrasonic flaw detector according to an embodiment of the present invention. In the figure, the same parts as those shown in FIG. 20 is a frequency dividing circuit for dividing the output pulse of the timing circuit 4 into 1/4, 21 is a shift register for sequentially shifting and outputting the pulse output from the frequency dividing circuit 20, and 22 is for sequentially selecting the output of the shift register 21. It is a multiplexer for outputting. The frequency dividing circuit 20 and the shift register 21 constitute a signal generating means having four output terminals. The shift register 21 is reset (initialized) by the timing circuit 4 before the transmitter 5 is activated, and the multiplexer 22 is configured to be sequentially switched each time the transmitter 5 is activated. There is. M ₁ , M ₂ , M ₃ , and M ₄ are memories for storing the data latched in the latch circuit 7b. Reference numeral 23 denotes a demultiplexer which sequentially switches and selects the memories M _{1 to} M ₄ each time the transmitter 5 is activated, and 24
Is a multiplexer for switching and designating the addresses of the memories M _{1 to} M ₄ according to an instruction of the address counter 9 or the CPU 10, and 25 is a memory M _{1 to} M based on the instruction of the CPU 10.
It is a decoder for selecting any one of the _four . The A / D conversion circuit 7a, the latch circuit 7b, the memory M ₁
.About.M _{4 and the} like are all operated by a normal TTL circuit.

Next, the operation of this embodiment will be described with reference to the waveform charts shown in FIGS. 2 (a) and 2 (b) and the time chart shown in FIGS. 3 (a) to 3 (j). First, Fig. 2 (a), (b)
An outline of the operation will be described based on the waveform chart shown in FIG. FIG. 2 (a) is the same waveform diagram as that shown in FIG.
It is shown in order to facilitate comparison with the waveform diagram of FIG. 2 (b) showing the operation of this embodiment. In the conventional device, data is sampled for each cycle (sampling period τ _s ) of the pulse output from the timing circuit 4 by one activation of the transmission unit 5. On the other hand, in the present embodiment, the frequency of the output pulse of the timing circuit 4 is divided into ¼, and the transmission unit 5 is activated once for each divided period (sampling period 4 · τ _s ). Data sampling. This will be described with reference to FIG. 2 (b).
Performing a first-time sampling at time t ₀ as shown by the black circles ●, time t _{0 + 1} has elapsed period 4 · τ _s from the time t ₀
The second sampling is performed. Below is the sequential period 4
Sampling is performed at intervals of τ _s . in this way,
Since it was a long sampling period 4 · tau _s executes connexion sampling, A / D converter circuit 7a, latch 7
b, the memories M _{1 to} M ₄ , and the other circuit configurations are all normal TTL circuit configurations, the sampling period 4
It can correspond to the timing of τ _s .

In order to sample the data in the middle of such a long sampling period τ _s , the transmitter 5 performs the second activation. In this case as well, sampling is executed in a divided cycle as in the case of the first activation, but the sampling is executed with a phase shift of 1/4 cycle. The sampling in this case is shown by a white circle in FIG. That is, sampling is performed at time t _1, the next sampling is carried out and then a period 4 · tau _s elapsed time t _{1 + 1.} Hereinafter, sampling is performed at intervals of 4 · τ _{s in} sequence. Subsequent to this second activation, the transmitter 5 activates the third and fourth activations,
As shown by triangle mark △ and square mark □ in Fig. (B), 1 sequentially
Sampling is performed by shifting by / 4 cycle. As a result, the same sampling as that of the conventional apparatus shown in FIG. 2 (a) can be performed during the four activations of the transmitter 5.

In the above operation, the conventional device samples all the data by activating the transmitting unit once, whereas the conventional device samples all the data by activating the transmitting unit four times. Since the same waveform can be obtained as long as the object 1 to be inspected is in contact with the same place with the same pressure, the same reflected waveform is received and sampled every time the transmitter 5 is activated a plurality of times in the above operation. There is no error in the collected data.

Now, the operation of the circuit shown in FIG. 1 for executing the above operation will be described with reference to the time charts shown in FIGS. 3 (a) to 3 (j). The timing circuit 4 outputs a pulse having a period τ _s as shown in FIG. The frequency divider circuit 20 outputs this output 1 / as shown in FIG. 3 (b).
The frequency is divided into four and output to the shift register 21. The output divided by the shift register 21 is shifted by the period τ _s by the output of the timing circuit 4. Each shifted output is shown in Figures 3 (c)-(f). The multiplexer 22 is switched to the state of outputting the signal shown in FIG. 3C by the first activation of the transmitter 5. This signal is output to the A / D conversion circuit 7a, the latch circuit 7b, the demultiplexer 23, and the address counter 9 to activate them.

When the A / D conversion circuit 7a and the latch circuit 7b are activated, the reflected wave signal received via the ultrasonic probe 1 by the activation of the transmitter 5 and amplified by the amplification circuit 6b is A / D converted, and then the latch. To be done. The data of this reflected wave signal is shown by reference numeral D ₁ in FIG. On the other hand, the demultiplexer 23 causes the timing circuit 4 to detect the first memory M ₁
Is selected, and is activated by a signal from the multiplexer 22 to bring the selected memory M ₁ into a storable state. Further, the address counter 9 outputs a signal designating the address A _{M (0)} by the signal of the multiplexer 22. At this time, since the multiplexer 24 is switched to the address counter 9 side, the address A _{M (0)} is designated in the memory M ₁ . In the above state, the data D ₁ latched in the latch circuit 7b at that time is stored in the address A _{M (0)} of the memory M ₁ as shown in FIG. 3 (g).

The multiplexer 22 continues to select the signal shown in FIG. 3 (c) among the output signals of the shift register 21 unless the transmitter 5 is activated for the second time, and the demultiplexer 23 selects the memory M ₁ . Therefore, the same operation as above is repeated every time the signal rises, and the address A of the memory M ₁ designated by the address counter 9 is specified.
_The data D ₅ , D ₉ , D ₁₃ , ... Are sequentially stored in _{M (1)} , A _{M (2)} , ... As shown in FIG. 3 (g). The above operation corresponds to the sampling operation in the black circle mark ● shown in FIG. 2 (b), and each data sampled at that time is the data D ₁ , D ₅ , stored in the memory M ₁ .
D ₉ , ...

When the first data sampling is completed in this way, the second activation of the transmitter 5 is executed. By this activation, the multiplexer 22 selects the signal shown in FIG. 3 (d), which is out of phase with the period τ _s from the signal selected at the first time among the signals output from the shift register 21, and also The multiplexer 23 selects the memory M ₂ . If the condition in the same operation as the first round is repeated, the memory M ₂ address _{A M (0), A M} (1), A M (2), ...
As shown in FIG. 3 (h), the data D ₂ ,
D ₆ , D ₁₀ , D ₁₄ , ... Are stored. Then, this operation corresponds to the sampling operation in the white circle mark ◯ shown in FIG.

Similarly, each time the transmitter 5 is activated for the third time and the fourth time, the multiplexer 22 causes the shift register 21 to operate as shown in FIG.
The output shown in (f) is sequentially selected, and the demultiplexer 24 is switched so as to sequentially select the memories M ₃ and M ₄ , whereby the triangular mark Δ and the square mark □ shown in FIG. 2B are selected. Is sampled. As a result, as shown in FIG. 3 (i), the data D ₃ , D are stored in the memory M ₃ .
_7, D _11, ...... it is stored, also the memory _{M 4} Figure 3 data as shown in _{(j) D 4, D 8} , D 12, ...... are stored. Here, the relationship between the data stored in each of the memories M _{1 to} M ₄ and each address is shown in the following table.

Next, the operation of taking out the data stored in each of the memories M _{1 to} M ₄ will be described. When the data to be taken out is determined so as to meet various conditions such as the set measurement range, the CPU 10 outputs a signal designating the memory in which the data is stored to the decoder 25, The decoder 25 decodes this signal and outputs the signal to the designated memory. At the same time, the CPU 10 outputs a signal designating the address of the memory in which the data is stored to the multiplexer 24, and the multiplexer 24 switches the address in response to this.
Designate the address by the signal. As a result, the required data is fetched from the address of the memory and processed by the CPU 10.

As described above, in the present embodiment, sampling is performed by activating the transmitting unit four times, so sampling may be performed in a sampling period (for example, 50 ns) that is four times the required sampling period (for example, 12.5 ns). Therefore, the device can be configured with a low-speed A / D conversion circuit, a latch circuit, a memory, and the like, which can suppress the power consumption and the heat generation amount, and reduce the price of the ultrasonic flaw detector. It can be done.

In the description of the above embodiment, the example in which the sampling period is quadrupled has been described.
The multiple can be freely selected in consideration of various conditions.

〔The invention's effect〕

As described above, according to the present invention, the sampling is performed by activating a plurality of times, so that the sampling period can be lengthened, whereby the low speed A / D converter, the latch circuit and the memory are used. As a result, the power consumption and heat generation amount of the ultrasonic flaw detector can be suppressed, and the cost thereof can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a part of an ultrasonic flaw detector according to an embodiment of the present invention, FIGS. 2 (a) and 2 (b) are waveform diagrams of reflected wave signals, and FIG.
(A) to (j) are time charts showing the operation of the configuration shown in FIG. 1, FIG. 4 is a block diagram of an ultrasonic flaw detector, and FIG.
6 is a waveform diagram of a reflected wave signal, FIG. 6 is a block diagram of a waveform memory, and FIG. 7 is a partial block diagram of an ultrasonic flaw detector which can be considered when a high-speed A / D conversion circuit is used. 4 ... Timing circuit, 7a ... Low speed A / D conversion circuit,
7b ...... latch, 20 ...... divider circuit, 21 ...... shift register, 22, 24 ...... multiplexer, 23 ...... _{demultiplexer,} M 1 ~M ₄ ...... slow memory.

Claims (1)

[Claims] 1. An ultrasonic signal is transmitted to an object to be inspected,
An ultrasonic flaw detector that receives an ultrasonic reflected wave from the flaw detection object and performs flaw detection of the flaw detection object by analyzing the received signal has a plurality of output terminals and a predetermined sampling frequency for the received signal. Signal generating means for outputting a signal divided by the reciprocal of the output fraction from each of the output terminals by shifting the sampling period, and each of the output terminals of the signal generating means are sequentially selected for each transmission of the ultrasonic signal. A multiplexer that outputs a signal at the selected output end, a low-speed A / D converter that converts the reception signal of the ultrasonic reflected wave into a digital value by the signal from the multiplexer, and a low-speed A / D converter by the signal from the multiplexer. A latch circuit for holding the value converted by the / D converter,
Each low-speed memory provided with the same number of output terminals as the signal generating means and storing the data held in the latch circuit, and the low-speed memory operated by the output signal of the multiplexer, and each low-speed memory An ultrasonic flaw detector, comprising: a demultiplexer which is sequentially selected for each transmission of an acoustic wave signal and connected to the latch circuit.