JPH0648264B2 - Ultrasonic flaw detector - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an ultrasonic flaw detection apparatus that performs flaw detection inside an object using ultrasonic waves.

[Conventional technology]

The ultrasonic flaw detection device is well known as a device for inspecting the presence or absence of a flaw inside an object, its size, and the like without destroying the object. Conventionally, as such an ultrasonic flaw detection device, an analog type device for displaying an ultrasonic reflected wave reflected from an object on an oscilloscope has been used. On the other hand, in recent years, a digital type ultrasonic flaw detection apparatus has been proposed which can process the reflected ultrasonic waves so as to be more convenient for flaw detection. This will be described with reference to FIGS. 3 and 4.

FIG. 3 is a block diagram of a conventional digital ultrasonic flaw detector. In the figure, 1 indicates an object to be inspected (inspection object), and F indicates a defect in the inspection object 1. A probe 2 emits ultrasonic waves to the subject 1 and receives a reflected wave from the subject 1 and outputs an electric signal corresponding thereto. Reference numeral 3 denotes a pulser / receiver section for applying a pulse to the probe 2 to generate ultrasonic waves and for receiving and detecting and amplifying a signal from the probe 2, and 4 denotes an output signal of the pulser / receiver section 3. It is an A / D conversion unit for converting into a digital value. Reference numeral 5 is a control unit for controlling the pulser / receiver unit 3 and the A / D conversion unit 4, and takes in a signal of an ultrasonic reflected wave from the subject 1 converted into a digital value by the A / D conversion unit 4 and predetermined. Is processed. Reference numeral 6 denotes a display device which displays the waveform of an ultrasonic reflected wave or the like under the control of the control unit 5 based on the data processed by the control unit 5.

FIG. 4 is a block diagram showing the detailed structure of the A / D conversion unit 4 shown in FIG. In the figure, 40 is a pulser / receiver unit 3
A / D converter for A / D converting signal e from
Is a data bus gate for conducting and blocking the data converted by the A / D converter 40, 42 is a memory for storing the data passed through the data bus gate 41, and 43 is a memory 42 for the memory 42 by the signal b from the control unit 5. A read line controller for storing data and reading the stored data. Reference numeral 44 is a data bus gate which is turned on when the data stored in the memory 42 is read and outputs the data d to the control unit 5, 45 is a NOT circuit, and 46 is a control unit 5.
It is a flip-flop circuit that changes the output level in response to the A / D converter activation signal a from. 47 is a memory 42
Address counter that sequentially specifies the addresses of
Is a multiplexer for switching between the address signal of the address counter 47 and the address signal c from the control section 5 in response to a command from the read / write controller 43. 49 is A
The oscillator regulates the operation of the / D converter 4, and a predetermined element of the A / D converter 4 operates in synchronization with the clock signal output from the oscillator 49.

Next, the operation of the A / D converter 4 will be described with reference to FIG.
This will be described with reference to the time chart shown in (g). Fifth
FIG. 7A shows a clock signal of the oscillator of the control unit 5, the period of which is indicated by T ₅ . (B) is a start signal a output from the control unit 5, (c) is a flip-flop circuit 4
6, an output signal of 6; a clock signal (cycle T ₄₉ ) of the oscillator 49; (e) a count-up signal of the address counter 47; (f) data converted by the A / D converter 40; (g) Indicates the pulser output of the pulser / receiver unit 3.

First, as shown in FIG. 5A, the control unit 5 outputs the activation signal a to the pulser / receiver unit 3 and the A / D conversion unit 4. As a result, as shown in FIG. 5 (g), the pulser / receiver unit 3 outputs a pulse to the probe 2 to radiate ultrasonic waves, and the reflected wave signal e from the pulser / receiver unit 3 to A / It is input to the A / D converter 40 of the D conversion unit 4.

On the other hand, the start-up signal a is also input to the flip-flop circuit 46 of the A / D converter 4, and changes its output level from, for example, low level to high level, as shown in FIG. 5 (c). As a result, the read / write controller 43 operates to put the memory 42 in a writable state, switches the multiplexer 48 to a state in which the output signal of the address counter 47 is selected, activates the address counter 47, and
The data bus gate 41 is turned on and the data bus gate 44 is turned off.

Since the read / write controller 43 and the address counter 47 operate in synchronization with the clock signal of the oscillator 49, the signal is output from the read / write controller 43 and at the same time, the address counter 47 outputs the address of the memory 42 at the cycle of the oscillator 49. Specify in order. When the reflected wave signal e is input to the A / D converter 40 in this state, the reflected wave signal e is synchronized with the clock signal of the oscillator 49 as shown in FIG.
A / D conversion is performed. The converted data is stored in the address of the memory 42 designated by the address counter 47 via the data bus gate 41 in the conductive state.

The count number of the address counter 47 is set according to the capacity (number of addresses) of the memory 42. And
When the above operation is continued and the count of the address counter 47 reaches the above count number, the address counter 47
As shown in FIG. 5 (e), a count-up signal is output from the flip-flop circuit 46 to change the output of the flip-flop circuit 46 from a high level to a low level. As a result, the data bus gate 41 is turned off, the data bus gate 44 is turned on, the count of the address counter 47 is stopped, and the multiplexer 48 is switched to the state of selecting the signal c, as shown in FIG. Then, the first writing to the memory 42 is completed.

Subsequently, the data of the ultrasonic reflected wave signal thus A / D converted is read out, and the waveform is displayed on the display device based on this. This operation will be described below. First, the read signal b is output from the control unit 5 to the read / write controller 43, and at the same time, the address signal c is output to the memory 42 via the multiplexer 48. In this case, the read signal b and the address signal c are transferred to the control unit 5.
Is output in synchronization with the clock signal of the oscillator (not shown). When the read signal b is input, the read / write controller 43 puts the memory 42 into a read state. As a result, the data of the addresses sequentially designated by the address signal c is output from the memory 42 to the control unit 5 as the data signal d via the data bus gate 44 in the conductive state.

The control section 5 performs necessary calculations and controls based on these data signals d, and displays the waveform of the reflected wave signal on the display device 6.

In this way, when the first data collection and display are completed, the command signal a from the control unit 5 continues
The same data collection and display operation as the second time is performed, and the third time, the fourth time, and so on are sequentially repeated.

[Problems to be Solved by the Invention]

In the ultrasonic flaw detector, since the A / D conversion performed by the A / D conversion unit 4 is high speed, the A / D conversion unit 4 is provided with a dedicated oscillator 49 in addition to the oscillator of the control unit 5. There is. Therefore, the clock signal (T ₅ ) of the oscillator of the control unit 5 and the clock signal of the oscillator 49 are asynchronous.

By the way, the start signal (T ₄₉ ) a is output in synchronization with the clock signal of the oscillator of the control unit 5, but the conversion data is written in the memory 42 in synchronization with the clock signal of the oscillator 49 as described above. Therefore, it is not synchronized with the clock signal of the oscillator of the control unit 5. Therefore, the time from the output of the activation signal a to the designation of the first address in the memory 42 is at each A / D conversion period (first time, second time, ... … Every time will be different.
In other words, after the pulser / receiver unit 3 is driven,
The time required to start A / D conversion of the reflected wave signal is A
The time is different for each / D conversion period. As a result, when the waveform of the reflected wave is displayed on the display device 6, the displayed waveform is always slightly moved in the time axis direction and is not constant, which causes a serious problem of flaw detection. This is the fifth
This will be described in detail with reference to FIGS.

As described above, since the clock signal of the control unit 5 and the clock signal of the oscillator 49 are not synchronized, the reflected wave signal is changed to A by the A / D converter 40 after the activation signal a is output.
Before the D / D conversion, for example, FIGS. 5 (d) and 5 (f) are performed.
As in the first A / D conversion operation shown in, there is a time difference of t ₁ . In addition, D ₁₁ shown in FIG.
D ₁₂ and D ₁₃ represent data of the converted reflected wave signal. For the same reason, the deviation time in the second A / D conversion operation is, for example, time t ₂ . The probability that the times t ₁ and t _{2 of} the first time and the times of the second time coincide with each other is extremely low, and usually the times are different.

As described above, the display state on the display device 6 when the A / D conversion start times are different will be described with reference to the time charts shown in FIGS. 6 (a) to 6 (e). FIG. 6 (a),
(D) is the same clock signal as that shown in FIGS. 5 (a) and 5 (d), and FIG. 6 (c) is the same start signal as shown in FIG. 5 (c). The axis is shown to be smaller than the latter time axis. FIG. 6B shows the waveform of the reflected wave signal e input to the A / D converter 40,
The signal wave (transmitted wave) in which the pulsar output shown in FIG. 5 (g) is directly reflected on the surface of the probe 2 appears first, and then the defect F
A defect wave appears after a time corresponding to the position of.

Such a reflected wave signal e is sequentially A / S synchronized with the clock signal of the oscillator 49 as shown in FIGS. 6 (b) and 6 (d).
D converted. The data D ₁₁ converted in this way,
D ₁₂ and D ₁₃ are written on the waveform of FIG. 6 (b),
These data correspond to each data shown in FIG. 5 (f).

Here, the state of the first A / D conversion and the second A / D conversion
Compare with the state of D conversion. In FIG. 6, in order to more clearly explain the drawbacks of the conventional device, the first rising edge of the starting signal a and the rising edge of the clock signal of the oscillator 49 are set to the same time. In this first conversion operation, the first
The data stored at the address is D ₁₁ , the data stored at the second address is D ₁₂ , and the data stored at the third address is D ₁₃ .

On the other hand, in the second conversion operation, the sixth conversion is performed between the rising edge of the activation signal a and the rising edge of the clock signal of the oscillator 49.
There is a time t ₀ shift as shown in FIG. In this case, the data stored at the first address is D ₂₁ , the data stored at the second address is D ₂₂ , the data stored at the third address is D ₂₃ , and the data stored at each address. Is a different value during the first conversion operation and during the second conversion operation. That is, during the second conversion operation, the data at the time point shifted by the time t _{0 as} compared with the first conversion operation is stored.

FIG. 6 (e) is a diagram showing a case where the data at the time of the first conversion operation and the data at the time of the second conversion operation are displayed on the same display surface. The display waveform indicated by the solid line is the waveform during the first conversion operation, and the display waveform indicated by the broken line is the waveform during the second conversion operation. As is apparent from the figure, the latter waveform is shifted to the left by a length corresponding to time t ₀ in the time axis direction as compared with the former waveform.

In this way, the display waveform is shifted left and right for each conversion operation and is not constant.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide an ultrasonic flaw detector capable of preventing fine movement in the time axis direction.

[Means for Solving the Problems]

In order to achieve the above object, the present invention synchronizes with a signal of a first oscillator and a transmitting / receiving unit that transmits an ultrasonic output signal to a probe and receives an ultrasonic signal from the probe. A / which converts the ultrasonic signal from the transmitting / receiving unit into A / D
In an ultrasonic flaw detector equipped with a D conversion unit and a control unit for performing display processing in synchronization with the signal of the second oscillator based on the data from the A / D conversion unit, the A / D conversion unit is controlled. It is characterized in that a starting means is provided for simultaneously outputting the A / D conversion starting signal and the transmitting / receiving section starting signal in synchronization with the signal of the first oscillator in response to a command signal from the section.

[Work]

The activation command signal from the control unit is input to the activation means of the A / D conversion unit. The starting means receives the starting command signal once, and outputs the A / D conversion starting signal and the transmitting / receiving section starting signal in synchronization with the clock signal of the first oscillator. As a result, it is possible to prevent the position of the displayed reflected wave signal in the time axis direction from changing for each A / D conversion period.

〔Example〕

 Hereinafter, the present invention will be described based on the illustrated embodiments.

FIG. 1 is an A / D of an ultrasonic flaw detector according to an embodiment of the present invention.
It is a block diagram of a conversion part. In the figure, the same parts as those shown in FIG. In this embodiment, the configurations of the pulser / receiver unit 3, the control unit 5 and the display device 6 are the same as those of the conventional device shown in FIG.
In the present embodiment and the conventional device, the conventional device outputs the activation signal a of the pulser / receiver unit 3 from the control unit, whereas in the present embodiment, it is output from the A / D conversion unit. , And the A / D conversion unit of the present embodiment is different only in that a flip-flop circuit 50 is added to the configuration of the A / D conversion unit 4 of the conventional device, and the other configurations are the same.

The flip-flop circuit 50 is a flip-flop circuit 46.
Changes its output in response to changes in its output. The data bus gates 41 and 44, the address counter 47, and the multiplexer 48 are driven by the output of the flip-flop 50. The output of the flip-flop 50 is input to the pulsar receiver 3 as a start signal a ″ for the pulsar receiver 3.

Here, the operation of this embodiment will be described with reference to FIGS. 2A is a clock signal of the oscillator of the control unit 5, FIG. 2B is a start signal a ′ output from the control unit 5, and FIG. 2C is an output signal of the flip-flop circuit 46.
(D) is the clock signal of the oscillator 49, (e) is the count-up signal of the address counter 47, (f) is the data converted by the A / D converter 40, (g) is the pulser output of the pulser / receiver unit 3, (H) shows an output signal (pulser activation signal) of the flip-flop 50.

As shown in FIG. 2 (b), when the activation signal a'from the control unit 5 is input to the flip-flop circuit 46 of the A / D conversion unit, the output of the flip-flop circuit 46 is shown in FIG. 2 (c). As shown, for example, the level changes from low level to high level. In this case, the signal a'input to the flip-flop circuit 46 is the same as the signal a input to the same flip-flop circuit 46 in the conventional device as the activation signal for the A / D conversion, whereas the signal a ' This is a signal having the functions of an activation signal and an activation signal of the pulser / receiver unit 3. With the output of the flip-flop circuit 46 changed to a high level, the flip-flop circuit 50 includes an oscillator 49.
When the clock signal is input, the flip-flop circuit 5
The output of 0 changes from low level to high level, for example, as shown in FIG. 2 (h). Due to this change, the data bus gate 41 is turned on, the data bus gate 44 is turned off, and the multiplexer 48 is turned off.
7, the read / write controller 43 puts the memory 42 into the read state, and the address counter 47 starts outputting the address signal according to the clock signal of the oscillator 49. Simultaneously with these operations, as shown in FIG. 2 (g), the activation signal a ″ is output to the pulser / receiver unit 3, and as shown in FIG. 2 (f), A /
A / D conversion of the reflected wave signal e by the D converter 40 is started. That is, the pulser output and the A / D conversion of the reflected wave signal e are performed in synchronization with the signal a ″ (in synchronization with the clock of the oscillator 49).

After that, the addresses of the memory 42 are sequentially designated, and at that time, the data A / D converted by the A / D converter 40 is stored in the address. Such operation is the same as that of the conventional device. When this operation is continued and the address counter 47 counts up as shown in FIG. 2 (e), the count-up signal is input to the flip-flop circuits 46 and 50, and FIG.
As shown in (h), those outputs are set to low level.
When the output of the flip-flop circuit 50 becomes low level,
Data bus gate 41 is cut off, data bus gate 4
4 becomes conductive, the multiplexer 48 is switched to the input side of the address signal c from the control unit 5, and the address counter 47 is stopped, whereby the first data collection is completed. From this state, the data stored in the memory 42 is read and displayed in the control unit 5 by the same means as the conventional device.

Subsequently, the control unit 5 outputs the start signal a ′ at time t _{20 as} shown in FIG. 2 (b) in order to perform the second data collection and display, and the data collection and display are performed by the same operation. Done. In this case, the flip-flop circuit 50 is provided in the present embodiment, and the flip-flop circuit 5 is provided.
0 is configured to change the output in synchronization with the clock signal of the oscillator 49, and this output is used to start the storage of the memory 42 and the activation of the pulser / receiver unit 3. starting pulser-receiver unit 3, and the a / D converter each time the a / D conversion start of 40, FIG. 2 (f), (g), as shown in (h), all at time t ₂₁ It will be a match. That is, the first data D ₁₁ and each subsequent data sampled at the first time and the first data D ₂₁ and each subsequent data sampled at the second time are reflected at the same time after the pulser output. It becomes the data of the wave signal e. Same operation is the third
It is repeated after the first time. In this way, it is possible to prevent the time from the driving of the pulser / receiver unit 3 to the start of A / D conversion of the reflected wave signal from changing for each A / D conversion period, and When a waveform is displayed, the waveform does not slightly move in the time axis direction.

〔The invention's effect〕

As described above, according to the present invention, the A / D conversion unit is provided with the activation means and the activation signal of the A / D conversion and the activation signal of the transmission / reception unit are simultaneously output. A fine movement in the axial direction can be prevented, and stable flaw detection can be performed.

[Brief description of drawings]

FIG. 1 is an A / D of an ultrasonic flaw detector according to an embodiment of the present invention.
2A to 2H are time charts for explaining the operation of the apparatus shown in FIG. 1, FIG. 3 is a block diagram of a conventional ultrasonic flaw detector, and FIG. A block diagram of the A / D converter shown in FIG. 3, FIGS. 5 (a) to (g), and FIGS. 6 (a) to (e) are time charts for explaining the operation of the apparatus shown in FIG. is there. 2 ... Probe, 3 ... Pulser / receiver section, 5 ... Control section, 6 ... Display device, 40 ... A / D converter, 4
1,44 ... Data bus gate, 42 ... Memory, 43
... Read / write controller, 46, 50 ... flip-flop circuit, 47 ... address counter, 48 ...
… Multiplexer.

Claims (3)

[Claims] 1. A transmission / reception unit that transmits an ultrasonic wave output signal to a probe and receives an ultrasonic wave signal from the probe,
An A / D converter for A / D converting the ultrasonic signal from the transmitter / receiver in synchronization with the signal of the first oscillator;
In an ultrasonic flaw detector equipped with a control unit that performs display processing in synchronization with a signal from a second oscillator based on data from the D conversion unit, the A / D conversion unit receives a command signal from the control unit. An ultrasonic flaw detector, comprising a starting means for simultaneously outputting an A / D conversion starting signal and a starting signal of the transmitting / receiving section in synchronization with a signal of the first oscillator. 2. A first flip-flop circuit for changing the output state according to the command signal of the control section, and an input of a signal of the first oscillator according to claim (1). According to the above, the ultrasonic flaw detector is constituted by an A / D conversion starting unit and a second flip-flop circuit for outputting the output state of the first flip-flop circuit to the transmitting / receiving unit. 3. In the claim (2), the A
The ultrasonic flaw detector, wherein the / D conversion starting unit is a gate means for conducting and blocking A / D converted data.