JP2624749B2 - Ultrasonic flaw detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an ultrasonic flaw detector that performs flaw detection on a test material using ultrasonic waves.

[Conventional technology]

Ultrasonic flaw detectors can detect defects inside an object without destroying the object, and are used in many fields. For example, when detecting the presence or absence of delamination between layers of a plate-shaped semiconductor chip molded with a synthetic resin material, a probe that transmits and receives ultrasonic waves is scanned in the vertical and horizontal directions or in the circumferential direction on the surface of the chip, Ultrasonic waves are transmitted and received at a number of points on the scanning path to detect the presence or absence of peeling. Such an ultrasonic flaw detector will be described with reference to FIG.

FIG. 4 is a system diagram of a conventional ultrasonic flaw detector. In the figure, X and Z indicate coordinate axes, and the Y axis is a direction perpendicular to the paper surface. 1 is a water tank, 2 is water filled in the water tank 1, and 3 is a water tank 1.
4 is a rotary table rotatably supported by the table 3 and 5 is a test material mounted and fixed on the rotary table 4. 6 is an ultrasonic probe, 7 is an ultrasonic probe 6
Is supported in such a manner that it can be driven in the Z-axis direction.
It is a moving body that supports. The moving body 8 can move on the water tank 1 in the Y-axis direction, and can move the support 7
Means for moving in the axial direction is provided. Reference numeral 10 denotes a motor that drives the support 7 in the X-axis direction, 11 denotes a motor that drives the ultrasonic probe 6 in the Z-axis direction, and 12 denotes a motor that drives the rotary table 4 to rotate in the θ direction shown in the drawing. Reference numerals 13, 14, and 15 denote encoders that output a number of pulses corresponding to the rotation amounts of the motors 10, 11, and 12, respectively. Reference numeral 16 denotes a motor controller that drives and controls the motors 10, 11, and 12.

Reference numeral 17 denotes a frequency divider that receives output pulses from the encoders 13, 14, and 15 and converts the pulses into pulses corresponding to the rotational position of the motor.
Reference numeral 18 denotes a pulser receiver, which outputs a pulse to the ultrasonic probe 6 to generate an ultrasonic wave, receives a reflected wave from the test material 5 input to the ultrasonic probe 6, and uses this as data. Output. Reference numeral 19 denotes a gate circuit peak hold circuit which passes only arbitrary data among the data output from the pulser receiver 18 and holds the peak value of the data. The depth range of the flaw detection from the surface of the test material 5 is determined by the gate circuit peak hold 19, and a peak value in the range can be extracted. Reference numeral 20 denotes an A / D converter, 21 denotes a CPU (central processing unit) for performing required calculations and controls according to a predetermined procedure, 22 denotes a memory for storing input data, and 23 denotes a signal input / output. An interface to perform. CP
The U21, the memory 22, and the interface 23 constitute a signal processing device. Reference numeral 24 denotes an oscilloscope for displaying a flaw detection waveform of the test material 5 based on a reception signal of the pulsar receiver 18.
25 is a monitor television (monitor T
V) and 26 are keyboards for inputting required data, commands and the like.

Here, the operation of the ultrasonic flaw detector will be described. CPU2
For 1, required numerical values are set from the keyboard 26, for example, the gate range of the gate circuit peak hold 19, the frequency division number of the frequency divider 17, the driving speed of the motors 10, 11, and 12. CPU21
Outputs a command signal to the motor controller 16 and the motor 1
0, 11, and 12 are driven to move the probe 6 to a predetermined scanning start point (origin). At this time, the A / D converter 20 is driven by the signal output from the frequency divider 17 and the CPU 21
Drives the pulse receiver 18 to transmit and receive ultrasonic waves. Received reflected wave is gate circuit peak hold
19, of which only the peak value within a predetermined depth range is taken out, and this peak value is the A / D
The converted value is converted into a digital value by the converter, and the converted value is stored at a predetermined address in the memory 22 according to a command from the CPU 21.

Thereafter, the motor 12 is continuously driven at a predetermined speed. During this driving, the encoder 15 outputs a pulse for each unit movement amount, and the frequency divider 17 outputs a pulse for each predetermined movement amount. The A / D is output for each pulse output from the frequency divider 17.
The converter 20 is driven, and the peak value is sequentially stored at a predetermined address in the memory 22. When this operation is repeated and the probe 6 returns to the origin again, the CPU 21 outputs a command signal to the motor controller 16 and drives the motor 10 to move the probe 6 by a predetermined amount toward the center. The above operation is repeated again to collect flaw detection data of the test material 5. When scanning of the entire surface of the test material 5 is completed in this manner, the CPU 2
1 fetches data from the memory 22, performs necessary processing on the data, and displays the result on the monitor TV25. As a result, the state of each flaw detection point in the cross section of the test material 5 at a predetermined depth is displayed on the monitor TV 25, and the position and size of the defective portion can be grasped.

[Problems to be solved by the invention]

By the flaw detection by the ultrasonic flaw detector, the position and the size of the defective portion existing in the test material 5 can be detected with a considerable accuracy. However, since the ultrasonic flaw detector does not take out the reflected waveform itself but merely takes out the peak value of the reflected wave, there is a limit in the detection accuracy, and the state of the defective portion is further detailed. I couldn't explore.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide an ultrasonic flaw detector capable of collecting a waveform itself of an ultrasonic reflected wave and optionally selecting a collecting method. It is in.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a transmitting / receiving unit that transmits an ultrasonic wave to the surface of a test material while continuously scanning the surface of the test material with an ultrasonic probe and receives a reflected wave thereof, An ultrasonic wave comprising: a signal processing unit that stores a digital value corresponding to the signal of the above in a storage unit and performs a predetermined process based on the stored value; and a display unit that performs display based on the process of the signal processing unit. In the flaw detection device, an A / D converter that converts the signal of the reflected wave into a digital value, a trigger detection circuit that detects a start signal of transmission and reception of the ultrasonic wave, and a position after inputting flaw detection point position information on the scanning path And a delay circuit that activates the A / D converter with a plurality of different delay times for each output of a detection signal of the trigger detection circuit. Provided with a waveform conversion unit was example, characterized in that a sampling selection means for commanding the respective delay times in the delay circuit to the signal processing unit.

(Operation)

When a command is given from the signal processing unit to the transmission / reception unit, a pulse is generated from the transmission / reception unit and transmission / reception of ultrasonic waves is started. On the other hand, the hold circuit inputs each piece of flaw detection point position information of the flaw detection points that are continuously scanned, and activates the trigger detection circuit when one flaw detection point is reached. In such a state, the pulse of the transmission / reception unit is detected by the trigger detection circuit of the waveform conversion unit, and the delay circuit of the waveform conversion unit is operated. The delay circuit outputs a delay signal after a plurality of different delay times specified by the sampling selection means. The output delayed signals sequentially activate the A / D converter of the waveform converter. On the other hand, the ultrasonic reflected wave signal received by the transmission / reception unit is input to the A / D converter, is converted into a digital value only when the A / D converter is in the operating state, and is stored in the storage unit of the signal processing unit. You.

The transmission and reception of the pulse of the transmission / reception unit is substantially one in spite of continuous scanning because the sampling operation is performed at high speed.
This can be regarded as being repeated at one of the flaw detection points, and the above-described sampling operation is repeated for each output, and each delay time which is different at each repetition is added by the sampling pitch. Therefore, when the predetermined repetition is completed, the waveform of each part of the ultrasonic reflected wave sampled by the sampling pitch is stored in the storage means of the signal processing unit. When the sampling is completed, the hold circuit is reset and the sampling is stopped. Then, when the next flaw detection point information is input, the hold circuit is again set, and the above sampling is executed again. Scanning continues without interruption during such a sampling period.

〔Example〕

 Hereinafter, the present invention will be described with reference to the illustrated embodiments.

FIG. 1 is a system diagram of an ultrasonic flaw detector according to an embodiment of the present invention. In the figure, the same portions as those shown in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. Numeral 30 denotes a waveform converter for inputting a signal from the parser receiver 18 and converting the signal into a digital value. As shown, the waveform conversion unit 30 includes a trigger detection circuit 30a, a delay circuit 30b, an A / D converter 30c, and a hold circuit 30d. The configuration of the delay circuit 30b will be described later with reference to FIG. The trigger detection circuit 30a detects a pulse output from the pulser receiver 18 to the probe 6 while the set signal from the hold circuit 30d is being input, and outputs the detection signal to the delay circuit 30b. Delay circuit 3
0b outputs a signal to the A / D converter 30c in a manner to be described later after the detection signal is input, and the A / D converter 30c is activated by this signal. The A / D converter 30c converts the ultrasonic reflected wave signal received by the pulsar receiver 18 into a digital value in its operating state. The hold circuit 30d is a trigger detection circuit 30 when a signal reaching the flaw detection point is input from the frequency divider 17 during scanning.
A set signal is output to a, and a reset signal is output when sampling at the flaw detection point is completed. 21 'is a CPU corresponding to the CPU 21 shown in FIG. CPU21 ′ is CPU21
In addition to the functions described above, a function for controlling the delay circuit 30b and other functions are provided. These functions will be described later.

FIG. 2 is a block diagram of the waveform converter shown in FIG. In the figure, the same parts as those shown in FIG. 1 are denoted by the same reference numerals. Delay circuit 30b 'is constituted by a first delay circuit 30b _1, the second delay circuit 30b ₂ and a third delay circuit 30b _3, and the diode D.

Next, the operation of this embodiment will be described with reference to the waveform diagram of the ultrasonic reflected wave shown in FIG. First, in the initial setting, the CPU 21 ', as shown in FIG.
Sets the Deire (sampling position) T _{D 1,} and setting the respective delay times to the second delay circuit 30b ₂ and a third delay circuit 30b ₃ T _D2, T _D3. In the case of this embodiment,
The delay time T _D2 and the delay time T _D3 are made equal. Further, a sampling pitch P _t (not shown) and a gate width Tg ′ are set, and the memory address is set to address 0.

The A / D converter 30c is reset, and each delay time T _D , T _D2 , T
_D3 is a first delay circuit 30b ₁ and a second delay circuit 30
b ₂ , output to the third delay circuit 30b ₃ and output to the pulser receiver 18
There detects this when activated trigger detection circuit 30a, the first delay circuit 30b ₁ starts to operate. After the delay time T _D elapses,
Conversion command to the first output signal from the delay circuit 30b ₁ A / D converter 30c is provided. Thereby, the reflected wave signal of the sampling point s ₁ ′ input at that time is A / D converted, and when the conversion is completed, the data is stored in the memory 22 and the A / D conversion is performed.
The converter 30c is reset again.

On the other hand, the output signal from the first delay circuit 30b ₁ Part time 2
It is also input to the delay circuit 30b _2, the second delay circuit 30b ₂ starts operating. When the delay time T _D2 elapses, the second delay circuit 30b
Signal is output from ₂ A / D converter 30c and the third delay circuit 30b _3. As a result, the A / D converter 30c sets the sampling point
The signal of s ₂ ′ is A / D converted, the data is stored in the memory 22, and the third delay circuit 30b ₃ starts operating.
Then, when the delay time T _D3 has elapsed, a signal is output from the third delay circuit 30b ₃ to the A / D converter 30c, and the sampling point s ₃ ′
Are A / D converted and stored in the memory 22. That is,
In the present embodiment, three points are sampled for one waveform in the repeated waveform of the reflected wave.

The CPU 21 'counts the number of A / D conversions,
Or by viewing the output of the third delay circuit 30b _3, to determine the end of sampling in one of the reflected waves, a delay time of the first delay circuit 30b ₁ in the next reflected wave _{(T D} + P _t)
And the same operation as above is repeated again. In this case, the delay times T _D2 , T _{D of} the second delay circuit 30b ₂ and the third delay circuit 30b _3
D3 does not change. The repetition of the above operation ends when the sampling of the gate width T _g ′ ends. Then, at the completion of the memory 22 so that data of the waveform during the period T _g 'shown in Figure 3 it is stored in the sampling pin Tutsi P _t.

The sampling operation described above is an operation at one flaw detection point on the scanning path of the test material 5. During the period of the sampling operation, the scanning is continuously performed without interruption. Strictly speaking, the sampling is not the sampling of the same flaw detection point. But,
The sampling time is extremely short compared to the scanning time required to move from one flaw detection point to the next flaw detection point, and therefore, the sampling can be considered to have been performed for the same flaw detection point, and even if it is considered as such, no sampling is performed. There is no inconvenience.

As described above, since the data stored in the memory 22 can be regarded as the waveform itself during the period _Tg 'shown in FIG. 3 at the same flaw detection point of the test material 5, the CPU 21' is provided with the function of analyzing this waveform. If you give it, you will be able to explore the reflected wave in detail. An example of such an analysis function is frequency analysis. That is, the peak value for each frequency can be obtained by frequency-analyzing the obtained reflected wave, whereby the defect of the test material 5 based on the mere peak value obtained by the gate circuit peak hold 19 in the conventional device can be obtained. Compared to the position and size of the part, more precise data about them can be obtained, and high-level flaw detection can be performed.

As described above, in the present embodiment, since a plurality of samplings are performed by shifting the pitch for each signal of the repetitive waveform signal, the waveform itself of the ultrasonic reflected wave signal can be extracted, and high-precision flaw detection can be performed. It can be carried out. Also, the sampling start position, pitch, and gate width can be set freely, and appropriate sampling can be performed.
Further, since the sampling can be started in synchronization with the scanning position by the hold circuit, the sampling at the predetermined flaw detection point position can be performed without interrupting the scanning, and the scanning time can be shortened. Furthermore, when the gate width is large, for example, in the extreme case where the gate width is from the surface to the bottom surface of the test material, or when the A / D converter has high performance, more rapid sampling can be performed. .

It should be noted that one delay circuit may be used instead of the three delay circuits in the above embodiment, and the delay time may be sequentially set by the CPU 21 '. In this case, the reset of the delay circuit may be performed using the output of the delay circuit. The number of samples for one of the repetitive waveforms is not limited to three, but may be two or four or more.

Further, in the description of the above-described embodiment, an example in which the inspection material is scanned for flaw detection has been described. However, the present invention is not limited to this, and can be applied to any type of flaw detection.

〔The invention's effect〕

As described above, in the present invention, a plurality of samplings are performed by shifting the pitch for each signal of the repetitive waveform signal, so that the waveform itself of the ultrasonic reflected wave signal can be taken out, and high-precision flaw detection can be performed. It can be performed. or,
The sampling start position, pitch, and gate width can be freely set, and appropriate sampling can be performed. Further, since the sampling can be started in synchronization with the scanning position by the hold circuit, the sampling at the predetermined flaw detection point position can be performed without interrupting the scanning, and the scanning time can be shortened. Furthermore, when the gate width is large, for example, in the extreme case where the gate width is from the surface to the bottom surface of the test material, or when the A / D converter has high performance, more rapid sampling can be performed. .

[Brief description of the drawings]

FIG. 1 is a block diagram of an ultrasonic flaw detector according to an embodiment of the present invention, FIG. 2 is a block diagram of a waveform converter shown in FIG. 1,
FIG. 3 is a waveform diagram of an ultrasonic reflected wave, and FIG. 4 is a system diagram of a conventional ultrasonic flaw detector. 5 ... Test material, 6 ... Probe, 18 ... Pulser receiver,
21 ': CPU, 22: Memory, 30: Waveform converter, 30a ...
... Trigger detection circuit, 30b ... Delay circuit, 30c ... A / D converter.

Claims (3)

(57) [Claims] 1. A transmitting / receiving unit for transmitting an ultrasonic wave to a surface of a test material while continuously scanning the surface of the test material with an ultrasonic probe and receiving a reflected wave thereof, and a digital value corresponding to a signal of the reflected wave. In a ultrasonic flaw detector comprising a signal processing unit for performing a predetermined process based on a value stored in the storage unit and performing a display based on the process of the signal processing unit, the reflected wave A / D that converts the digital signal into a digital value
A converter, a trigger detection circuit that detects a start signal of transmission and reception of the ultrasonic wave, a hold circuit that activates the trigger detection circuit until the end of sampling for that position after inputting the flaw detection point position information on the scanning path, and Along with providing a waveform conversion unit including a delay circuit that operates the A / D converter with a plurality of delay times different from each other for each output of the detection signal of the trigger detection circuit, the signal processing unit, An ultrasonic flaw detector comprising sampling selection means for instructing a delay time. 2. The ultrasonic flaw detector according to claim 1, wherein the number of the delay circuits is one, and the sampling selecting means sequentially sets a delay time for the delay circuits. . 3. The delay circuit according to claim 1, wherein said delay circuit comprises a plurality of delay circuits connected in series, and said sampling selection means sets a predetermined delay time for each of said plurality of delay circuits. An ultrasonic flaw detector wherein the delay time of the leading delay circuit connected in series is shifted by a predetermined sampling time for each output of the detection signal.