JPH02236159A - Waveform display apparatus of ultrasonic flaw detector - Google Patents

Abstract

PURPOSE:To obtain an ultrasonic flaw detector capable of accurately displaying an echo height by adding an ROM showing processing procedure, a measurement start point setting part and a data selection circuit to a conventional apparatus. CONSTITUTION:The echo from an object to be inspected is received by a receiving part 4 and sampled at a predetermined cycle to be converted to a digital value by an A/D converter 5. The converted data is successively divided at every predetermined number on the basis of the number of addresses of a display memory 16m and the measuring range of an echo waveform by a measuring start point setting part 21 and a measuring range setting part 14 and the data of the max. value among data is selected at every section by a selection circuit 22 to be stored in a waveform memory 16. These data are transmitted to the display memory 16m to be displayed on a display part 15 on the basis of the memory 16m. These processing means are stored in an ROM 20 to be processed under the control of a CPU 10. By this constitution, an echo height can be displayed accurately and, even when the echo height is smaller than an actual one, wrong judgement is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a waveform display device for an ultrasonic flaw detector for displaying an ultrasonic waveform on a display unit in an ultrasonic flaw detector. [Prior Art] Ultrasonic flaw detectors are known as devices that inspect the surface and internal conditions of objects without destroying them. In such an ultrasonic flaw detector, the reflected wave signal (echo) of the ultrasonic wave emitted from the object is processed appropriately and displayed as a waveform, but generally, the echo, which is an analog signal, is processed as is and sent to an oscilloscope. A means of displaying waveforms is adopted. However, in recent years, a digital ultrasonic flaw detector that digitally processes the echoes and displays the waveform has been proposed, for example, in Japanese Patent Laid-Open No. 63-95353. This digital ultrasonic flaw detector is explained with a diagram. Figure 10 is a system diagram of a digital ultrasonic flaw detector.
In the figure, 1 is an object to be inspected, 1f is a defect in the object to be inspected 1, and 2 is a probe which emits ultrasonic waves into the object to be inspected 1 and converts the reflected waves into electricity proportional to the ultrasonic waves. Convert to a target signal (echo). 3 is a transmitter that outputs pulses to the probe 2 to generate ultrasonic waves, and 4 is a receiver that receives echoes from the probe 2. The receiving section 4 includes an attenuation circuit 4a.
, an amplifier circuit 4b, and a detection circuit 4C.

5 is an A/D converter that converts the echo received by the receiver 4 into a digital value, 6 is a waveform memory that stores the data converted by the A/D converter 5, and 7 is an address of the waveform memory 6. This is an address counter. 8 is a timing circuit composed of a crystal oscillator, which controls the pulse output timing of the transmitter 3, the conversion timing of the A/D converter a5,
and controls the address specification timing of the address counter. 10 is a CPU (Central Processing Unit) that performs necessary controls such as processing data stored in the waveform memory 6 and driving the timing circuit 8; 11 is a RAM (Random Access Memory) that temporarily stores various parameters, data, etc.; memory),
12 is a ROM (read-only memory) that stores CPUIO processing procedures and the like. Reference numeral 13 denotes a sound velocity input section for inputting the speed (sound velocity) of ultrasonic waves propagating within the object to be inspected 1, and 14 is a measurement range setting section for inputting a desired measurement range in the object to be inspected 1. 15 is a liquid crystal display section composed of a predetermined number of liquid crystal dots arranged in a matrix;
6 is a display controller that controls the display of the liquid crystal display 15; 16m is a display memory that is provided in the display controller 16 and stores data to be displayed on the liquid crystal display 15. Reference numeral 18 indicates the main body of the ultrasonic flaw detector, which is composed of a part surrounded by a single point M line. Note that when inspecting the object 1 to be inspected using ultrasonic waves, the inspection is usually performed without bringing the probe 2 into direct contact with the object 1 to be inspected, with water interposed between the two.

Therefore, the object to be inspected 1 is placed in a water tank. In the figure, W
is a water tank, W. indicates the water put in tank W. Next, an outline of the operation of the ultrasonic flaw detector is shown in Fig. 11(a).
, (b) and the contents explanatory diagram of the waveform memory 6 shown in FIG. 12. Ultrasonic waves are emitted from the probe 2 in response to pulses from the transmitter 3, and their echoes are received by the receiver 4 and output.
FIG. 11(a) shows an echo waveform from the receiver 4 when the test is carried out using the water tank W as shown in FIG. 10. In this figure, time is plotted on the horizontal axis and echo size is plotted on the vertical axis. T is the transmitted echo that appears immediately when the ultrasonic wave is emitted from the probe 2, and S is the object to be inspected 1
F is the defect echo reflected from the defect 1f, B is the bottom echo reflected from the bottom of the object to be inspected 1, and B is the bottom echo of the tank W reflected from the bottom of the water tank W. show. This echo waveform is transmitted to the sequential A/D converter 5.
is converted into a digital value proportional to the size of the echo,
Stored in waveform memory. This will be explained using FIG. 11(b) and FIG. 12. Figure 11(b) is shown in Figure 11(b).
A part of the transmitted echo T and defective echo F shown in a) is shown, with the horizontal axis being extremely enlarged. In this diagram,
The black dots on the echo waveform indicate sampling points, and the points at time t.
~t,......j t-l~t▲. ,...
...indicates the sampling time. τ, is the sampling period. According to a command from the timing circuit 8, the echo at each sampling point is converted into digital value data by the A/D converter 5 and stored in the waveform memory 6. FIG. 12 shows how the converted data is stored in the waveform memory 6. That is, AH(.

、． . . . is the address of the waveform memory (these are represented by Axtt+), D<<. 》 ・・・・・・
... is the data stored at each address (these are
(represented by i}), and each data is stored in the order in which it was sampled and in the order of the addresses in the waveform memory as specified by the address counter. Next, the data stored in the waveform memory 6 is displayed on the liquid crystal display l.
5 will be explained. The maximum number of data that can be displayed on the liquid crystal display section 15 is equal to the number of horizontally arranged dots constituting the liquid crystal display section l5, which is also equal to the number of addresses in the display memory 16m. On the other hand, the number of addresses in the waveform memory 6 is relatively large compared to the number of dots, since all sampling data of the echo waveform must be stored therein. Even if the range to be displayed (measurement range) of the echo waveform is limited to a part, the sampling data included in the measurement range is usually greater than the number of dots mentioned above. Therefore, in order to display the echo waveform on the liquid crystal display section l5, the waveform memory 6
An address within the measurement range must be appropriately selected. The selection of this address will be explained below.

First, input the sound speed of the ultrasonic wave inside the object to be inspected 1 to the sound velocity input section 13, and set the length (measurement range) from the surface of the object to be inspected 1 to the depth to be measured in the measurement range setting section l4. . Now, τS: Sampling time 1, l: Measurement range v3: Sound speed t: Time for the ultrasonic wave to reciprocate within the measurement range ΔA: Number of addresses in the waveform memory 6 where echo waveforms within the measurement range are stored Dt: Liquid crystal display section If the number of dots in the horizontal direction is 15, then
(1) τS τs'vs Here, when trying to display the echo waveform of the measurement range across the entire horizontal direction of the liquid crystal display section 15, the number of addresses ΔA
, an address is selected for each ΔA/Dt (if it is not an integer, it is converted into an integer), the data stored in the selected address is sequentially transferred to the display memory 16m, and the data is displayed on the liquid crystal display section. 15, the echo waveform of the measurement range can be displayed. Note that since the interval between the transmitted echo T and the surface echo S is known, if data is sequentially stored in the waveform memory 6 starting from the data of the transmitted echo T, the address of the shell surface echo S in the waveform memory 6 is also known. From this address, addresses can be selected every ΔA/Dt. [Problem to be solved by the invention] When inspecting an object to be inspected l using an ultrasonic flaw detector, the length from the surface echo S to the defect echo F (defect 1
It is important to measure the position of f), and this length can be determined by the length in the horizontal axis direction between the surface echo S and the defect echo F of the displayed echo waveform. By the way, in the inspection of the object to be inspected 1, the same important thing as the above-mentioned length is to know the size of the defect 1f, which can be known from the echo height of the defect echo F. That is, an artificial defect is created in advance by machining or the like on an object of the same material and shape as the object to be inspected 1, and the magnitude of the echo of this artificial defect is recorded. The size of the defect 1f can be determined by comparing the height of the echo obtained from the inspection of the object to be inspected l with the size of the recorded echo. However, with the above conventional ultrasonic flaw detector, there are cases where the size of the defect 1f cannot be accurately measured. This will be explained using Figure 13. This figure is the first
This is a waveform diagram in which the time axis (horizontal axis) of defective echo F is extremely expanded among the echo waveform diagrams shown in Figure 1(a). In addition,
The vertical axis shows the echo height. Like other echo waveforms, the defect echo F is also sampled with a sampling period τ,
The data indicated by black dots on the waveform are sequentially stored in the waveform memory 6. Here, in order to display the echo waveform on the liquid crystal display section 15, the address of the waveform memory 6 is set to a number (ΔA/D
t ), and the data stored in the selected address is sampled at the sampling time t shown in the figure.
If it is the data at a-j E, the waveform of the defective echo displayed on the liquid crystal display section l5 will be a line connecting these data. As a result, although the actual peak value of the defect echo is at the height h, the peak value of the defect echo displayed on the liquid crystal display section 15 is at the sampling time t.
The height of the data at 1 becomes h', making it impossible to display an accurate echo height.

First, when a defect If exists in a product (object to be inspected 1), an inspection that depends on the echo height is often an inspection to determine whether the defect If is acceptable. Therefore, as mentioned above, if the displayed echo height h' is smaller than the actual echo height h, the product will be treated as a good product even though it is defective, and the inspection will be unreliable. The nature of whales will be severely damaged.

The purpose of the present invention is to solve the problems in the above-mentioned prior art,
An object of the present invention is to provide a waveform display device for an ultrasonic flaw detector that can more accurately display the echo height.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a transmitter that outputs a predetermined pulse to an ultrasound probe, a receiver that receives a signal from the ultrasound probe, and a transmitter that outputs a predetermined pulse to an ultrasound probe. An A/D converter that sequentially A/D converts the received signal at a predetermined sampling period, a waveform memory that stores the data converted by this A/D converter, and a waveform memory that stores the data stored in this waveform memory. In an ultrasonic flaw detector equipped with a display section for displaying information and a display memory for storing data to be displayed on the display section, a sorting means for sequentially sorting the data converted by the A/D converter into predetermined numbers; , a selection means for selecting data with a maximum value among the data in each division divided by the division means, and a data storage means for storing the data selected by the selection means in the waveform memory in the order of each division. It is characterized by having been established.

[For production]

When the echo from the object to be inspected is received by the receiver, this echo is sampled at a predetermined sampling period,
It is converted into a digital value by an A/D converter. The converted data is sequentially divided into a predetermined number based on the number of addresses in the display memory and the measurement range of the echo waveform, and for each division, the data with the maximum value among the divided data is selected. The data is stored in the waveform memory in the order of the sections. The data in the waveform memory is transferred to the display memory, and a display is made on the display section based on the data stored in the display memory.

〔Example〕

Hereinafter, the present invention will be explained based on illustrated embodiments.

FIG. 1 is a system diagram of a waveform display device of an ultrasonic flaw detector according to an embodiment of the present invention. In the figure, parts that are the same as those shown in Figure 10 are given the same reference numerals. The CPUIO is the same as the CPUIO shown in FIG. 1θ, but the ROM 20 that stores processing procedures differs from the conventional ROM 12 in some of its processing contents. 2l is a measurement start point setting section. 22 is A
This is a data selection circuit interposed between the /D converter 5 and the waveform memory 6. ROM 20, measurement start point setting section 21
, and the configuration other than the data selection circuit 22 is the same as the configuration shown in FIG. Here, the configuration of the data selection circuit 22 will be explained with reference to FIG. FIG. 2 is a diagram showing a first specific example of the data selection circuit. In the figure, parts that are the same as those shown in Figure 1 are given the same reference numerals and their explanations will be omitted. 22
Reference numeral 1 denotes a frequency dividing circuit that divides the frequency of the first clock signal a output from the timing circuit 8 and outputs the second clock signal b. A waveform processing memory 222 stores predetermined data for sequentially dividing the data converted by the A/D converter 5 into a predetermined number of sections. 223 is an address counter that sequentially specifies addresses in the waveform processing memory 222. 224 is a shift register to which data at an address designated by the address counter 223 is transferred. shift register 224
From then on, the third clock signal C is output to the address counter for each of the above sections. 225, 226 is a latch circuit, 227 is a comparator, 228 is a comparator 227
This is a composite circuit that is activated by the output signal d.
The data converted by the A/D converter 5 is sequentially latched into the latch circuit 225. On the other hand, the latch circuit 226 latches the largest data among the data after the first data in the above section. The comparator 227 compares the maximum value of the previous data latched by the latch circuit 226 with the data newly latched by the latch circuit 225, and outputs a signal d when the new data is larger.

When the signal d is input, the synthesis circuit 228 outputs the latch circuit 2.
The data latched in the latch circuit 226 is changed to the data latched in the latch circuit 225. Details of these operations will be described later.

Next, the operation of this embodiment will be explained with reference to the echo waveform diagram shown in FIG. 3 and the flowchart shown in FIG. 4. In Figure 3, T. S.F. B. ss is the same echo waveform as shown in Figure 11(a). The portion 15A surrounded by the dashed line is the desired measurement range to be displayed on the liquid crystal display section 15. ejl is the measurement range 15A as described above.
The width of,! , indicates the distance from the peak position (starting point) of the surface echo S to the left end of the measurement range 15A. In this embodiment, the above starting point is calculated from the elapsed time from the time when data storage started in the waveform memory 6 (assuming that the transmission pulse output and data storage start are performed at the same time) and the speed of sound (known). A method is taken. Note that the starting point for such distance calculation is not limited to the position of the surface echo S as in this embodiment, but may be any arbitrary position. It can be set to . In the following explanation, the position corresponding to the start address of the waveform memory 6 is assumed to have a distance of 0. Next, the operation when displaying a waveform as shown in FIG. 3 above on the liquid crystal display section 15 will be explained. First, the sound speed at which the ultrasonic wave propagates within the object to be inspected 1 (this sound speed is V) is inputted to the sound speed input section 13, and the measurement start point setting section 21 and measurement range setting section 14 set the respective starting points. The distance is from to the left edge of the measurement area, and the width 18 of the measurement area 15A
Enter.

Further, the number of addresses (AL (represented by Jl) of the display memory 16rn is a value determined according to the liquid crystal display section l5 and is stored in advance.
Express the number of (j) by KL. The measurement start point setting section 21 and measurement range setting section 14 are each composed of a rotary switch, and a unit numerical value Δl determined by rotation of a unit angle in one direction, for example, clockwise (positive direction), is added to the current value. is subtracted by rotation of unit angle in the opposite direction (negative direction). Addition like this. Subtraction is performed by the CPU 20 reading the operation amount of each rotary switch,
As a result, the distance 1s is set in the measurement start point setting section 21, and the distance 1l is set in the measurement range setting section l4, and these values 1m+111 determine the distance it (J!!-77!+ji) from the start point to the end point of the measurement range. *) is determined. Each of the above numerical values v,,j! ．． ,1,,KL are determined, the CPU 20 sequentially reads these numerical values according to the procedure stored in the ROM 12 (procedure P shown in FIG. 4). Next, in order to display the waveform in the measurement range 15A of the liquid crystal display section 15, it is determined by calculation how to select the data to be sequentially sampled, converted, and outputted by the A/D converter 5. (Procedure Pat)
. This operation will be explained below. Here, the distance between the surface and bottom surface of the object to be inspected L, that is, the distance between the surface echo S and the bottom surface echo B, is Lass, and the distance A between them is
When the number of data output from the /D converter 5 is ΔK, and the time from when the surface echo S is received until the bottom echo B is received is t, the following equation holds true. 2L! Il=vs − t−v3・ΔK・τ,...
... (3) Vg + τS (3) above. Equation (4) is the same as Equation (1) when distance Lsm is defined as two measurement ranges. Equivalent to (2). And (4
), A/ in the measurement range 15A of distance lIII
The number ΔK' of output data from the D converter 5 is vs τ
It becomes S. In this equation (5), 2/(V.・τ,)−β
Then, ΔK'-βIllI...
...(6). In order to display the measurement range 15A to the full extent of the liquid crystal display section 15, it is sufficient to select the number KL of addresses of the display memo IJl6m from the number ΔK' of the data and make it correspond to the address AL(Jl) of the display memory 16m. Therefore, the number ΔK
Taking the ratio α between ' and the number KL, we get ΔK' 2
It will be 1m. That is, the data outputted from the A/D converter 5 is sequentially selected in units of 1/α and displayed at address A of the display memory 16m.
If it corresponds to L(J), it becomes possible to display the echo waveform in the measurement range jlIl. On the other hand, the data at the left end of the measurement area at a distance of 1 s from the peak point (starting point) of the surface echo S indicates that the data at the peak point is the third data, and the distance l and the number of data in between are ( 6) From the formula, βl, so $+
It can be seen that this is the 13th data of β. Therefore, in order to display the measurement range 15A, it is sufficient to sequentially select data every l/α starting from the (S+βaS)th data. That is, the number l of data to be selected is expressed by the following equation.

iws+βffis+j/α・・・・・・・・・
- (8) In equation (8), j is the address number of the display memory 16m. In the calculation of formula (8), there are cases where the number j/α is not an integer, so in this case, the number l is converted to an integer by an appropriate method such as 4 to 5 (step Prs) - Then, the quantity In order to sequentially select data based on the data selection circuit 22, data to be stored in the waveform processing memory 222 of the data selection circuit 22 is created (step P+a). Next, according to the data in the waveform processing memory 222, the latch circuit 226
The maximum value data of is extracted and stored in the waveform memory 6 (procedure P+s) - the processing of procedure PI4 is executed by the CPU 20, and the processing of procedure Pil1 is executed by the data selection circuit 22. An explanation of these processes will be given later. The data stored in the waveform memory 6 is transferred to the corresponding address in the display memory 16m (procedure Pl &) - and the data at each address in the display memory 16m is displayed on the liquid crystal display unit 15 by the display controller 16 (procedure P, 7), the desired measurement range 15A can be displayed. Here, the waveform processing memory 222 of the data selection circuit 22
We will explain the data that should be stored in . Now, to make it easier to understand, the number l obtained by the operation of procedure p+s is
5". That is, ``This means that data (described later) selected at the timing of selecting every five pieces of data sequentially output from the A/D converter 5 is stored in the waveform memory 6. By the way, data is converted and outputted from the A/D converter 5 every pulse of the first clock a from the timing circuit 8 shown in FIG. The address of the waveform memory 6 can be changed and instructed every 5 pulses. For this purpose, the third clock C that advances the count of the address counter should be the frequency of the first clock a divided by 175. ．． Therefore, if the address counter is now operated with a high level signal "1", the third clock C is rl. 0. 0. O. 0. 1, 0,
0. 0, 0, 1. O. It is sufficient to construct the signal by a series of signals in which there are four low-level signals "0" between high-level signals rlJ, such as "0...".
In order to output such a signal, the waveform processing memory 22
2, address counter 223, and shift register 2
24 are provided. The address of the waveform processing memory 222 is A,%+j)(
1-0.1, 2. ......), and the data stored in one address is 8 bits (bits 50 to b).
y), in the case of i-5, the data stored in the waveform processing memory 222 is the data rlJ of the third clock C, as shown in the content explanatory diagram of the waveform processing memory shown in FIG. ．． The rOJ array is divided into 8-bit units and stored sequentially at addresses. In this case, data I)at stored at address As(.). >> is rl0000100 in binary notation, r8 4J in hexadecimal notation,
Data Dlm (1) is r00100001J in binary notation
, "21" in hexadecimal notation.
The process of creating data in the waveform processing memory 222 (the process of step Pl4 shown in FIG. 4) will be explained with reference to the flowchart shown in FIG. In order to perform the above processing, first, write the waveform processing memo I7 2
2 The integer indicating the order of each address in 2 is U, and the bit number of the data stored in each address (bit numbers b1 to bo shown in Figure 5) is P (Pth? bit is b.)
and rQJ, rl for a given one of these bits.
Let q be an integer indicating the number of times of processing to allocate J. Then, P=7, q=o, u=0 are first set (procedure Pzt shown in FIG. 6) - P-7 is set because of the processing of data output to the address counter, as will be described later. This is because it starts from bit number b. Next, the data of bit number b of the first address A va (.) is “1”.
”, and in order to move the processing to the next bit board (P-1
) is calculated, and (q + 1) is calculated to indicate the number of processing times after the end of rlJ allocation processing (step P0
). Procedure P. After completing the processing, the next number i (in the above example,
i=5) is read out (procedure P!3) - Then, it is determined whether the read number I is equal to the current number q, that is, whether the next process is the fifth process or not. is judged (procedure Px
n)-5, the data of the current bit number is set to "0" (procedure P■), and the bit number is set to the final bit number b. of the address. Is it determined whether or not? Step P2,). If it is not the final bit, (P-1) is calculated to move the process to the next bit number (procedure P.). Then, processing moves to the next bit, so
The number of times of processing is increased by one (q+1) is calculated (procedure Pz*), and it is determined whether the value of q at that time is equal to the number i (procedure P!!). If they are not equal, the process returns to step P■ again and repeats. P=-0 in procedure pza,
That is, when it is determined that the assignment to the last bit of the address has been completed, it is set to P-7 in order to move to the most significant bit b of the next address, and the operation of (u+1) is performed (procedure P, ). Also, step P2. So, q m i
, that is, if it is determined that it is the fifth process in the above example, the bit b. Let the data of rlJ be (procedure P3I)
, the process returns to step P0 again. In addition, in the data creation procedure of the waveform processing memory 222, "reading the next i" in step P0 does not necessarily mean that all numbers i are converted into integers in the process of step p+s shown in FIG. This is because the numbers are not necessarily equal and may differ by one or more. Also, in this embodiment, data is thinned out, so naturally i≧2. After the data in the waveform processing memory 222 is created and stored in this manner, these data are output as the third clock C. For this output, an address counter 223 and a shift register 224 are used. That is, the address counter 223 is counted by the second clock b obtained by dividing the first clock a by 178 by the frequency dividing circuit 221, and sequentially specifies the address of the waveform processing memory 222. When an address is designated by the address counter 223, the data at that address is transferred to the shift register 224 in parallel. The process after this transfer is shown in FIGS. 7(a) to 7(d) in the shift register 2.
This will be explained with reference to the content explanatory diagram of No. 24. FIG. 7(a) shows the waveform processing memo I72 shown in FIG.
2 shows a state in which data at address As(.,. As a result, data is output from the shift register 224 starting from the upper bit.One "0" is written in FIG. 7(b) as shown in FIG. 7(a). When shift register 2
24 most significant bit} (b?) is output, and each data in the shift register 224 is shifted one by one to the upper bit. In this way, the first
Shift register 2 is activated by eight consecutive pulses of clock a.
From 24 onwards, the third clock C is rl 0 0 0 0
1 0 0J is output. At this time, the data in the shift register 224 are all "
0”. Next, the address counter 223 advances the count by one, and the data at address All(1) is transferred to the shift register 224. This state is shown in Figure 7(d).
It is shown in By repeating this operation, the third clock C
is supplied to address counter 1 as a signal that generates "1" every five times. On the other hand, the first data output from the A/D converter 5 is latched by latch circuits 225 and 226. These data are input to the converter 227 and compared in size. Now, the data of the latch circuit 225 is DA, and the data of the latch circuit 226 is DA. Then, comparator 227
Then, DA≧D. A comparison is made, and when DA≧Da, a low level signal d is output. Initially, the same data is latched in each latch circuit 225 and 226 as described above, so it is DA-DI, and the signal d is output to the combining circuit 2.
28 is activated, and the data in the latch circuit 226 is rewritten to the data in the latch circuit 225 by the signal of the first clock a. When the next data is output from the A/D converter 5, this data is latched by the latch circuit 225,
The data is compared with the previously held data of the latch circuit 226 by the converter 227. In this case, if DA<DI, the next data is simply latched into the latch circuit 225, and the latch circuit 225 simply latches the next data.
26 data remains retained, but DA≧D. If so, a low level signal d is output from the comparator 227, the synthesis circuit 228 is activated, and the data in the latch circuit 226 is rewritten to the data in the latch circuit 225 by the pulse of the first clock a. By repeating the above operations, the latch circuit 226 always holds the maximum value data of the data up to that point.

Here, when the third clock C output from the shift register 224 is rOJ, there is no change in the above operations by the latch circuits 225 and 226 and the comparator 227. However, if the third clock is rlJ, the latch circuit 226
This “1” signal is input to the latch circuit 226, and the data held in the latch circuit 226, that is, the maximum value data, is output to the waveform memory 6 and at the same time, the latch circuit 226
The data held in 26 is cleared. On the other hand, since the signal "1" is also input to the address counter at the same time, the address counter 7 designates a new address in the waveform memory 6. Therefore, the latch circuit 22
The maximum value data outputted from the waveform memory 6 will be stored at the above-mentioned new address in the waveform memory 6. Through the above operations, data is stored in the waveform memory 6 in synchronization with every fifth output timing of data output from the A/D converter 5, and this stored data is the maximum value data among the five data before the fifth data. Therefore, the first
It is possible to reliably obtain the data h shown in Figure 3 or a value extremely close to this. FIG. 8 is a block diagram showing a second specific example of the data selection circuit. In the figure, parts that are the same as those shown in Fig. 2 are given the same reference numerals and explanations will be omitted. 222' is a waveform processing memory, which corresponds to the waveform processing memory 222 shown in FIG. This waveform processing memory 222' is composed of a 1-bit memory, whereas the waveform processing memory 222 of the previous specific example is composed of an 8-bit memory as shown in FIG. This specific example differs from the previous specific example in that the configuration of the waveform processing memory described above is different, and the frequency dividing circuit 2
21 and the shift register 224 is removed, and the other configurations are the same. In addition, as described later, R
Some of the processing procedures of OM20 are also different.

The operation of this specific example is shown in FIG. 9 by the waveform processing memory 222.
′ will be explained with reference to the content explanation diagram. As in the previous specific example, it is assumed that the number i obtained by the operation of the procedure pus is r5J. In this case, the waveform processing memory 222' is 1
Since it is a bit memory, the data storage process to this memory is different from the data storage process to the waveform processing memory 222 in the previous specific example, and data is stored in this memory in order from CPUIO to rl0000.
1ooootoo......'' bit signals may be stored one by one. This stored state is shown in Figure 9. That is, each address has 20 ROMs.
According to the processing procedure, 1-bit data rlJ and rOJ are stored from the CPUIO in the above order. In the ultrasonic flaw detection operation, the bit data stored in the waveform processing memory 222', which stores such 1-bit data, is transferred as a signal C by a signal from the address counter 223, which sequentially specifies addresses. Since the address counter 7 is outputted, the address counter 7 is counted up every five pulses of the first clock a, as in the previous example. The other operations in the waveform processing memory 222' are the same as the waveform processing memory 222 in the previous specific example. With such a configuration, a frequency dividing circuit and a shift register are not required in this specific example, and the overall configuration can be simplified, and the processing procedure of the ROM 20 can also be simplified. In the above embodiment, the data stored in the waveform memory 6 is processed according to the procedure PI& as shown in FIG.
However, in this embodiment, the number of addresses in the waveform memory 6 and the number of addresses in the display memory 16m are the same, and data from the waveform memory 6 is transferred to the display memory 1.
Data is transferred to the corresponding address of 6m. The reason why two identical memories are provided is that the operation of the probe 2, the conversion operation of the A/D converter 5, and the storage operation in the waveform memory 6 all follow the timing signal of the timing circuit 8. This is because the waveform display is desired to be displayed freely without being restricted by the timing signal of the timing circuit 8. This is achieved by separately providing the display memory 16m as in this embodiment and transferring the latest echo waveform data from the waveform memory 6 to the display memory 16m.

Furthermore, in inspections using ultrasonic flaw detectors, the degree of change in the measurement range is extremely small, and once the measurement range is set for a certain member, basically the measurement range cannot be changed for that member. There is nothing to do. Furthermore, when a certain measurement range is set, data related to it (including data stored in the waveform processing memory 222, 222')
is easy to remember, so even if there is a change in the measurement range, this is used if the relevant data is already stored. Therefore, in actual use, the processing of steps Pll to Pl4 and the sixth step shown in FIG.
The processing shown in the figure is almost never executed. From the above, the processing from data output in the A/D converter 5 to data storage in the waveform memory 6 is executed simultaneously (in real time) by hardware, resulting in high-speed processing.

In this way, in this embodiment, the data output from the A/D converter is divided into predetermined periods, and the maximum value data of the classification is stored in the waveform memory for each predetermined period, and this is stored in the display memory. Since the height of the echo waveform is transferred, the height of the echo waveform can be displayed even more accurately. Also, a waveform memory with a small capacity can be used. Furthermore, since a measurement start point setting section and a measurement range setting section are provided, any part of the echo waveform can be enlarged, enlarged, or reduced for display. Furthermore, as long as the measurement range is not set to a completely new value, data can be processed at high speed and thus displayed quickly. Note that if a switch is installed on the probe or other appropriate location to stop data transfer from the waveform memory to the display memory, the display of the echo waveform on the display can be fixed at the current state.
Echo waveforms or their data can be easily recorded.

〔Effect of the invention〕

As described above, in the present invention, the data output by the A/D converter is divided into a predetermined number of parts, the maximum value of the data in each division is stored in the waveform memory, and these data are stored in the display memory. Since the echo waveforms are transferred in order, the height of the echo waveform can be displayed even more accurately.

[Brief explanation of drawings]

FIG. 1 is a system diagram of a waveform display device of an ultrasonic flaw detector according to an embodiment of the present invention, FIG. 2 is a block diagram of a first specific example of the data selection circuit shown in FIG. 1, and FIG. 3 is a display 4 is a flowchart explaining the operation of the device shown in FIG. 1, FIG. 5 is a diagram explaining the contents of the waveform processing memory shown in FIG. 2, and FIG. 6 is a diagram showing the data in the waveform processing memory. A flowchart explaining the creation operation, FIG. 7(a). (b)
,(c). (d) is an explanatory diagram of the contents of the shift register shown in Fig. 2, Fig. 8 is a block diagram of a second specific example of the data selection circuit shown in Fig. 1, and Fig. 9 is a diagram for explaining the contents of the shift register shown in Fig. 8. An explanatory diagram of the contents of the memory. Figure 10 is a system diagram of the digital ultrasonic flaw detector. Figures 11 (a) and (b) are echo waveform diagrams and partially enlarged waveform diagrams. Figure 12 is the contents of the waveform memory. The explanatory diagram, FIG. 13, is an enlarged waveform diagram of the defect echo. l......Object to be inspected, 1f...
...Defect, 2...Probe, 3.
...... Transmitter section, 4...... Receiving section, 6... Waveform memory, 10...
...CPU, 13...Sound velocity input section, 1
4...Measurement range setting section, l5...
...Liquid crystal display section, 16...Display section controller, 16m...Display memory, 2
0・・・・・・・・・ROM, 21・・・・・・・・・
Measurement start point setting section, 22... Data selection circuit. Figure AM(S) AM(S) Figure Figure Figure Figure Figure Figure Figure? -Figure 11 (a) (b) Figure 12 Figure 13

Claims (1)

[Claims] a transmitter that outputs a predetermined pulse to the ultrasound probe; a receiver that receives the signal from the ultrasound probe;
An A/D converter that sequentially A/D converts the signal received by the receiver at a predetermined sampling period, a waveform memory that stores the data converted by the A/D converter, and a waveform memory that stores the data. In an ultrasonic flaw detector equipped with a display unit that displays the data that has been converted, and a display memory that stores the data to be displayed on the display unit, the data converted by the A/D converter is sequentially divided into a predetermined number of units. a selection means for selecting data with a maximum value among the data in each division divided by the division means, and data for storing the data selected by the selection means in the waveform memory in the order of each division. 1. A waveform display device for an ultrasonic flaw detector, characterized in that a storage means is provided.