JPH065860A - Thin film transistor and its production - Google Patents

Abstract

PURPOSE:To reduce leak current and improve transistor characteristics for a thin film transistor provided with an activating layer for an element on an insulating film by permitting the level density of an interface between the activating layer and the insulating film to be 1X10<11>/cm<2> or less. CONSTITUTION:A thin film transistor 10 is provided with an activating layer for an element on an insulating film 13. The level density of an interface between the activating layer 14 and the insulating film 13 is permitted to be 1X10<11>/cm<2> or less. Then, at least the front plane or rear plane or the side planes of the activating polysilicon layer that performs transistor operation is covered with silicon oxide formed by oxidizing the activating layer. The activating polysilicon layer formed on the insulating film is patterned so as to permit the width of the activating area of the transistor to be 1mum or less, the activating polysilicon layer is thermally oxidized and a thermal oxide film is grown on the interface between the insulating film and the activating polysilicon layer. Thus, the trap density is reduced and leak current is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and its manufacturing method.

[0002]

2. Description of the Related Art Thin film transistors, particularly thin film transistors having a polysilicon active layer, have started to be used in liquid crystal display devices, static random access memories (SRAM), and the like, and their technical importance has increased in recent years.

Polysilicon thin film transistors (hereinafter sometimes simply referred to as TFTs) have unfavorable characteristics such as a small on-current and a large off-current due to the effect of traps existing in the grain boundary of polysilicon. Improvement is desired.

Particularly in consideration of application to SRAM, it is very important to reduce the off current, that is, the leak current of the TFT in order to keep the data retention current small.

Regarding the leak current of the conventional TFT, it is considered that the tunnel current through the grain boundary trap is mainly as described in, for example, the technical report SDM90-141 (Kato, 1990) of the Institute of Electronics, Information and Communication Engineers. Therefore, efforts have been made to reduce this grain boundary trap. To this end, for example, a method of increasing the grains to substantially reduce the number of grain boundaries in which a single TFT is included, thereby reducing traps, and using hydrogen contained in plasma SiN are used. Then, the method of deactivating the trap is mainly adopted.

However, even if these methods are used, it cannot be said that satisfactory characteristics have been obtained yet, and the guideline for improving the characteristics is not clear. .

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and to provide a thin film transistor having excellent characteristics by reducing the leak current, and a method of manufacturing such a thin film transistor. The purpose is to provide.

[0008]

[Means and Actions for Solving the Problems] The inventors of the present invention have achieved the above-mentioned objects as a result of earnestly analyzing and examining the cause of the leak current of the TFT. I found that.

That is, according to the invention of claim 1 of the present application, in a thin film transistor in which an active layer of an element is formed on an insulating film, the interface state density existing at the interface between the active layer and the insulating film is 1 × 10 ¹¹ / cm ² that was below is a thin film transistor, wherein, thereby is obtained by achieving the above object.

According to a second aspect of the present invention, in a polysilicon thin film transistor in which an active layer of an element is formed on an insulating film, at least a front surface, a back surface and a side surface of the active layer polysilicon layer which operates as a transistor are formed. One of the thin film transistors is characterized in that one of them is covered with silicon oxide formed by oxidation of the active layer, whereby the above object is achieved.

According to the invention of claim 3 of the present application, an active layer of an element is formed on an insulating film, and at least one of a front surface, a back surface and a side surface of a region of the active layer polysilicon layer which operates as a transistor, A method of manufacturing a thin film transistor covered with silicon dioxide formed by oxidation of the active layer, comprising: forming an active layer polysilicon layer formed on an insulating film so that a width of an active region of the transistor is 1 μm or less. After patterning, the active layer polysilicon layer is thermally oxidized to provide a method for manufacturing a thin film transistor characterized in that a thermal oxide film is grown at an interface between the insulating film and the active layer polysilicon layer. The above object is achieved.

The invention according to claim 4 of the present application is the method for manufacturing a thin film transistor according to claim 3, wherein the insulating film is silicon dioxide, and achieves the above object.

The operation of the present invention will be described below together with the background of the present invention. First, the analysis of the leak current will be described.

FIG. 1 is a schematic sectional view showing a structural example of a TFT according to the present invention. As shown in FIG. 1, the TFT of the present invention is a thin film transistor in which an active layer of an element is formed on an insulating film 13 (in FIG. 1, reference numeral 14 indicates a polycrystalline silicon film for forming an active layer in this structural example). 2), the interface state density existing at the interface between the active layer 14 and the insulating film 13 is set to 1 × 10 ¹¹ / cm ² or less.

In the structural example illustrated in FIG. 1, the gate electrode 1 is formed on the upper surface of a substrate 11 having an insulating property at least on the surface.
2 is formed, the substrate 11 is made of, for example, a silicon oxide substrate, and the gate electrode 12 is made of, for example, polycrystalline silicon doped with p-type impurities. A gate insulating film 13 made of a silicon oxide film is formed so as to cover the gate electrode 12. Formed on the gate insulating film 13 is a polycrystalline silicon film 14 which becomes an active layer of the thin film transistor 10 to be formed.
A silicon dioxide film 15 is formed on the surface of the polycrystalline silicon 14. The source / drain regions 1 are formed on the polycrystalline silicon film 14 on both sides of the gate electrode 12.
6, 17 are formed. In addition, the polycrystalline silicon film 14 between the source / drain regions 16 and 17 is the channel region 1.
It will be 8. With this configuration, the thin film transistor 10 is formed.

The leak current characteristic of such a PMOS TFT is shown in FIG. The horizontal axis represents the drain voltage Vd, the vertical axis represents the drain current Id, and the gate voltage is 0V. Therefore, the drain current indicates the leak current of the TFT. Figure 2
As a result of detailed examination of the characteristics shown in (1), the present inventors have obtained the following new findings.

(1) The absolute value of the drain voltage Vd is 0.3.
Below V, there is a relationship between Id and Vd: Id ∝ √Vd, which indicates that Id is a generated recombination current based on the classical Shockley-Reed-Hole model.

(2) In the region where | Vd | is about 0.3 to 3 V, Id is an electric field acceleration type (field enhancing type) generated current.

(3) When | Vd | becomes 3 V or more, band-to-band tunnel type leak current begins to appear, and at 6 V or more, this component becomes the main component of the leak.

Further, it is known that the above (2) is theoretically expressed as I _FE = I ₀ exp (α√E). Here, I _FE is an electric field acceleration type generated current, I ₀ is a low electric field, that is, a generated current corresponding to the above (1), α is a coefficient related to a material constant, and E is an electric field strength. Therefore, it is understood that it is necessary to reduce I ₀ in order to suppress the leakage currents of (1) and (2) above.

According to the Shockray-Lead-Hole model, carrier generation rate (amount corresponding to leakage current)
Is Is expressed as Where A is a constant determined by the substance, Nt
Is the trap density or generated recombination center density, Et is the trap energy level, Ei is the intrinsic energy level, k is the Boltzmann constant, and T is the absolute temperature. From this relationship, it can be seen that in order to reduce U, it is necessary to reduce Nt.

Considering Nt, Nt can be expressed as Nt = Nb · t _poly + Nsf + Nsb. Here, Nb is the trap volume density of the polysilicon layer, t _poly is the thickness of the polysilicon layer, and Ns
b and Nsf represent interface state densities on the back and front of the polysilicon, respectively. FIG. 3 schematically shows this state, and here, the vicinity of the drain of the TFT is shown.

As shown in FIG. 3, near the edge of the drain region 17 of the TFT, the depletion layer 40 expands toward the channel region 18, and a leak current is generated in this depletion layer.

Although Si bulk traps (corresponding to Nb) have been mainly considered as the generation center of the leak current in the depletion layer, the interface state densities Nsf and Nsb are also considered to be important generation centers. To be

It is well known that the interface state density between Si and an oxide film changes depending on the method of forming the interface.
Is the smallest in the case of direct thermal oxidation, approximately 10 ¹⁰ / cm
It is about ² . On the other hand, SiO _{2 is} deposited on Si by CVD or the like.
However, depending on the conditions, the formation of 10 ¹² / cm ²
It is generally a moderate value.

Conventionally, when a TFT is formed, a method of forming a Si layer on SiO ₂ by a CVD method or the like is used, and the interface state density here is -10 ¹² / cm ² (10
^-12 / cm ² or slightly less. Same in the present specification). This was an unavoidable problem as long as a general process was used. This is because it is difficult to reduce the interface state density of the lower surface (interface side) of the deposited Si layer by thermal oxidation or the like.

On the other hand, since it is easy to oxidize the surface of the deposited Si layer, Nsb can be easily reduced in FIG. On the other hand, Nsf is usually about 10 ¹² / cm ² .

Various analyzes have been attempted up to now for the trap density in the bulk, but this is also about 10 ¹² / cm 2.
It is considered to be about ² (Nb × t _poly ) or less.

Therefore, in order to investigate the influence of the interface state density, a polysilicon active layer having both sides thermally oxidized, one side only oxidized, and neither one being oxidized are prepared.
N _T was obtained from the analysis of the generated current in the low electric field region.

As a result, a result of no oxidation 2.5 × 10 ¹² / cm ² single-sided oxidation 9 × 10 ¹¹ / cm ² double-sided oxidation 1 × 10 ¹⁰ / cm ² was obtained. According to the result of the transmission electron microscope observation, it is not recognized that the polysilicon grains are particularly affected by the oxidation, and Nb is almost constant.

As is clear from this result, reducing the interface state density by oxidation has a direct effect on significantly reducing N _T. Therefore, this causes TF
It becomes possible to reduce the leakage current of T.

The present invention has been made as a result of the detailed study as described above. Particularly, in order to reduce the leak current, it is very important to keep the interface state density of the TFT low as described above. It was completed as a result of discovering that it is important.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. However, as a matter of course, the present invention is not limited to the examples described below.

Example 1 FIG. 4 is a sectional view showing the structure of the TFT of this example, (a) is a sectional view in a direction parallel to the channel, and (b) is a sectional view in a direction perpendicular to the channel.

In the TFT of this embodiment, the gate insulating film is 13
And 13 '. This inner insulation film 1
3'is formed by oxidizing the channel region of the TFT.

That is, the TFT of this embodiment is a polysilicon thin film transistor in which an active layer 14 of an element is formed on an insulating film, and at least the surface of the active layer polysilicon layer 14 where the transistor operates, the back surface and the side surface. At least one of them is covered with silicon dioxide formed by oxidation of the active layer.

Next, a method of manufacturing the thin film transistor 10 of this embodiment will be described with reference to FIG. 5 showing the manufacturing process (No. 1) and FIG. 6 showing the manufacturing process (No. 2).

First, the first step shown in FIG. 5A is performed. In this step, for example, a silicon oxide substrate is used as the substrate 11 having an insulating property at least on the surface.

Chemical vapor deposition method (hereinafter referred to as CVD method)
The polycrystalline silicon film 21 is formed on the upper surface of the substrate 11 by
Is formed to have a thickness of, for example, 50 nm. After that, the portion indicated by the chain double-dashed line in FIG. 5A of the polycrystalline silicon film 21 is removed by ordinary photolithography and etching to form polycrystalline silicon patterns 22, 23, 24.

Then, as shown in FIG. 5B, the polycrystalline silicon patterns 22 to 2 are formed by, for example, an ion implantation method.
Boron difluoride (BF ₂ ⁺ ) is introduced into No. 4. As the ion implantation conditions at this time, for example, the ion implantation energy is set to 20 keV and the dose amount is set to 1 × 10 ¹⁵ / cm ² . Then, the polycrystalline silicon pattern 22 is made p-type to form the gate electrode 12. In the same way as above,
The polycrystalline silicon patterns 23 and 24 are made p-type to form p ⁺ source / drain extraction electrodes 25 and 26.

Then, a silicon oxide film is formed on the surface of the gate electrode 12 and the surfaces of the p ⁺ source / drain extraction electrodes 25 and 26 by, for example, a low pressure CVD method using silane as a reaction gas to a thickness of 35 nm. To form. In order to further improve the insulating property, dry oxidation is performed at 850 ° C. to further increase the thickness of the silicon oxide film to about 5 nm. Therefore, the silicon oxide film 27 having a thickness of 40 nm is formed. The silicon oxide film 27 on the gate electrode 12 becomes the gate insulating film 13.

Then, the silicon oxide film 27 on the p ⁺ source / drain extraction electrodes 25 and 26 is partially removed by ordinary photolithography and etching to form contact holes 28 and 29. As a result,
The structure of (b) is obtained.

Then, the second step is performed. In this process,
As shown in FIG. 5C, the inside of the contact holes 28 and 29 and the gate insulating film 1 are formed by a low pressure CVD method.
An amorphous silicon film 30 is formed on the surface of the silicon oxide film 27 and the surface of the silicon oxide film 27 to have a thickness of, for example, 30 nm. As the film forming conditions, for example, the film forming temperature is set to 450 ° C. and the pressure of the film forming atmosphere is set to 0.67 kPa.

After that, annealing treatment (low temperature solid-phase crystallization treatment) is performed at 600 ° C. for 30 hours to crystallize the amorphous silicon film 30 to form the polycrystalline silicon film 14. The crystal grain size of the polycrystalline silicon film 14 is, for example, about 2 μm.

Next, as shown in FIG. 6D, the portion indicated by the chain double-dashed line of the polycrystalline silicon film 14 is removed by ordinary photolithography and etching, and the remaining polycrystalline silicon film 14 is used as an active region. The forming part 19 is formed.

After that, the third step is performed. In this process,
First, as shown in FIG. 6 (e), dry oxidation at 850 ° C. is performed to oxidize the active region forming portion 19, and 10 nm to 10 nm
A silicon oxide film 15 having a thickness of 20 nm is formed. Therefore, due to this oxidation, the film thickness of the active region forming portion 19 is 1
It becomes 0 nm to 20 nm. Although dry oxidation is used here, oxidation may be performed, for example, by wet oxidation.

By this oxidation, oxygen diffuses in the gate oxide film 13 to oxidize the lower surface of the channel polysilicon, and the second gate oxide film 13 'is formed as shown in FIG. 6 (e).
Is formed. Oxidation of the lower surface is determined by the initial film thickness of the gate oxide film, the amount of oxidation of the active layer, and the correlation of the width of the active layer. Can be sufficiently oxidized to reduce

If the film thickness of the active region forming portion 19 is too thin (eg, about 5 nm or less),
Since the ON resistance becomes very large, it becomes very difficult for the ON current to flow. Therefore, the ON / OFF ratio is significantly reduced. Therefore, the active region forming portion 19 made of the polycrystalline silicon film 14 is finally formed to have a thickness of, for example, about 10 nm.

Next, as shown in FIG. 6F, source / drain regions 16 and 17 are formed in the active region forming portions 19 on both sides of the gate electrode 12. Source / drain region 1
To form 6, 17, first, an ion implantation mask (not shown) is formed on the gate electrode 12 by ordinary photolithography. After that, by a normal ion implantation method, for example, p-type impurities are introduced into the active region forming portion 19 to form the source / drain regions 16 and 17. As the ion implantation conditions, for example, boron difluoride (BF ₂ ⁺ ) is used as the p-type impurity, and the ion implantation energy is 1
0 keV, dose amount of 1 × 10 ¹⁴ / cm ^{2 to} 5 × 10 ¹⁴
Set to / cm ² . The source / drain region 16,
The active region forming portion 19 between 17 becomes the channel region 18.

After that, a wiring process is performed as shown in FIG. In the wiring step, first, as shown in FIG. 7A, the interlayer insulating film 31 is formed on the entire surface on the silicon oxide film 15 side by, for example, the CVD method. The interlayer insulating film 31 is made of, for example, silicon oxide.

Then, the source / drain lead-out electrodes 25, 25 are formed by ordinary photolithography and etching.
Contact holes 32 and 33 are formed in the interlayer insulating film 31 and the silicon oxide film 27 on 26.

Then, boron difluoride (BF ₂ ⁺ ) is ion-implanted on the entire surface by, for example, an ion implantation method, and then 1
A rapid thermal annealing (RTA) process is performed for 10 seconds in a temperature atmosphere of 050 ° C. to remove the source / drain region 16,
Activate 17

Next, as shown in FIG. 7B, for example, a wiring metal film 34 is formed inside the contact holes 32 and 33 and on the surface of the interlayer insulating film 31 by, for example, a sputtering method.
To form. The wiring metal film 34 is formed of, for example, aluminum or an aluminum alloy.

Subsequently, the portion indicated by the chain double-dashed line of the wiring metal film 34 is removed by ordinary photolithography and etching, and the p ⁺ source / drain extraction electrode 2 is formed.
Metal wirings 35, 36 connected to 5, 26 are formed.

Thereafter, as shown in FIG. 7C, a plasma silicon nitride (p-SiN) film, for example, is formed as a passivation film 37 on the entire surface on the side of the metal wirings 35 and 36 by, for example, the plasma CVD method. Further, the metal wirings 35 and 36 are sintered.

In the above manufacturing method, the thin film transistor 10
Of the channel length (L) of the thin film transistor 10 and the grain width of 1/3 or more of the channel width (W) of the thin film transistor 10 are formed, and then the polycrystalline silicon film 14 is formed. Since the surface of the crystalline silicon film 14 is oxidized to reduce the film thickness of the polycrystalline silicon film 14, a thin polycrystalline silicon film 14 having a large grain size can be obtained.

Further, since the lower surface of the polycrystalline Si film is also thermally oxidized, the interface state density can be sufficiently lowered.

By forming the active region forming portion 19 with the polycrystalline silicon film 14, the off current of the TFT can be reduced, and a TFT having excellent characteristics with high mobility can be realized.

FIG. 8 shows a PMOSTF produced by the above method.
An example of the characteristic of T is shown. The channel width W and the channel length L of the TFT are 0.5 and 0.7 μm, respectively, showing the comparison between the active layer oxidized (shown by I) and the active layer not oxidized (shown by II). There is.

As is clear from FIG. 8, in the TFT in which the interface layer density is reduced by oxidizing the active layer, the off current (Vg = 0 V) can be reduced by two digits or more as shown in Graph I. . Also, the switching characteristics are sharp.

FIG. 9 shows an example of characteristics of TFTs of two sizes formed by the above method. In this case, W
= (10 μm) (graph Ia) and W = 0.5 μm (graph Ib) are compared, but when W = 10 μm, there is a tendency that the off current does not always decrease sufficiently as shown by Ia. is there. This is presumably because the lower surface of the active layer was not sufficiently oxidized because W was wide.

FIG. 1 shows this more systematically.
It is 0. FIG. 10 shows the on-current and off-current of the TFT,
It is shown with respect to the amount of oxidation of the polysilicon layer. The thickness of the polysilicon layer before oxidation is 30 nm, the thickness after reduction by oxidation is shown in the lower row of the horizontal axis, and the amount of oxidation is shown in the upper row.

Ion is drain voltage, gate voltage-
It is a value at 3.3V. Also, Ioff is −
Values at 3.3V and 0V.

As is apparent from this, when W = 10 μm, the decrease in Ioff is gentle with respect to the amount of oxidation, and it is not a great improvement. At W = 0.5 μm, Iof
f decreases greatly with oxidation. However, when the amount of oxidation was too large (oxidized by 24 nm), the channel poly-Si partially disappeared, and Ion also decreased and the variation became large.

Considering the above results and the mechanism of oxidation together, the following can be said.

SiO on the substrate 103 as shown in FIG.
_When oxidizing the polysilicon 101 formed on the ₂ 102, the lower surface of the polysilicon 101 is oxidized by SiO ₂ 10
Oxygen diffused in 2 reaches the lower surface of the poly-Si layer 101 and is carried out, so that the oxidation proceeds more easily near the polysilicon pattern edge. As shown in FIG. 12, which shows the oxidation process, the oxidation occurs in a wedge shape as is generally known, and this wedge-shaped region 105 is called a bird's beak.
The structure after sufficient oxidation is shown in FIG.

When the length of the bird's beak is x (see FIG. 12), x is a function of the thickness t ₁₀₂ of the oxide film ₁₀₂ , the oxidation temperature, the oxidation time and the like.

In order to obtain the effect of the present invention well, the length x of the bird's beak 105 is 1/2 of the width W of the poly-Si active layer.
The above is desirable.

For example, when t ₁₀₂ is 35 nm, 800 ° C.
X is approximately 0.4 μm when oxidized (20 nm on Si substrate)
It will be about. Therefore, W is about 0.8 μm or less. When t ₁₀₂ is 10 nm, x is 0.1
Since it is about μm, W = 0.2 μm.

Although t ₁₀₂ , oxidation conditions, and W are problems that are determined by the design of the device and the process, in an LSI process in which heat treatment at high temperature for a long time is desired to be minimized,
In particular, it is desirable to reduce the width of W so that the lower surface of the poly-Si layer is oxidized with a small amount of oxidation.
It can be said that the range of m or less is practically used.

Therefore, as shown in FIG. 10, the TFT with W = 10 μm, which is much larger than x, does not sufficiently improve the characteristics, but with W = 0.5 μm, the characteristic is significantly improved.

As an effect of further reducing W,
Hydrogen that inactivates the interface states and the bulk trap is Si
Since it diffuses more easily in SiO ₂ than inside, it is considered that hydrogen having a smaller W can easily reach hydrogen in the poly-Si or the interface of the lower layer through SiO ₂ in the lower layer. Therefore W
It is considered that in the TFT having a small value, hydrogen is more effectively inactivated in the trap.

[0073]

According to the present invention, it is possible to provide a thin film transistor with reduced leakage current and excellent characteristics, and a method for manufacturing the same.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a configuration of the present invention, and is a schematic configuration cross-sectional view of a thin film transistor.

FIG. 2 is a diagram showing leakage current characteristics (relationship between drain current and leakage current).

FIG. 3 is a schematic explanatory diagram of an interface state density.

FIG. 4 is a cross-sectional view showing the TFT of Example 1.

FIG. 5 is a diagram showing a manufacturing process (No. 1) of the TFT of Example 1.

FIG. 6 is a diagram showing a manufacturing process (No. 2) of the TFT of Example 1.

FIG. 7 is a diagram showing a wiring manufacturing process in the first embodiment.

FIG. 8 is a diagram showing a characteristic example of the TFT of Example 1;

FIG. 9 is a diagram showing a characteristic example of the TFT of Example 1;

FIG. 10 is a diagram showing the relationship between the amount of polysilicon oxidized and the on-current and off-current.

FIG. 11 is an explanatory view of the action of the oxidation mechanism.

FIG. 12 is an explanatory view of the action of the oxidation mechanism.

FIG. 13 is an explanatory view of the action of the oxidation mechanism.

[Explanation of symbols]

 10 Thin Film Transistor 13 Insulating Film (Gate Insulating Film) 13 ′ Silicon Oxide Formed by Oxidation of Active Layer 14 Active Layer Forming Polysilicon Layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location 8617-4M H01L 21/265 P

Claims (4)

[Claims] 1. A thin film transistor having an active layer of an element formed on an insulating film, wherein an interface state density existing at an interface between the active layer and the insulating film is 1 or less.
A thin film transistor having a density of x10 ¹¹ / cm ² or less. 2. In a polysilicon thin film transistor in which an active layer of an element is formed on an insulating film, at least one of a front surface, a back surface and a side surface of a region of the active layer polysilicon layer which operates as a transistor has the active layer of the active layer. A thin film transistor, which is covered with silicon oxide formed by oxidation. 3. An active layer of a device is formed on an insulating film, and at least one of a front surface, a back surface and a side surface of a region of the active layer polysilicon layer where a transistor operates is formed by oxidation of the active layer. A method for manufacturing a thin film transistor covered with silicon dioxide, comprising: patterning an active layer polysilicon layer formed on an insulating film so that a width of an active region of the transistor is 1 μm or less; A method of manufacturing a thin film transistor, characterized in that a thermal oxide film is grown at an interface between the insulating film and the active layer polysilicon layer by thermally oxidizing the silicon layer. 4. The method of manufacturing a thin film transistor according to claim 3, wherein the insulating film is silicon dioxide.