KR100650715B1 - Method for forming contact plug of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a contact plug of a semiconductor device. The disclosed method includes providing a silicon substrate having a transistor composed of a gate electrode and a source / drain region, and having an interlayer insulating film formed on a front surface thereof to cover the transistor, and etching the interlayer insulating film to form a silicon substrate. Forming a contact hole exposing a source / drain region, growing a first epitaxial silicon layer to a thickness that does not fill the contact hole, and heat-treating the resultant substrate on which the first epitaxial silicon layer is grown. Making an amorphous silicon portion of the upper part of the first epitaxial silicon layer into an epitaxial silicon layer, growing a second epitaxial silicon layer with a thickness filling a contact hole on the first silicon epitaxial layer, and exposing the interlayer insulating layer. And CMP the second and first silicon epitaxial layers as much as possible. According to the present invention, in the method of growing the epitaxial silicon by heat treatment after depositing amorphous silicon, the epitaxial silicon film of full thickness is formed by dividing it twice, thereby increasing the thickness of the amorphous layer of the epitaxial silicon film. By making it thin, heat processing time can be shortened.

Description

Method for forming contact plug of semiconductor device

1A to 1F are cross-sectional views illustrating processes for forming a contact plug of a semiconductor device according to the present invention.

* Description of Major Symbols in Drawings *

11: silicon substrate 12: device isolation film

13: gate electrode 14 source / drain region

15: spacer 16: interlayer insulating film

17: contact hole 18: the first epi silicon layer

18a: epitaxial layer 18b: amorphous layer

18c: epitaxial layer 19: second epitaxial silicon layer

19a: epitaxial layer 19b: amorphous layer

The present invention relates to a method of forming a contact plug of a semiconductor device, and more particularly, to a method of forming a contact plug of a semiconductor device capable of shortening a heat treatment time when forming a contact plug using epitaxial silicon.

In general, when epitaxial silicon is used as a contact plug of a semiconductor device, low contact resistance may be obtained even at a relatively low doping concentration. This low doping concentration results in relatively low dopant diffusion, which is essential for improving the refresh characteristics due to transistor characteristics and thermal stress as the size of the semiconductor device becomes smaller.

In more detail, as the semiconductor device becomes smaller, the gate length becomes smaller, and excessive ion implantation is performed to obtain an appropriate threshold voltage. As a result, the refresh characteristic margin is gradually reduced. In addition, in order to obtain an appropriate current driving force, the contact resistance is being lowered. Accordingly, when polysilicon is used as the contact plug material, phosphorus (P) doping of approximately 5E19 to 1E20 orders is obtained to obtain an appropriate contact resistance. Doing

However, when the doped phosphorus (P) as described above is diffused into the junction or the cell transistor by a subsequent thermal process, it may adversely affect the refresh characteristics. In addition, in order to improve refresh characteristics, the doping is further added to the contact plug. In addition, the diffusion of phosphorus in the polysilicon used as the contact plug halves the effect of the doping. Of course, if the phosphorous doping is lowered unconditionally, since the contact resistance is increased to greatly reduce the current driving force of the device, it is essential to secure appropriate process conditions. In addition, defects exist at the interface between the silicon layer and the contact plug in the active region, thereby degrading device reliability.

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In order to solve this problem, a method of using epitaxial silicon as a plug material has been proposed. If epitaxial silicon is used as the plug material, the contact resistance can be lowered because the interfacial properties are excellent even though the phosphorus doping concentration is low.

However, since the process must be performed at a high temperature, there is a problem that the semiconductor characteristics due to the high temperature is deteriorated.

Therefore, a method called solid phase epitaxy (SPE) has been studied as a method for forming epitaxial silicon at low temperature, which deposits amorphous silicon at a low deposition temperature and then grows the epitaxial silicon by subsequent heat treatment. Way.

However, in general, silicon deposited with SPE has a dual structure in which epitaxial silicon grows to some extent depending on the interface state, and amorphous silicon is formed, and when it is heat-treated at a temperature of 550 to 650 ° C. for several hours, the whole is crystallized to epitaxial silicon. However, such a long heat treatment process may be a problem in mass production.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of shortening the heat treatment time when forming a contact plug using epitaxial silicon.

In order to achieve the above object, the present invention provides a silicon substrate comprising a transistor formed of a gate electrode and a source / drain region, the interlayer insulating film formed on the front surface to cover the transistor; Etching the interlayer insulating layer to form a contact hole exposing a source / drain region of a silicon substrate; Growing a first epitaxial silicon layer to a thickness not filling the contact hole; Heat-treating the substrate product in which the first epitaxial silicon layer is grown to form an amorphous silicon portion of the upper portion of the first epitaxial silicon layer as an epitaxial silicon layer; Growing a second epitaxial silicon layer to a thickness to fill a contact hole on the first silicon epitaxial layer; And CMPing the second and first silicon epitaxial layers to expose the interlayer insulating layer.

Here, the method of the present invention, after the step of forming the contact hole, and before the step of growing the first epitaxial silicon layer, residual oxide on the surface of the source / drain region of the silicon substrate exposed by the contact hole Or after the cleaning to remove the etching residues, further comprising the step of heat treatment to a temperature of 700 ~ 1000 ℃ to remove the natural oxide film remaining on the surface.

In addition, the first epitaxial silicon layer is grown to a thickness of 200 ~ 1500Å by a chemical vapor deposition method at a temperature of 530 ~ 650 ℃, the epitaxial layer excluding the amorphous silicon layer of the first epitaxial silicon layer of 100 ~ 1000Å The thickness of the first epitaxial silicon layer is formed using Si2H2Cl2, H2 and PH3 gas, and the PH3 gas flows at a flow rate of 0 to 500 sccm, and the heat treatment of the first epitaxial silicon layer is 550 to 650 ° C. The process proceeds in a hydrogen atmosphere in-situ at a temperature of 2 to 30 minutes under vacuum.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.                     

1A through 1G are cross-sectional views illustrating processes for forming a contact plug of a semiconductor device according to the present invention.

Referring to FIG. 1A, a gate electrode 13 is formed on a silicon substrate 11 having an isolation layer 12, and then source / drain regions 14 are formed in the substrate surface on both sides of the gate electrode 13. To form. Subsequently, spacers 15 are formed on both sides of the gate. Here, the gate electrode 13 may be understood as a stacked structure of a gate oxide film, a gate conductive film, and a hard mask film.

Next, an interlayer insulating film 16 is formed on the substrate 11 to cover the gate electrode 13 including the spacer 15.

Referring to FIG. 1B, the interlayer insulating layer 16 is selectively removed to form a contact hole 17 exposing the source / drain regions 14 of the substrate. In this case, the contact hole refers to a landing plug contact that defines a bit line contact or a storage node contact region.

Subsequently, dry and wet cleaning are performed on the surface of the source / drain region 14 of the silicon substrate 11 exposed by the contact hole 17 to remove residual oxides or etching residues, and then 700 to 1000 ° C. The heat treatment is performed at a temperature of to remove the natural oxide film remaining on the exposed surface of the substrate source / drain region 14.

Referring to FIG. 1C, the first epitaxial silicon layer 18 is formed on the surface of the contact hole 17 and the surface of the interlayer insulating layer 16 at a temperature of 530 ° C. to 650 ° C. by using a chemical vapor deposition (LPCVD) method. To grow the contact hole to a thickness of 200 ~ 1500Å. Here, the reaction gas uses Si2H2Cl2, H2 and PH3, PH3 is a flow rate of 0 ~ 500sccm. At this time, the phosphorus doping concentration may be adjusted according to the PH3 gas flow rate.

The epitaxial layer 18a is formed from the surface of the contact hole silicon substrate, and the first epitaxial silicon layer 18 is grown according to a temperature of heat applied when the epitaxial layer 18a is deposited. If abnormal, the amorphous layer 18b is grown. At this time, the epitaxial layer 18a is grown to a thickness of about 100 ~ 1000Å according to the deposition temperature.

Referring to FIG. 1D, the grown first epitaxial silicon layer 18 is heat-treated in a hydrogen atmosphere in-situ at a temperature of 550 ° C. to 650 ° C., so that the first epitaxial silicon layer 18 may be The amorphous layer 18b is crystallized into the epitaxial layer 18c. At this time, the heat treatment is carried out in a vacuum state for a time of 2 to 30 minutes.

Referring to FIG. 1E, a second epitaxial silicon layer 19 is grown on the first epitaxial silicon layer 18. Here, the epitaxial layer 19a is also formed at the bottom of the second epitaxial silicon layer 19, and the amorphous layer 19b is formed at the top of the second epitaxial silicon layer 19.

Referring to FIG. 1F, etching back or CMP is performed to remove the amorphous layer 19b of the grown second epitaxial silicon layer and the amorphous layer 18b formed on the interlayer insulating layer.

According to the present invention, a method of forming a plug for reducing contact resistance with a silicon substrate has been generally used to deposit epitaxial silicon and then grow epitaxial silicon by heat treatment.

In order to shorten the heat treatment time of the process, the first epitaxial silicon layer is thinly formed to a thickness where the contact hole is not embedded, and the amorphous layer formed on the first epitaxial silicon layer is formed as an epitaxial layer through heat treatment. By growing the second epitaxial silicon layer on the first epitaxial silicon layer, the heat treatment time for crystallizing the amorphous layer into the epitaxial layer can be shortened.

According to the present invention, as a method for forming an epitaxial silicon layer with a contact plug, the first epitaxial silicon layer is thinly formed to have a contact hole-free thickness, and the amorphous layer formed on the first epitaxial silicon layer is subjected to epi by heat treatment. By making the epitaxial layer and growing the second epitaxial silicon layer on the first epitaxial silicon layer, the thickness of the non-crystalline layer of the epitaxial silicon layer can be reduced to shorten the heat treatment time for crystallizing the amorphous layer into the epitaxial layer. . Accordingly, it is possible to reduce the burden of a long heat treatment time to improve the device characteristics.

In addition, it is possible to predict the growth of epitaxial silicon to some extent even in the in-situ heat treatment after depositing a single silicon amorphous layer without using a double silicon layer using the in-situ heat treatment shown in the present invention. It can also be used to form contacts using this.

While the invention has been shown and described with reference to certain preferred embodiments, it will be appreciated that the invention can be modified and modified in various ways without departing from the spirit or scope of the invention as set forth in the following claims. One of ordinary skill in the art will readily know.

Claims (5)

Providing a silicon substrate having a transistor formed of a gate electrode and a source / drain region, and having an interlayer insulating film formed on a front surface thereof to cover the transistor; Etching the interlayer insulating layer to form a contact hole exposing a source / drain region of a silicon substrate; Growing a first epitaxial silicon layer to a thickness not filling the contact hole; Heat-treating the substrate product in which the first epitaxial silicon layer is grown to form an amorphous silicon portion of the upper portion of the first epitaxial silicon layer as an epitaxial silicon layer; Growing a second epitaxial silicon layer to a thickness to fill a contact hole on the first silicon epitaxial layer; And CMPing the second and first silicon epitaxial layers to expose the interlayer dielectric layer; Contact plug forming method of a semiconductor device comprising a. The method of claim 1, wherein after the forming of the contact hole and before growing the first epitaxial silicon layer, residual oxide or etching is performed on a surface of a source / drain region of the silicon substrate exposed by the contact hole. After the cleaning to remove the residue, the method of forming a contact plug of the semiconductor device further comprising the step of heat treatment at a temperature of 700 ~ 1000 ℃ to remove the natural oxide film remaining on the surface. The epitaxial layer of claim 1, wherein the first epitaxial silicon layer is grown to a thickness of 200 to 1500 kPa by a chemical vapor deposition method at a temperature of 530 to 650 ° C., except for the amorphous silicon layer of the first epitaxial silicon layer. A method for forming a contact plug in a semiconductor device, characterized by growing at a thickness of 100 to 1000 Å. The method of claim 1, wherein the first epitaxial silicon layer is formed of Si 2 H 2 Cl 2, H 2, and PH 3 gas, and the PH 3 gas flows at a flow rate of 0 to 500 sccm. According to claim 1, wherein the heat treatment for the first epi silicon layer is carried out in a hydrogen atmosphere in-situ at a temperature of 550 ~ 650 ℃, and proceeds in a vacuum state for a time of 2 to 30 minutes A contact plug forming method for a semiconductor device, characterized in that.

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