JP3494304B2 - Method for manufacturing thin film semiconductor device - Google Patents
Method for manufacturing thin film semiconductor deviceInfo
- Publication number
- JP3494304B2 JP3494304B2 JP03393093A JP3393093A JP3494304B2 JP 3494304 B2 JP3494304 B2 JP 3494304B2 JP 03393093 A JP03393093 A JP 03393093A JP 3393093 A JP3393093 A JP 3393093A JP 3494304 B2 JP3494304 B2 JP 3494304B2
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- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor device
- thin film
- gate insulating
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、薄膜半導体装置の製造
方法に係り、特に、薄膜半導体装置におけるゲ−ト絶縁
膜の界面特性の改良を図った薄膜半導体装置の製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film semiconductor device, and more particularly to a method of manufacturing a thin film semiconductor device in which the interface characteristics of a gate insulating film in the thin film semiconductor device are improved.
【０００２】[0002]
【従来の技術】従来、この種の薄膜半導体装置として
は、例えば薄膜トラジスタと称されるものがある。図６
にはかかる薄膜トランジスタの一例が示されおり、以
下、同図を参照しつつこの薄膜トランジスタの製造プロ
セスについて概略的に説明する。この薄膜トランジスタ
は、ガラス基板２０上にｐｏｌｙ−Ｓｉからなる半導体
活性層２１を形成し、その後、ゲ−ト絶縁膜２２を堆積
し、さらにｐｏｌｙ−Ｓｉからなるゲ−ト電極２３を形
成する。そして、ゲ−ト電極２３形成後、イオン注入に
より、リン又はボロンをゲ−ト電極２３に注入すると共
に、半導体活性層２１のチャンネル方向（図６において
紙面左右方向）の両側にイオン注入することによりソ−
ス領域２４ａとドレイン領域２４ｂとを形成する。この
後、アニ−ル処理によりド−パントの活性化を行う。そ
して、層間絶縁膜２５を堆積後、コンタクト孔２６ａ，
２６ｂを層間絶縁膜２５及びゲ−ト絶縁膜２２に穿設し
て電極２７ａ，２７ｂを設けることによって薄膜トラン
ジスタが完成される。2. Description of the Related Art Conventionally, as a thin film semiconductor device of this type, there is one called a thin film transistor, for example. Figure 6
Shows an example of such a thin film transistor, and hereinafter, a manufacturing process of this thin film transistor will be schematically described with reference to FIG. In this thin film transistor, a semiconductor active layer 21 made of poly-Si is formed on a glass substrate 20, a gate insulating film 22 is deposited thereafter, and a gate electrode 23 made of poly-Si is further formed. Then, after the gate electrode 23 is formed, phosphorus or boron is implanted into the gate electrode 23 by ion implantation, and ions are implanted into both sides of the semiconductor active layer 21 in the channel direction (left and right direction of the paper in FIG. 6). Because of
Forming a drain region 24a and a drain region 24b. After that, the dopant is activated by an annealing treatment. After depositing the interlayer insulating film 25, the contact holes 26a,
A thin film transistor is completed by forming 26b in the interlayer insulating film 25 and the gate insulating film 22 and providing electrodes 27a and 27b.
【０００３】ところで、いわゆるＬＳＩの製造技術にお
いて、Ｓｉを約１０００℃前後の酸素雰囲気中で酸化さ
せることにより、良好な界面特性を有するシリコン酸化
膜を形成できることは、公知、周知のことである。一
方、上述のような薄膜トランジスタは、近年液晶ディス
プレイ装置に用いるられることが多いが、この場合、装
置を安価なものとするために絶縁特性が良好で且つ安価
なガラス基板を用いることが前提となる。ところが、ガ
ラス基板は１０００℃もの高温には耐え得ないことから
上述したようなＬＳＩにおけるゲ−ト絶縁膜の製造方法
を用いることはできない。そのため、これに代わる技術
として例えば、常圧ＣＶＤ法、減圧ＣＶＤ法、プラズマ
ＣＶＤ法、スパッタリング法等が提案されているが、こ
れらの方法により得られるゲ−ト絶縁膜は、先の１００
０℃前後の酸素雰囲気中でＳｉを酸化させることにより
得られるゲ−ト絶縁膜に比して、未だ十分満足できるも
のではない。By the way, in the so-called LSI manufacturing technology, it is well known and well known that a silicon oxide film having good interface characteristics can be formed by oxidizing Si in an oxygen atmosphere at about 1000.degree. On the other hand, the thin film transistor as described above is often used in a liquid crystal display device in recent years, but in this case, it is premised that a glass substrate having good insulating properties and inexpensive is used in order to make the device inexpensive. . However, since the glass substrate cannot withstand a temperature as high as 1000 ° C., the method of manufacturing a gate insulating film in an LSI as described above cannot be used. Therefore, for example, an atmospheric pressure CVD method, a low pressure CVD method, a plasma CVD method, a sputtering method, etc. have been proposed as an alternative technique. The gate insulating film obtained by these methods is 100
It is not yet sufficiently satisfactory as compared with a gate insulating film obtained by oxidizing Si in an oxygen atmosphere at about 0 ° C.
【０００４】そこで、これら常圧ＣＶＤ法等により形成
されるゲ−ト絶縁膜に比してさらに良好な界面特性のゲ
−ト絶縁膜を得る技術として、ＥＣＲ（Electron Cyclo
tronResonance) プラズマＣＶＤ装置を用いてゲ−ト絶
縁膜を堆積させる方法が提案されている（例えば、T.W.
Little et al., Extended Abstracts of the 23rd and
Materials, 1991,pp.644〜646 参照）。Therefore, as a technique for obtaining a gate insulating film having better interface characteristics than those of the gate insulating film formed by the atmospheric pressure CVD method or the like, ECR (Electron Cyclo
tronResonance) A method of depositing a gate insulating film using a plasma CVD apparatus has been proposed (for example, TW
Little et al., Extended Abstracts of the 23rd and
Materials, 1991, pp.644-646).
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このＥ
ＣＲプラズマＣＶＤ装置を用いた技術にしても、先の常
圧ＣＶＤ法等に比して相対的に界面特性が良好なゲ−ト
絶縁膜が得られるというに過ぎず、薄膜半導体装置に求
められる特性を満足するに十分なゲ−ト絶縁膜を得るに
至っていないという問題があった。However, this E
Even if a technique using a CR plasma CVD apparatus is used, a gate insulating film having relatively good interface characteristics can be obtained as compared with the atmospheric pressure CVD method and the like, which is required for a thin film semiconductor device. There has been a problem that a gate insulating film sufficient to satisfy the characteristics has not been obtained yet.
【０００６】本発明は、上記実情に鑑みてなされたもの
で、優れた界面特性を有するゲ−ト絶縁膜を形成するこ
とのできる薄膜半導体装置の製造方法を提供するもので
ある。The present invention has been made in view of the above circumstances, and provides a method of manufacturing a thin film semiconductor device capable of forming a gate insulating film having excellent interface characteristics.
【０００７】[0007]
【課題を解決するための手段】本発明に係る半導体装置
の製造方法は、ソ−ス及びドレイン領域が一部に形成さ
れた半導体活性層をガラス基板上に配設し、この半導体
活性層を覆うようにゲ−ト絶縁膜を設け、このゲ−ト絶
縁膜上にゲ−ト電極を設け、さらに前記ゲート電極及び
前記ゲ−ト絶縁膜を覆う層間絶縁膜を形成してなる薄膜
半導体装置の製造方法において、前記ゲ−ト絶縁膜の形
成工程は、ガラス基板を１００℃以下に保持しつつシリ
コンを含む絶縁部材を前記半導体活性層を含む前記ガラ
ス基板上に堆積させる第１の工程と、前記堆積された絶
縁部材に対し界面準位の減少させるため、窒素、酸素及
び水素からなる群から選ばれた雰囲気下で４００〜６０
０℃の熱処理を施す第２の工程と、を具備するものであ
る。特に、第１の工程における絶縁部材の堆積は、ＥＣ
ＲプラズマＣＶＤ法により行うのが好適である。また、
第２の工程において、熱処理は窒素、酸素及び水素から
なる群から選ばれた２以上の気体の混合気中で行うよう
にしても好適である。According to the method of manufacturing a semiconductor device of the present invention, a semiconductor active layer having source and drain regions partially formed is provided on a glass substrate, and the semiconductor active layer is formed. A gate insulating film is provided so as to cover the gate insulating film, and a gate electrode is provided on the gate insulating film.
In the method of manufacturing a thin film semiconductor device, which comprises forming an interlayer insulating film covering the gate insulating film, in the step of forming the gate insulating film, the glass substrate is kept at 100 ° C. or lower and the glass substrate is sealed.
A first step of depositing an insulating member containing cones on the glass substrate containing the semiconductor active layer , and nitrogen, oxygen, and oxygen in order to reduce an interface state with respect to the deposited insulating member.
400-60 in an atmosphere selected from the group consisting of hydrogen and hydrogen.
Der which includes a second step, a heat treatment of 0 ℃
It In particular, the deposition of the insulating member in the first step is
It is preferable to use the R plasma CVD method. Also,
In the second step, the heat treatment is preferably performed in a mixture of two or more gases selected from the group consisting of nitrogen, oxygen and hydrogen.
【０００８】[0008]
【作用】ゲ−ト絶縁膜は、１００℃以下の基板温度の下
でＥＣＲ−ＣＶＤ法により堆積され、その後、４００乃
至６００℃の熱処理を施すことによってゲ−ト絶縁膜の
界面準位が低下し界面特性の向上したものとなる。その
ため、薄膜半導体装置においては、キャリアの移動度、
しきい値の向上に寄与することとなり信頼性の高い薄膜
半導体装置が提供されることとなる。The gate insulating film is deposited by the ECR-CVD method at a substrate temperature of 100 ° C. or lower, and then heat-treated at 400 to 600 ° C. to lower the interface state of the gate insulating film. The interface characteristics are improved. Therefore, in the thin film semiconductor device, carrier mobility,
This contributes to the improvement of the threshold value, and a highly reliable thin film semiconductor device is provided.
【０００９】[0009]
【実施例】以下、図１乃至図４を参照しつつ本発明に係
る薄膜半導体装置の製造方法について説明する。ここ
で、図１は本発明に係る薄膜半導体装置の製造方法によ
り製造された薄膜半導体装置の一例を示す縦断面図、図
２及び図３は本発明に係る薄膜半導体装置の製造方法を
説明するための主要な工程における縦断面図、図４は本
発明に係る薄膜半導体装置の製造方法によって形成され
るゲ−ト絶縁膜の特性を従来との比較において説明する
ための特性線図、図５は本発明に係る薄膜半導体装置に
より形成されるゲ−ト絶縁膜の界面特性を評価するため
の特性評価試験の概略を説明するための試験回路の概略
図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a thin film semiconductor device according to the present invention will be described below with reference to FIGS. Here, FIG. 1 is a longitudinal sectional view showing an example of a thin film semiconductor device manufactured by the method for manufacturing a thin film semiconductor device according to the present invention, and FIGS. 2 and 3 explain a method for manufacturing a thin film semiconductor device according to the present invention. 5 is a vertical cross-sectional view in the main steps for manufacturing the same, FIG. 4 is a characteristic diagram for explaining characteristics of a gate insulating film formed by the method of manufacturing a thin film semiconductor device according to the present invention in comparison with a conventional method, and FIG. FIG. 3 is a schematic view of a test circuit for explaining the outline of a characteristic evaluation test for evaluating the interface characteristics of the gate insulating film formed by the thin film semiconductor device according to the present invention.
【００１０】先ず、本発明に係る薄膜半導体装置の製造
方法により製造された薄膜半導体装置について図１を参
照しつつ説明すれば、この薄膜半導体装置の基本的な構
成は、この種の従来の薄膜半導体装置と同じである。し
たがって、以下の構造の説明は概略に止めることとす
る。この薄膜半導体装置は、ｐｏｌｙ−Ｓｉからなる半
導体活性層２、ソ−ス領域３ａ及びドレイン領域３ｂが
ガラス基板１上の略同一平内に形成され、これら半導体
活性層２、ソ−ス領域３ａ、ドレイン領域３ｂ及びガラ
ス基板１の一部を覆うようにゲ−ト絶縁膜４が形成され
ている。そして、ゲ−ト絶縁膜４の上にはゲ−ト電極５
が設けられると共に、このゲ−ト電極５及びゲ−ト絶縁
膜４を覆うように層間絶縁膜６が形成されている。さら
に、層間絶縁膜６及びゲ−ト絶縁膜４を貫通するように
電極層７ａ，７ｂが形成されてなるものである。First, a thin film semiconductor device manufactured by the method for manufacturing a thin film semiconductor device according to the present invention will be described with reference to FIG. 1. The basic structure of this thin film semiconductor device is the conventional thin film of this type. It is the same as the semiconductor device. Therefore, the following description of the structure will be briefly described. In this thin film semiconductor device, a semiconductor active layer 2 made of poly-Si, a source region 3a and a drain region 3b are formed in substantially the same plane on a glass substrate 1, and these semiconductor active layer 2, source region 3a, A gate insulating film 4 is formed so as to cover the drain region 3b and a part of the glass substrate 1. A gate electrode 5 is formed on the gate insulating film 4.
And an interlayer insulating film 6 is formed so as to cover the gate electrode 5 and the gate insulating film 4. Further, electrode layers 7a and 7b are formed so as to penetrate the interlayer insulating film 6 and the gate insulating film 4.
【００１１】次に、上記構成の薄膜半導体装置の製造プ
ロセスについて図２及び図３を参照しつつ説明する。先
ず、ガラス基板１上にａ−Ｓｉを約１０００オングスト
ロ−ム程度着膜させ、次にエキシマレ−ザを用いたアニ
−ルを行うことにより結晶化を施してｐｏｌｙ−Ｓｉ膜
を得、さらに、このｐｏｌｙ−Ｓｉ膜をフォトリソグラ
フィ法により島状にパタ−ニングすることにより半導体
活性層２を得る（図２（ａ）参照）。尚、このｐｏｌｙ
−Ｓｉ膜のパタ−ニングの際、パタ−ニングの結果得ら
れる半導体活性層２の端部（図２において紙面左右方向
の両端部）の傾斜が３０度以下となるようにする。Next, a manufacturing process of the thin film semiconductor device having the above structure will be described with reference to FIGS. First, a-Si is deposited on the glass substrate 1 to a thickness of about 1000 Å, and then annealed using an excimer laser for crystallization to obtain a poly-Si film. This poly-Si film is patterned into an island shape by a photolithography method to obtain a semiconductor active layer 2 (see FIG. 2A). In addition, this poly
At the time of patterning the -Si film, the inclination of the end portions of the semiconductor active layer 2 (both end portions in the left-right direction of the paper in FIG. 2) obtained as a result of the patterning is set to 30 degrees or less.
【００１２】次に、ＥＣＲプラズマＣＶＤ法を用いてシ
リコン酸化膜を堆積させる。すなわち、基板温度２３
℃、マイクロ波パワ−４００Ｗ、ガス流量ＳｉＨ4 ：Ｏ
2 ＝３：９sccm、ガス圧力１ｍＴorr の諸条件の下でシ
リコン酸化膜を約１０００オングストロ−ム程度堆積す
る。そして、５００℃の窒素雰囲気中で１時間の熱処理
を行う（図２（ｂ）参照）。熱処理完了後、Ｔａ（タン
タル）を約１５００オングストロ−ム程度堆積させ、例
えばフォトリソグラフィ法によりパタ−ニングしてゲ−
ト電極５を形成する（図３（ａ）参照）。続いて、シャ
ワ−ド−プ法により、リンを注入し自己整合的にソ−ス
領域３ａ及びドレイン領域３ｂを形成する。ここで、本
実施例におけるリンの注入条件は、５％ＰＨ3 ／Ｈ2 を
用いて１１０Ｋｅｖ、４×１０15リン原子／ｃｍ2であ
る。Next, a silicon oxide film is deposited by using the ECR plasma CVD method. That is, the substrate temperature 23
° C., the microwave power -400W, gas flow rate SiH 4: O
2 = 3: 9 sccm, under a gas pressure of 1 mTorr, a silicon oxide film is deposited to a thickness of about 1000 Å. Then, heat treatment is performed for 1 hour in a nitrogen atmosphere at 500 ° C. (see FIG. 2B). After the heat treatment is completed, Ta (tantalum) is deposited to a thickness of about 1500 Å and patterned by, for example, a photolithography method.
The contact electrode 5 is formed (see FIG. 3A). Subsequently, phosphorus is injected by the shower doping method to form the source region 3a and the drain region 3b in a self-aligned manner. Here, the implantation conditions of phosphorus in this example are 110 Kev using 5% PH 3 / H 2 and 4 × 10 15 phosphorus atoms / cm 2 .
【００１３】さらに、ド−パントの活性化として５００
℃の窒素雰囲気中で２乃至５時間の熱処理を行う。この
後、シリコン酸化膜を約７０００オングストロ−ム程度
堆積して層間絶縁膜６を形成し、コンタクト孔８ａ，８
ｂを層間絶縁膜６及びゲ−ト絶縁膜４に穿設する（図１
参照）。そして、このコンタクト孔８ａ，８ｂにＡｌ−
Ｃｕを堆積させ、パタ−ニングすることにより電極層７
ａ，７ｂを形成し（図１参照）、薄膜半導体装置が完成
する。Further, as activation of the dopant, 500
Heat treatment is performed for 2 to 5 hours in a nitrogen atmosphere at ℃. Thereafter, a silicon oxide film is deposited to a thickness of about 7,000 Å to form an interlayer insulating film 6, and contact holes 8a, 8
b is formed in the interlayer insulating film 6 and the gate insulating film 4 (see FIG. 1).
reference). Then, in the contact holes 8a and 8b, Al-
The electrode layer 7 is formed by depositing Cu and patterning.
a and 7b are formed (see FIG. 1), and the thin film semiconductor device is completed.
【００１４】次に、本実施例によるゲ−ト絶縁膜４の界
面特性の良否を図４を参照しつつ説明する。先ず、本実
施例の製造プロセスによって形成されたゲ−ト絶縁膜４
の特性を評価する方法としては、この種の特性評価方法
としてよく知られている水銀プロ−ブ法が好適である。
図５には、水銀プロ−ブ法を模式的に表した説明図が示
されており、同図を参照しつつ概略的にこの方法を説明
すれば、この方法は、評価しようとする絶縁膜１０をシ
リコンウエファ１１上に形成し、このシリコンウエファ
１１を接地する一方、絶縁膜１０には水銀からなる電極
１２を介して交流電圧を印加し、その印加電圧を変化さ
せることによっていわゆるＣ−Ｖ特性線を得て、このＣ
−Ｖ特性線によって絶縁膜の特性評価を行うものであ
る。尚、図５において可変コンデンサ１３は印加電圧を
調整するためのものである。Next, the quality of the interface characteristics of the gate insulating film 4 according to this embodiment will be described with reference to FIG. First, the gate insulating film 4 formed by the manufacturing process of this embodiment.
The mercury probe method, which is well known as a characteristic evaluation method of this kind, is suitable as a method for evaluating the characteristics.
FIG. 5 is an explanatory view schematically showing the mercury probe method. The method will be roughly described with reference to the figure. 10 is formed on a silicon wafer 11 and the silicon wafer 11 is grounded, while an AC voltage is applied to the insulating film 10 through an electrode 12 made of mercury, and the applied voltage is changed to change the so-called CV voltage. Get the characteristic line,
The characteristic of the insulating film is evaluated by the −V characteristic line. The variable capacitor 13 in FIG. 5 is for adjusting the applied voltage.
【００１５】図４には上述の水銀プロ−ブ法により得ら
れたいわゆるＣ−Ｖ特性が示されている。尚、図４
（ａ），（ｂ）において、横軸は酸化膜に印加されるバ
イアス電圧であり、縦軸は正規化した酸化膜容量であ
る。また、図４（ａ），（ｂ）において、Ｃoxは負のバ
イアス電圧を印加した際の酸化膜容量の飽和値である。
先ず、図４（ａ）には、基板温度２３℃（室温）の下で
ＥＣＲプラズマＣＶＤ法を用いてシリコン酸化膜を堆積
させた直後におけるＣ−Ｖ特性線（同図において実線で
表された特性線イ）と、従来のように比較的高温の基板
温度、すなわち基板温度４００℃の下で堆積されたシリ
コン酸化膜のＣ−Ｖ特性線（同図において点線で表され
た特性線ロ）とが、それぞれ表されている。FIG. 4 shows a so-called CV characteristic obtained by the above-mentioned mercury probe method. Incidentally, FIG.
In (a) and (b), the horizontal axis is the bias voltage applied to the oxide film, and the vertical axis is the normalized oxide film capacitance. In addition, in FIGS. 4A and 4B, C ox is the saturation value of the oxide film capacitance when a negative bias voltage is applied.
First, in FIG. 4A, a CV characteristic line (represented by a solid line in the figure) immediately after depositing a silicon oxide film by using the ECR plasma CVD method at a substrate temperature of 23 ° C. (room temperature). Characteristic line a) and a CV characteristic line of a silicon oxide film deposited under a relatively high substrate temperature, that is, a substrate temperature of 400 ° C. as in the conventional case (characteristic line b indicated by a dotted line in the figure). And are shown respectively.
【００１６】この図４（ａ）において、結論的にはシリ
コン酸化膜を堆積した直後においては、本実施例のよう
に室温で堆積した場合に比して従来のように比較的高温
で堆積させた場合の方がＣ−Ｖ特性は良好であると言え
る。すなわち、このような酸化膜のＣ−Ｖ特性の評価基
準としては、Ｃ／Ｃoxの上側の飽和値Ｃａから、この飽
和値Ｃａと下側の飽和値Ｃｂとの差の約１／３程下がっ
た点ハ（特性線イの点）及び点ニ（特性線ロの点）にお
けるバイアス電圧が０ｖ又はその近傍となり且つ飽和値
Ｃａと飽和値Ｃｂとの間における特性線の傾きが大であ
る程よく、理想的には横軸（バイアス電圧側）に対して
垂直であることが望まれる（この様なＣ−Ｖ特性線の理
想的な形を以下「理想特性線」と言う。）。図４
（ａ），（ｂ）において特性線イと特性線ロとを上述の
観点から比較して見ると明らかに特性線ロが特性線イに
優っていると言うことができる。換言すれば、既述した
ように、比較的高い温度で堆積されたシリコン酸化膜の
ほうが、室温或いは比較的低い温度で堆積されたシリコ
ン酸化膜よりも、堆積直後におけるＣ−Ｖ特性で比較す
る限りにおいて良好であるということが言える。In FIG. 4A, it is concluded that immediately after the silicon oxide film is deposited, the silicon oxide film is deposited at a relatively high temperature as in the conventional case as compared with the case where the silicon oxide film is deposited at room temperature. It can be said that the C-V characteristics are better in the case of That is, as an evaluation criterion of the CV characteristic of such an oxide film, about 1/3 of the difference between the saturation value Ca on the upper side of C / C ox and the saturation value Cb on the lower side is used. The bias voltage at the point C (point of the characteristic line B) and the point D (point of the characteristic line B) which are lowered becomes 0 v or its vicinity, and the slope of the characteristic line between the saturation value Ca and the saturation value Cb is large. It is desirable that it is reasonably and ideally perpendicular to the horizontal axis (bias voltage side) (the ideal shape of such a CV characteristic line is hereinafter referred to as “ideal characteristic line”). Figure 4
It can be said that, when comparing the characteristic line a and the characteristic line b in (a) and (b) from the above viewpoint, the characteristic line b is clearly superior to the characteristic line a. In other words, as described above, the silicon oxide film deposited at a relatively high temperature is compared with the silicon oxide film deposited at room temperature or a relatively low temperature by the C-V characteristic immediately after the deposition. It can be said that it is good as far as it goes.
【００１７】次に、堆積されたシリコン酸化膜に熱処理
を施した後のＣ−Ｖ特性を本実施例のものと従来例とで
比較した特性線図が図４（ｂ）であり、以下、同図を参
照しつつその内容について説明する。同図において実線
で表された特性線ホは、本実施例のシリコン酸化膜の熱
処理後のＣ−Ｖ特性である。すなわち、室温で堆積され
たシリコン酸化膜を５００℃の窒素雰囲気中で１時間熱
処理を施した後におけるＣ−Ｖ特性を示したものであ
る。一方、点線で表された特性線ヘは、従来の方法によ
り堆積されたシリコン酸化膜、すなわち、４００℃の基
板温度の下で堆積されたシリコン酸化膜を５００℃の窒
素雰囲気中で１時間熱処理を施した後におけるＣ−Ｖ特
性を示したものである。Next, FIG. 4 (b) is a characteristic diagram comparing the CV characteristics of the deposited silicon oxide film after heat treatment with that of this embodiment and the conventional example. The contents will be described with reference to FIG. A characteristic line E shown by a solid line in the figure is the C-V characteristic after the heat treatment of the silicon oxide film of this embodiment. That is, it shows the CV characteristics after heat-treating the silicon oxide film deposited at room temperature in a nitrogen atmosphere at 500 ° C. for 1 hour. On the other hand, for the characteristic line indicated by the dotted line, the silicon oxide film deposited by the conventional method, that is, the silicon oxide film deposited under the substrate temperature of 400 ° C. is heat-treated in a nitrogen atmosphere at 500 ° C. for 1 hour. 3 shows the C-V characteristics after the treatment.
【００１８】この二つの特性線ホ、ヘを比較して見る
と、特性線ホの方が特性線ヘに比して明らかに図４
（ａ）の説明で述べたような理想特性線に近似している
と言える。すなわち、基板温度を室温にしてシリコン酸
化膜を堆積させた後に５００℃の窒素雰囲気中で１時間
熱処理を施して形成された本実施例のゲ−ト絶縁膜４の
方が、４００℃の基板温度の下で堆積されたシリコン酸
化膜を５００℃の窒素雰囲気中で１時間熱処理を施した
シリコン酸化膜よりも、良好な界面特性を有するものに
なるということが言える。具体的に界面準位密度Ｎssで
比較すると、上述した方法により形成されたシリコン酸
化膜では、Ｎss＝５×１０11ｃｍ-2ｅＶ-1程度であるの
に対し、本実施例の方法で形成されたシリコン酸化膜に
おいては、Ｎss＝５×１０10〜１×１０11ｃｍ-2ｅＶ-1
となり確実に界面特性の向上が得られている。Comparing these two characteristic lines E and F, the characteristic line E is clearly shown in FIG.
It can be said that it is close to the ideal characteristic line as described in the explanation of (a). That is, the gate insulating film 4 of this embodiment formed by depositing a silicon oxide film at room temperature and then performing heat treatment in a nitrogen atmosphere at 500 ° C. for 1 hour has a substrate temperature of 400 ° C. It can be said that the silicon oxide film deposited under the temperature has better interface characteristics than the silicon oxide film obtained by performing the heat treatment for 1 hour in the nitrogen atmosphere at 500 ° C. Specifically, in comparison with the interface state density N ss , in the silicon oxide film formed by the above method, N ss = 5 × 10 11 cm −2 eV −1 , whereas the method of the present embodiment. In the silicon oxide film formed by Nss = 5 × 10 10 to 1 × 10 11 cm -2 eV -1
Therefore, the interface characteristics are surely improved.
【００１９】尚、本実施例においては、シリコン酸化膜
を堆積させる際の基板温度を２３℃としたが、基板温度
はこの温度に限定されるものではなく、室温以上で約１
００℃以下であれば本実施例と略同一の効果を得ること
ができる。また、本実施例においては基板温度を室温と
してシリコン酸化膜を堆積し、その後５００℃の窒素雰
囲気に於いて熱処理を施したが、熱処理の温度としては
４００〜６００℃の間であればよく、本実施例の５００
℃に限定されるものではない。さらに、熱処理を行う雰
囲気も窒素雰囲気に限られる必要はなく、外に酸素又は
水素のいずれかであればよい。またさらに、本実施例に
おいては、ゲ−ト絶縁膜４を形成するものとしてシリコ
ン酸化膜を例に説明したが、これに限らずシリコン窒化
膜（ＳｉＮｘ）、シリコン酸窒化膜（ＳｉＯｘＮｙ）或
いはこれらを２種以上組み合わせたものであってもよ
い。Although the substrate temperature for depositing the silicon oxide film is 23 ° C. in the present embodiment, the substrate temperature is not limited to this temperature, and it is about 1 at room temperature or higher.
If the temperature is 00 ° C. or lower, substantially the same effect as this embodiment can be obtained. Further, in this embodiment, the silicon oxide film was deposited at the substrate temperature of room temperature and then heat-treated in a nitrogen atmosphere at 500 ° C., but the heat-treatment temperature may be between 400 and 600 ° C. 500 of this embodiment
The temperature is not limited to ° C. Furthermore, the atmosphere in which the heat treatment is performed need not be limited to the nitrogen atmosphere, and may be oxygen or hydrogen in addition to the atmosphere. Furthermore, in the present embodiment, the silicon oxide film was described as an example for forming the gate insulating film 4, but the present invention is not limited to this, and a silicon nitride film (SiNx), a silicon oxynitride film (SiOxNy), or these films is used. It may be a combination of two or more.
【００２０】[0020]
【発明の効果】以上、述べたように、本発明によれば、
ゲ−ト絶縁膜を基板温度１００℃以下でＥＣＲ−ＣＶＤ
法によって堆積させた後、４００乃至６００℃の熱処理
を施すようにすることによって、従来に比してゲ−ト絶
縁膜の界面準位を下げることができ、界面特性の優れた
ゲ−ト絶縁膜を得ることができる。また、かかるゲ−ト
絶縁膜の界面特性を向上させることにより、薄膜半導体
装置の諸特性の向上に寄与できるという効果を奏するも
のである。As described above, according to the present invention,
ECR-CVD of gate insulating film at a substrate temperature of 100 ° C or less
By performing a heat treatment at 400 to 600 ° C. after the deposition by the method, the interface state of the gate insulating film can be lowered as compared with the conventional case, and the gate insulating having excellent interface characteristics can be obtained. A membrane can be obtained. Further, by improving the interface characteristics of the gate insulating film, it is possible to contribute to the improvement of various characteristics of the thin film semiconductor device.
【図１】 本発明に係る薄膜半導体装置の製造方法によ
り製造された薄膜半導体装置の一例を示す縦断面図であ
る。FIG. 1 is a vertical cross-sectional view showing an example of a thin film semiconductor device manufactured by a method of manufacturing a thin film semiconductor device according to the present invention.
【図２】 本発明に係る薄膜半導体装置の製造方法を説
明するための主要な工程における縦断面図である。FIG. 2 is a vertical sectional view in a main step for explaining the method of manufacturing the thin film semiconductor device according to the invention.
【図３】 本発明に係る薄膜半導体装置の製造工程を説
明するための製造工程の主要部における縦断面図であ
る。FIG. 3 is a vertical cross-sectional view in the main part of the manufacturing process for explaining the manufacturing process of the thin film semiconductor device according to the invention.
【図４】 本発明に係る薄膜半導体装置の製造方法によ
って形成されるゲ−ト絶縁膜及び従来のゲ−ト絶縁膜の
Ｃ−Ｖ特性を示す特性線図である。FIG. 4 is a characteristic diagram showing CV characteristics of a gate insulating film formed by a method of manufacturing a thin film semiconductor device according to the present invention and a conventional gate insulating film.
【図５】 図４の特性線を得るための水銀プロ−ブ法の
概略を模式的に表した模式図である。5 is a schematic view schematically showing a mercury probe method for obtaining the characteristic line of FIG.
【図６】 従来の薄膜半導体装置の構成を示す縦断面図
である。FIG. 6 is a vertical cross-sectional view showing the configuration of a conventional thin film semiconductor device.
１…ガラス基板、 ２…半導体活性層、 ３ａ…ソ−ス
領域、 ３ｂ…ドレイン領域、 ４…ゲ−ト絶縁膜、
５…ゲ−ト電極DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 2 ... Semiconductor active layer, 3a ... Source region, 3b ... Drain region, 4 ... Gate insulating film,
5 ... Gate electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山田 高幸 神奈川県海老名市本郷2274番地 富士ゼ ロックス株式会社内 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Takayuki Yamada Fujize, 2274 Hongo, Ebina City, Kanagawa Prefecture Within Rocks Co., Ltd.
Claims (3)
れた半導体活性層をガラス基板上に配設し、この半導体
活性層を覆うようにゲ−ト絶縁膜を設け、このゲ−ト絶
縁膜上にゲ−ト電極を設け、さらに前記ゲート電極及び
前記ゲ−ト絶縁膜を覆う層間絶縁膜を形成してなる薄膜
半導体装置の製造方法において、前記 ゲ−ト絶縁膜の形成工程は、ガラス基板を１００℃
以下に保持しつつシリコンを含む絶縁部材を前記半導体
活性層を含む前記ガラス基板上に堆積させる第１の工程
と、前記堆積された絶縁部材に対し界面準位の減少させ
るため、窒素、酸素及び水素からなる群から選ばれた雰
囲気下で４００〜６００℃の熱処理を施す第２の工程
と、を具備することを特徴とする薄膜半導体装置の製造
方法。1. A semiconductor active layer having source and drain regions partially formed is provided on a glass substrate, and a gate insulating film is provided so as to cover the semiconductor active layer. A gate electrode is provided on the insulating film, and the gate electrode and
In a method of manufacturing a thin film semiconductor device, which comprises forming an interlayer insulating film covering the gate insulating film, in the step of forming the gate insulating film, a glass substrate is heated to 100 ° C.
The semiconductor insulating member containing silicon while maintaining below
A first step of depositing on the glass substrate including an active layer, and a step of reducing an interface state with respect to the deposited insulating member.
Therefore, the atmosphere selected from the group consisting of nitrogen, oxygen and hydrogen.
Method of manufacturing a thin film semiconductor device characterized by comprising a second step of under囲気 heat treatment of 400 to 600 ° C., a.
ＥＣＲプラズマＣＶＤ法により行うことを特徴とする請
求項１記載の薄膜半導体装置の製造方法。2. The deposition of the insulating member in the first step is
The method for manufacturing a thin film semiconductor device according to claim 1, wherein the method is performed by an ECR plasma CVD method.
及び水素からなる群から選ばれた２以上の気体の混合気
中で行うことを特徴とする請求項１記載の薄膜半導体装
置の製造方法。3. In the second step, the heat treatment is nitrogen and oxygen.
And a mixture of two or more gases selected from the group consisting of hydrogen
The method for manufacturing a thin film semiconductor device according to claim 1, wherein the method is performed in the inside .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03393093A JP3494304B2 (en) | 1993-02-01 | 1993-02-01 | Method for manufacturing thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03393093A JP3494304B2 (en) | 1993-02-01 | 1993-02-01 | Method for manufacturing thin film semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06232402A JPH06232402A (en) | 1994-08-19 |
| JP3494304B2 true JP3494304B2 (en) | 2004-02-09 |
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ID=12400239
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|---|---|---|---|
| JP03393093A Expired - Fee Related JP3494304B2 (en) | 1993-02-01 | 1993-02-01 | Method for manufacturing thin film semiconductor device |
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| DE69727033T2 (en) * | 1996-06-06 | 2004-11-11 | Seiko Epson Corp. | METHOD FOR PRODUCING A THIN-LAYER FIELD EFFECT TRANSISTOR, LIQUID CRYSTAL DISPLAY AND ELECTRONIC ARRANGEMENT PRODUCED BY IT |
| JP2985789B2 (en) * | 1996-08-30 | 1999-12-06 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP2002151526A (en) | 2000-09-04 | 2002-05-24 | Seiko Epson Corp | Method of manufacturing field-effect transistor and electronic device |
| JP2003197632A (en) * | 2001-12-25 | 2003-07-11 | Seiko Epson Corp | Manufacturing method of thin film transistor, semiconductor device and electric optical device |
| JP2004079735A (en) * | 2002-08-15 | 2004-03-11 | Nec Corp | Method of manufacturing thin film transistor |
| US7727904B2 (en) | 2005-09-16 | 2010-06-01 | Cree, Inc. | Methods of forming SiC MOSFETs with high inversion layer mobility |
| JP2007081414A (en) * | 2006-10-10 | 2007-03-29 | Seiko Epson Corp | Method of manufacturing semiconductor device |
| US9984894B2 (en) | 2011-08-03 | 2018-05-29 | Cree, Inc. | Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions |
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1993
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