JPH06507275A - 薄膜法を用いた多層成形プラスチックパッケージ - Google Patents

薄膜法を用いた多層成形プラスチックパッケージ

Info

Publication number
JPH06507275A
JPH06507275A JP5514358A JP51435893A JPH06507275A JP H06507275 A JPH06507275 A JP H06507275A JP 5514358 A JP5514358 A JP 5514358A JP 51435893 A JP51435893 A JP 51435893A JP H06507275 A JPH06507275 A JP H06507275A
Authority
JP
Japan
Prior art keywords
layer
conductive
lead frame
integrated circuit
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5514358A
Other languages
English (en)
Japanese (ja)
Inventor
バッタチャリヤ　ビデュト　ケー
マリク　デベンドラ
俊祐 坂
貴稔 瀧川
山中　正策
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Intel Corp
Original Assignee
Sumitomo Electric Industries Ltd
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd, Intel Corp filed Critical Sumitomo Electric Industries Ltd
Publication of JPH06507275A publication Critical patent/JPH06507275A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/401—Resistive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/601—Capacitive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/442—Shapes or dispositions of multiple leadframes in a single chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/451—Multilayered leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/464—Additional interconnections in combination with leadframes
    • H10W70/467—Multilayered additional interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/475—Capacitors in combination with leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Physical Vapour Deposition (AREA)
JP5514358A 1992-02-18 1993-02-18 薄膜法を用いた多層成形プラスチックパッケージ Pending JPH06507275A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US83728592A 1992-02-18 1992-02-18
US07/837.285 1992-02-18
PCT/US1993/001481 WO1993016492A1 (en) 1992-02-18 1993-02-18 Advance multilayer molded plastic package using mesic technology

Publications (1)

Publication Number Publication Date
JPH06507275A true JPH06507275A (ja) 1994-08-11

Family

ID=25274058

Family Applications (2)

Application Number Title Priority Date Filing Date
JP5051328A Pending JPH0629452A (ja) 1992-02-18 1993-02-18 集積回路パッケージ及びその製造方法
JP5514358A Pending JPH06507275A (ja) 1992-02-18 1993-02-18 薄膜法を用いた多層成形プラスチックパッケージ

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP5051328A Pending JPH0629452A (ja) 1992-02-18 1993-02-18 集積回路パッケージ及びその製造方法

Country Status (5)

Country Link
US (2) US5556807A (enExample)
EP (2) EP0603158A3 (enExample)
JP (2) JPH0629452A (enExample)
CA (2) CA2120464A1 (enExample)
WO (1) WO1993016492A1 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828126A (en) * 1992-06-17 1998-10-27 Vlsi Technology, Inc. Chip on board package with top and bottom terminals
GB2293918A (en) * 1994-10-06 1996-04-10 Ibm Electronic circuit packaging
JPH0951062A (ja) * 1995-08-07 1997-02-18 Mitsubishi Electric Corp 半導体チップの実装方法，半導体チップ，半導体チップの製造方法，ｔａｂテープ，フリップチップ実装方法，フリップチップ実装基板，マイクロ波装置の製造方法及びマイクロ波装置
US5773320A (en) * 1995-11-13 1998-06-30 Asea Brown Boveri Ag Method for producing a power semiconductor module
US5843808A (en) * 1996-01-11 1998-12-01 Asat, Limited Structure and method for automated assembly of a tab grid array package
US6043559A (en) 1996-09-09 2000-03-28 Intel Corporation Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses
JP3382482B2 (ja) * 1996-12-17 2003-03-04 新光電気工業株式会社 半導体パッケージ用回路基板の製造方法
KR100218368B1 (ko) * 1997-04-18 1999-09-01 구본준 리드프레임과 그를 이용한 반도체 패키지 및 그의 제조방법
US5923959A (en) * 1997-07-23 1999-07-13 Micron Technology, Inc. Ball grid array (BGA) encapsulation mold
US6472252B2 (en) * 1997-07-23 2002-10-29 Micron Technology, Inc. Methods for ball grid array (BGA) encapsulation mold
US6117382A (en) * 1998-02-05 2000-09-12 Micron Technology, Inc. Method for encasing array packages
US6300687B1 (en) 1998-06-26 2001-10-09 International Business Machines Corporation Micro-flex technology in semiconductor packages
US6064286A (en) * 1998-07-31 2000-05-16 The Whitaker Corporation Millimeter wave module with an interconnect from an interior cavity
US7020958B1 (en) * 1998-09-15 2006-04-04 Intel Corporation Methods forming an integrated circuit package with a split cavity wall
US6114098A (en) * 1998-09-17 2000-09-05 International Business Machines Corporation Method of filling an aperture in a substrate
US6414386B1 (en) * 2000-03-20 2002-07-02 International Business Machines Corporation Method to reduce number of wire-bond loop heights versus the total quantity of power and signal rings
DE10031843A1 (de) * 2000-06-30 2002-01-10 Alcatel Sa Elektrisches oder opto-elektrisches Bauelement mit einer Verpackung aus Kunststoff und Verfahren zur Variation der Impedanz einer Anschlussleitung eines solchen Bauelements
US7015072B2 (en) 2001-07-11 2006-03-21 Asat Limited Method of manufacturing an enhanced thermal dissipation integrated circuit package
US6734552B2 (en) 2001-07-11 2004-05-11 Asat Limited Enhanced thermal dissipation integrated circuit package
JP2003045978A (ja) * 2001-07-30 2003-02-14 Niigata Seimitsu Kk 半導体装置
US6790710B2 (en) * 2002-01-31 2004-09-14 Asat Limited Method of manufacturing an integrated circuit package
US20030057544A1 (en) * 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US20030059976A1 (en) * 2001-09-24 2003-03-27 Nathan Richard J. Integrated package and methods for making same
JP2003188882A (ja) * 2001-10-12 2003-07-04 Hiroyuki Shinoda 通信装置、通信デバイス、基板実装方法および触覚センサ
US20030153119A1 (en) * 2002-02-14 2003-08-14 Nathan Richard J. Integrated circuit package and method for fabrication
US6903458B1 (en) 2002-06-20 2005-06-07 Richard J. Nathan Embedded carrier for an integrated circuit chip
US6940154B2 (en) * 2002-06-24 2005-09-06 Asat Limited Integrated circuit package and method of manufacturing the integrated circuit package
US20040094826A1 (en) * 2002-09-20 2004-05-20 Yang Chin An Leadframe pakaging apparatus and packaging method thereof

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE278227C (enExample) *
JPS61230363A (ja) * 1985-04-04 1986-10-14 Fujitsu Ten Ltd 半導体集積装置
DE3626151C3 (de) * 1986-08-01 1995-06-14 Siemens Ag Spannungszuführungsanordnung für eine integrierte Halbleiterschaltung
US4891687A (en) * 1987-01-12 1990-01-02 Intel Corporation Multi-layer molded plastic IC package
US4835120A (en) * 1987-01-12 1989-05-30 Debendra Mallik Method of making a multilayer molded plastic IC package
JPH0719898B2 (ja) * 1987-01-30 1995-03-06 日本電気株式会社 光電気集積回路
JPS63258046A (ja) * 1987-04-15 1988-10-25 Toshiba Corp 半導体集積回路装置
US4987100A (en) * 1988-05-26 1991-01-22 International Business Machines Corporation Flexible carrier for an electronic device
DD278227A1 (de) * 1988-12-19 1990-04-25 Erfurt Mikroelektronik Integrierter stuetzkondensator
JPH0810744B2 (ja) * 1989-08-28 1996-01-31 三菱電機株式会社 半導体装置
US5025114A (en) * 1989-10-30 1991-06-18 Olin Corporation Multi-layer lead frames for integrated circuit packages
US5206188A (en) * 1990-01-31 1993-04-27 Ibiden Co., Ltd. Method of manufacturing a high lead count circuit board
JP2828318B2 (ja) * 1990-05-18 1998-11-25 新光電気工業株式会社 多層リードフレームの製造方法
DE59105080D1 (de) * 1990-05-28 1995-05-11 Siemens Ag IC-Gehäuse, bestehend aus drei beschichteten dielektrischen Platten.
JP2966067B2 (ja) * 1990-09-04 1999-10-25 新光電気工業株式会社 多層リードフレーム
FR2668651A1 (fr) * 1990-10-29 1992-04-30 Sgs Thomson Microelectronics Circuit integre a boitier moule comprenant un dispositif de reduction de l'impedance dynamique.

Also Published As

Publication number Publication date
US5556807A (en) 1996-09-17
CA2120464A1 (en) 1993-08-19
EP0603158A2 (en) 1994-06-22
EP0580855A1 (en) 1994-02-02
EP0580855A4 (enExample) 1994-03-16
EP0603158A3 (en) 1994-07-13
CA2108542A1 (en) 1993-08-19
JPH0629452A (ja) 1994-02-04
WO1993016492A1 (en) 1993-08-19
US5488257A (en) 1996-01-30

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