JPH0644674B2 - Method for manufacturing multilayer wiring board - Google Patents
Method for manufacturing multilayer wiring boardInfo
- Publication number
- JPH0644674B2 JPH0644674B2 JP61265480A JP26548086A JPH0644674B2 JP H0644674 B2 JPH0644674 B2 JP H0644674B2 JP 61265480 A JP61265480 A JP 61265480A JP 26548086 A JP26548086 A JP 26548086A JP H0644674 B2 JPH0644674 B2 JP H0644674B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- wiring board
- insulating paste
- multilayer wiring
- metal thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はコンピュータ等の電子機器に適用される多層配
線基板の製造方法に関するものである。The present invention relates to a method for manufacturing a multilayer wiring board applied to electronic equipment such as a computer.
従来より多層配線基板は、導体層を形成する場合、絶縁
層の表面に金属薄膜を形成し、前記金属薄膜の表面に感
光性のレジストを塗布し、露光及び現像により所望の導
体パターンを前記レジストから取り除き、この部分に金
属メツキにより導体を形成し、レジストを取り除いた
後、エツチングすることにより導体層を形成していた。Conventionally, in the case of forming a conductor layer in a multilayer wiring board, a metal thin film is formed on the surface of an insulating layer, a photosensitive resist is applied to the surface of the metal thin film, and a desired conductor pattern is formed by exposing and developing the resist. Then, a conductor was formed by metal plating on this portion, the resist was removed, and etching was performed to form a conductor layer.
従来の多層配線基板の製造方法は導体層を形成する際、
レジストの塗布、剥離という工程を経て形成されるの
で、工数がかかるという欠点があつた。The conventional method for manufacturing a multilayer wiring board is
Since it is formed through the steps of coating and peeling the resist, there is a drawback that it takes man-hours.
本発明は、前述した従来の問題に鑑みてなされたもので
あり、その目的は少ない工数で導体層を形成することが
できる多層配線基板の製造方法を提供することにある。The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a method for manufacturing a multilayer wiring board capable of forming a conductor layer with a small number of steps.
〔問題点を解決するための手段〕 本発明の多層配線基板の製造方法は、耐熱性絶縁基板の
表面に導体層を形成する際、前記導体層の下地の金属薄
膜の表面に感光性絶縁ペーストを塗布する工程と、この
感光性絶縁ペーストを露光，現像し所望の導体パターン
形成部位を開口させ前記開口部にメツキを施し導体パタ
ーンを形成する工程と、前記耐熱性絶縁基板を850℃〜1
000℃で焼成し、前記下地の金属薄膜を絶縁体とすると
ともに前記絶縁層の焼結を同時に行なう工程とを有して
いる。[Means for Solving Problems] In the method for manufacturing a multilayer wiring board of the present invention, when a conductor layer is formed on the surface of a heat-resistant insulating substrate, a photosensitive insulating paste is formed on the surface of a metal thin film underlying the conductor layer. And a step of exposing and developing this photosensitive insulating paste to open a desired conductor pattern forming portion to form a conductor pattern by plating the opening, and the heat-resistant insulating substrate at 850 ° C to 1
Firing at 000 ° C., making the underlying metal thin film an insulator, and simultaneously sintering the insulating layer.
本発明における多層配線基板の製造方法は、導体層を、
感光性絶縁ペーストおよび金属メツキにより形成するこ
とにより、その工程が短縮化される。The method for manufacturing a multilayer wiring board according to the present invention, a conductor layer,
By forming the photosensitive insulating paste and the metal plating, the process is shortened.
以下、図面を用いて本発明の実施例を詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図から第８図は本発明による多層配線基板の製造方
法の一実施例を示す工程の断面図である。まず、第１図
に示すように、耐熱性絶縁基板１の表面に金属薄膜２を
形成する。この金属薄膜２は例えばチタン(Ti)およびパ
ラジウム(pd)をスパツタリング法もしくは真空蒸着法に
より形成させる。この場合、チタン薄膜層の膜厚は500
〜2000Åであり、パラジウム薄膜層の膜厚は500〜2000
Åである。次に第３図に示すように前記金属薄膜２上の
感光性絶縁ペースト３を塗布し、乾燥させる。この感光
性絶縁ペースト３は重量比で６０％の無機粉末と４０％
の感光性ビヒクルとからなる。この無機粉末はガラス粉
末とアルミナ粉末との混合物で、感光性ビヒクルはメチ
ルメタアクリレートを主成分とする基本樹脂，光架橋
剤，光重合剤，熱重合禁止剤，消泡剤，染料およびエチ
ルカーピトールアセテートを主成分とする溶剤などから
なる。またこの感光性絶縁ペースト３の塗布方法は通常
のスクリーン印刷法で行ない、その厚さは約２０μｍで
ある。次に第４図に示すように前記感光性絶縁ペースト
３の上方に導体パターン形成部位に遮光部を有するガラ
スマスク４を配置し、このガラスマスク４によつて露光
を行なう。ここで露光された部分の絶縁ペーストは硬化
される。次に第５図に示すように絶縁ペースト３を１−
１−トリクロロエタンで現像することにより露光部は硬
化されているので、不溶化され、非露光部のみが溶解さ
れて開口部５が形成される。次に第６図に示すように絶
縁ペーストの開口部５に金属薄膜２を電極として金メツ
キを施して導体パターン６を形成する。この場合、金メ
ツキの厚さは約１０μｍである。次に第７図に示すよう
に導体パターン６及び絶縁ペースト３を850〜900℃で約
１０分間以上焼成することにより、金属薄膜２を酸化さ
せ、絶縁体２′とし、各々のパターンを電気的に独立さ
せると共に絶縁ペースト３を焼結体３′とする。この場
合、焼結後の絶縁ペーストの厚さは金メツキ厚と同じ約
10μｍ程度となる。次に第８図に示すように前記絶縁ペ
ースト焼結体３′及び導体パターン６の上に新たに絶縁
ペーストを塗布し、焼結させて絶縁層７を形成する。こ
こで金メツキの厚さを調整することにより、導体パター
ン６および絶縁層７を平坦化させることができる。1 to 8 are sectional views of steps showing an embodiment of a method for manufacturing a multilayer wiring board according to the present invention. First, as shown in FIG. 1, the metal thin film 2 is formed on the surface of the heat resistant insulating substrate 1. The metal thin film 2 is formed of, for example, titanium (Ti) and palladium (pd) by a sputtering method or a vacuum evaporation method. In this case, the thickness of the titanium thin film layer is 500
~ 2000Å, the thickness of the palladium thin film layer is 500 ~ 2000
It is Å. Next, as shown in FIG. 3, the photosensitive insulating paste 3 on the metal thin film 2 is applied and dried. This photosensitive insulating paste 3 comprises 60% by weight of inorganic powder and 40% by weight.
Consisting of a photosensitive vehicle. The inorganic powder is a mixture of glass powder and alumina powder, and the photosensitive vehicle is a basic resin containing methyl methacrylate as a main component, a photocrosslinking agent, a photopolymerization agent, a thermal polymerization inhibitor, an antifoaming agent, a dye and ethyl carbox It consists of a solvent whose main component is pitol acetate. The photosensitive insulating paste 3 is applied by an ordinary screen printing method and has a thickness of about 20 μm. Next, as shown in FIG. 4, a glass mask 4 having a light-shielding portion at a conductor pattern forming portion is arranged above the photosensitive insulating paste 3, and the glass mask 4 is used for exposure. The exposed portion of the insulating paste is cured. Next, as shown in FIG.
Since the exposed portion is hardened by developing with 1-trichloroethane, it is insolubilized and only the non-exposed portion is dissolved to form the opening 5. Next, as shown in FIG. 6, gold plating is applied to the openings 5 of the insulating paste using the metal thin film 2 as an electrode to form a conductor pattern 6. In this case, the thickness of the gold plating is about 10 μm. Then, as shown in FIG. 7, the conductor pattern 6 and the insulating paste 3 are fired at 850 to 900 ° C. for about 10 minutes or more to oxidize the metal thin film 2 to form an insulator 2 ′, and each pattern is electrically connected. And the insulating paste 3 is used as a sintered body 3 '. In this case, the thickness of the insulating paste after sintering is the same as the thickness of the gold plating.
It will be about 10 μm. Next, as shown in FIG. 8, a new insulating paste is applied on the insulating paste sintered body 3 ′ and the conductor pattern 6 and sintered to form an insulating layer 7. Here, the conductor pattern 6 and the insulating layer 7 can be flattened by adjusting the thickness of the gold plating.
なお、本実施例は導体一層の場合であるが、本方法は導
体が多層化されても各導体層で適用させることが可能で
あり、多層配線基板の製造に利用できることは言うまで
もない。It should be noted that although the present embodiment is a case of one conductor layer, it is needless to say that the present method can be applied to each conductor layer even when the conductor is multi-layered and can be used for manufacturing a multilayer wiring board.
以上説明したように本発明による多層配線基板の製造方
法は、導体層形成の際、レジストを使わず、絶縁ペース
トを使うことにより、従来、レジストを使つていた工程
を省くことができ、導体層の形成がより少ない工数で実
現できる効果がある。As described above, in the method for manufacturing a multilayer wiring board according to the present invention, when a conductor layer is formed, a resist is not used, and an insulating paste is used. Therefore, it is possible to omit the step that conventionally uses a resist. There is an effect that the formation of layers can be realized with a smaller number of steps.
第１図ないし第８図は本発明による多層配線基板の製造
方法の一実施例を示す工程の断面図である。 １……耐熱性絶縁基板、２……金属薄膜、３……感光性
絶縁ペースト、４……ガラスマスク、５……開口部、６
……導体パターン、７……絶縁層。1 to 8 are sectional views of steps showing an embodiment of a method for manufacturing a multilayer wiring board according to the present invention. 1 ... Heat-resistant insulating substrate, 2 ... Metal thin film, 3 ... Photosensitive insulating paste, 4 ... Glass mask, 5 ... Opening, 6
...... Conductor pattern, 7 …… Insulation layer.
Claims (1)
る工程と、前記金属薄膜の表面に感光性絶縁ペーストを
塗布し乾燥させる工程と、前記感光性絶縁ペーストを露
光および現像により所望する部分を取り除き開口部を形
成する工程と、前記金属薄膜を電極とし前記開口部に金
属メッキにより導体層を形成する工程と、前記耐熱性基
板を850℃〜1000℃で焼成し前記絶縁ペースト下の金属
薄膜部を酸化させ絶縁体とするとともに前記絶縁ペース
トを焼結させ絶縁層とする工程とを含むことを特徴とす
る多層配線基板の製造方法。1. A step of forming a metal thin film on the surface of a heat-resistant insulating substrate, a step of applying a photosensitive insulating paste on the surface of the metal thin film and drying, and a step of exposing the photosensitive insulating paste to light and developing it. A step of removing a portion to form an opening, a step of forming a conductor layer by metal plating in the opening using the metal thin film as an electrode, and baking the heat-resistant substrate at 850 ° C. to 1000 ° C. to form a layer under the insulating paste. And a step of oxidizing the metal thin film portion to an insulator and sintering the insulating paste to form an insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61265480A JPH0644674B2 (en) | 1986-11-10 | 1986-11-10 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61265480A JPH0644674B2 (en) | 1986-11-10 | 1986-11-10 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63120499A JPS63120499A (en) | 1988-05-24 |
| JPH0644674B2 true JPH0644674B2 (en) | 1994-06-08 |
Family
ID=17417759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61265480A Expired - Lifetime JPH0644674B2 (en) | 1986-11-10 | 1986-11-10 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0644674B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6122692A (en) * | 1984-07-10 | 1986-01-31 | 日本電気株式会社 | Multilayer circuit board and method of producing same |
-
1986
- 1986-11-10 JP JP61265480A patent/JPH0644674B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63120499A (en) | 1988-05-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |