JPS63120499A - Manufacture of multilayer interconnection board - Google Patents
Manufacture of multilayer interconnection boardInfo
- Publication number
- JPS63120499A JPS63120499A JP26548086A JP26548086A JPS63120499A JP S63120499 A JPS63120499 A JP S63120499A JP 26548086 A JP26548086 A JP 26548086A JP 26548086 A JP26548086 A JP 26548086A JP S63120499 A JPS63120499 A JP S63120499A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- paste
- metal thin
- insulating
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004020 conductor Substances 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000010409 thin film Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 11
- 238000007747 plating Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 3
- 238000005245 sintering Methods 0.000 claims description 3
- 238000010304 firing Methods 0.000 claims description 2
- 238000001035 drying Methods 0.000 claims 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 239000011521 glass Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- SCYULBFZEHDVBN-UHFFFAOYSA-N 1,1-Dichloroethane Chemical compound CC(Cl)Cl SCYULBFZEHDVBN-UHFFFAOYSA-N 0.000 description 1
- VVQNEPGJFQJSBK-UHFFFAOYSA-N Methyl methacrylate Chemical group COC(=O)C(C)=C VVQNEPGJFQJSBK-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000002518 antifoaming agent Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- XXJWXESWEXIICW-UHFFFAOYSA-N diethylene glycol monoethyl ether Chemical group CCOCCOCCO XXJWXESWEXIICW-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000012719 thermal polymerization Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はコンピュータ等の電子機器に適用される多層配
線基板の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a multilayer wiring board applied to electronic equipment such as computers.
従来よシ多層配線基板は、導体層を形成する場合、絶縁
層の表面に金属薄膜を形成し、前記金属薄膜の表面に感
光性のレジストを塗布し、露光及び現像により所望の導
体パターンを前記レジストから数カ除き、この部分に金
属メッキにより導体を形成し、レジストを取り除いた後
、エツチングすることにより導体層を形成していた。Conventionally, when forming a conductor layer in a multilayer wiring board, a metal thin film is formed on the surface of an insulating layer, a photosensitive resist is applied to the surface of the metal thin film, and a desired conductor pattern is formed by exposure and development. A conductor layer was formed by removing a few parts from the resist, forming a conductor on these parts by metal plating, removing the resist, and etching.
従来の多層配線基板の製造方法は導体層を形成する際、
レジストの塗布、剥離という工程を経て形成されるので
、工数がかかるという欠点があった。In the conventional manufacturing method of multilayer wiring board, when forming the conductor layer,
Since it is formed through the steps of applying and peeling off a resist, it has the disadvantage of requiring a lot of man-hours.
本発明は、前述した従来の問題に鑑みてなされたもので
あシ、その目的は少ない工数で導体層を形成することが
できる多層配線基板の製造方法を提供することにある。The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a method for manufacturing a multilayer wiring board that can form a conductor layer with fewer man-hours.
本発明の多層配線基板の製造方法は、耐熱性絶縁基板の
表面に導体層を形成する際、前記導体層の下地の金属薄
膜の表面に感光性絶縁ペーストを塗布する工程と、この
感光性絶縁ペーストを露光。The method for manufacturing a multilayer wiring board of the present invention includes, when forming a conductor layer on the surface of a heat-resistant insulating substrate, a step of applying a photosensitive insulating paste to the surface of a metal thin film underlying the conductor layer, and a step of applying the photosensitive insulating paste Expose the paste.
現像し所望の導体パターン形成部位を開口させ前記開口
部にメッキを施し導体パターンを形成する工程と、前記
耐熱性絶縁基板ヲ８５０℃〜１０００℃で焼成し、前記
下地の金属薄膜を絶縁体とするとともに前記絶縁層の焼
結を同時に行なう工程とを有している。A step of developing and opening a desired conductor pattern forming area and plating the opening to form a conductor pattern, and baking the heat-resistant insulating substrate at 850°C to 1000°C to convert the underlying metal thin film into an insulator. and simultaneously sintering the insulating layer.
本発明における多層配線基板の製造方法は、導体層を、
感光性絶縁ペーストおよび金属メッキにより形成するこ
とにより、その工程が短縮化される。In the method for manufacturing a multilayer wiring board in the present invention, the conductor layer is
Forming with photosensitive insulating paste and metal plating shortens the process.
以下、図面を用いて本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図から第８図は本発明による多層配線基板の製造方
法の一実施例を示す工程の断面図である。1 to 8 are cross-sectional views showing steps of an embodiment of the method for manufacturing a multilayer wiring board according to the present invention.
まず、第１図に示すように、耐熱性絶縁基板１の表面に
金属薄膜２を形成する。この金属薄膜２は例えばチタン
（Ｔｉ）およびパラジウム（ｐｄ）をスパッタリング法
もしくは真空蒸着法により形成させる。この場合、チタ
ン薄膜層の膜厚は５００〜２０００ 、ｌであシ、パラ
ジウム薄膜層の膜厚は５００〜２０００ Ｘである。次
に第３図に示すように前記金属薄膜２上に感光性絶縁ペ
ースト３を塗布し、乾燥させる。この感光性絶縁ペース
ト３は重量比で６０％の無機粉末と４０％の感光性ビヒ
クルとからなる。この無機粉末はガラス粉末とアルミナ
粉末との混合物で、感光性ビヒクルはメチルメタアクリ
レ−）１主成分とする基本樹脂、光架橋剤。First, as shown in FIG. 1, a metal thin film 2 is formed on the surface of a heat-resistant insulating substrate 1. This metal thin film 2 is formed of titanium (Ti) and palladium (PD), for example, by sputtering or vacuum evaporation. In this case, the thickness of the titanium thin film layer is 500 to 2000×, and the thickness of the palladium thin film layer is 500 to 2000×. Next, as shown in FIG. 3, a photosensitive insulating paste 3 is applied onto the metal thin film 2 and dried. This photosensitive insulating paste 3 consists of 60% inorganic powder and 40% photosensitive vehicle by weight. This inorganic powder is a mixture of glass powder and alumina powder, and the photosensitive vehicle is methyl methacrylate (1), a basic resin as the main component, and a photocrosslinking agent.
光重合剤、熱重合禁止剤、消泡剤、染料およびエチルカ
ービトールアセテートを主成分とする溶剤などからなる
。またこの感光性絶縁ペースト３の塗布方法は通常のス
クリーン印刷法で行ない、その厚さは約２０μｍである
。次に第４図に示すように前記感光性絶縁ペースト３の
上方に導体パターン形成部位に遮光部を有するガラスマ
スク４を配置し、このガラスマスク４によって露光を行
なう。It consists of a photopolymerization agent, a thermal polymerization inhibitor, an antifoaming agent, a dye, and a solvent whose main component is ethyl carbitol acetate. The photosensitive insulating paste 3 is applied by a conventional screen printing method, and its thickness is approximately 20 μm. Next, as shown in FIG. 4, a glass mask 4 having a light-shielding portion at the conductive pattern forming area is placed above the photosensitive insulating paste 3, and exposure is performed using this glass mask 4.
ここで露光された部分の絶縁ペーストは硬化される。次
に第５図に示すように絶縁ペースト３を１−１−１）リ
クロロエタンで現像することにより露光部は硬化されて
いるので、不溶化され、非露光部のみが溶解されて開口
部５が形成される。次に第６図に示すように絶縁ペース
トの開口部５に金属薄膜２ｆ、電極として金メッキを施
して導体パターン６を形成する。この場合、金メッキの
厚さは約１０μｍでおる。次に第７図に示すように導体
パターン６及び絶縁ペースト３’ｅ８５０〜９００ ℃
で約１０分間以上焼成することによｐ１金属薄膜２を酸
化させ、絶縁体２′とし、各々のパターンを電気的に独
立させると共に絶縁ペースト３を焼結体３′とする。こ
の場合、焼結後の絶縁ペーストの厚さは金メッキ厚と同
じ約１０μｍ程度となる。次に第８図に示すように前記
絶縁ペースト焼結体３′及び導体パターン６の上に新た
に絶縁ペーストを塗布し、焼結させて絶縁層７を形成す
る。ここで金メッキの厚さを調整することにより、導体
パターン６および絶縁層７を平坦化させることができる
。At this point, the exposed portions of the insulation paste are cured. Next, as shown in FIG. 5, the insulating paste 3 is developed with 1-1-1) dichloroethane, so that the exposed area is hardened and thus insolubilized, and only the non-exposed area is dissolved and the opening 5 is formed. It is formed. Next, as shown in FIG. 6, a metal thin film 2f is applied to the opening 5 of the insulating paste and gold plating is applied as an electrode to form a conductive pattern 6. In this case, the thickness of the gold plating is approximately 10 μm. Next, as shown in FIG.
By firing for about 10 minutes or more, the p1 metal thin film 2 is oxidized to form an insulator 2', each pattern is made electrically independent, and the insulating paste 3 is formed into a sintered body 3'. In this case, the thickness of the insulating paste after sintering is about 10 μm, which is the same as the thickness of the gold plating. Next, as shown in FIG. 8, an insulating paste is newly applied on the insulating paste sintered body 3' and the conductive pattern 6 and sintered to form an insulating layer 7. By adjusting the thickness of the gold plating, the conductive pattern 6 and the insulating layer 7 can be flattened.
なお、本実施例は導体−層の場合であるが、本方法は導
体が多層化されても各導体層で適用させることが可能で
あシ、多層配線基板の製造に利用できることは言うまで
もない。Although this embodiment deals with conductor layers, it goes without saying that this method can be applied to each conductor layer even if the conductor is multilayered, and can be used to manufacture a multilayer wiring board.
以上説明したように本発明による多層配線基板の製造方
法は、導体層形成の際、レジストを使わず、絶縁ペース
トを使うことにより、従来、レジストを使っていた工程
を省くことができ、導体層の形成がよシ少ない工数で実
現できる効果がある。As explained above, the method for manufacturing a multilayer wiring board according to the present invention uses an insulating paste instead of a resist when forming a conductor layer, thereby omitting the process that conventionally used a resist. This has the effect that the formation of the material can be achieved with less man-hours.
第１図ないし第８図は本発明による多層配線基板の製造
方法の一実施例を示す工程の断面図である。
１・・・・耐熱性絶縁基板、２・・・・金属薄膜、３・
・・・感光性絶縁ペースト、４・・・・ガラスマスク、
５・・・・開口部、６・―・・導体パターン、Ｔ・・・
・絶縁層。1 to 8 are cross-sectional views showing steps of an embodiment of the method for manufacturing a multilayer wiring board according to the present invention. 1... Heat-resistant insulating substrate, 2... Metal thin film, 3...
...Photosensitive insulation paste, 4...Glass mask,
5...Opening, 6...Conductor pattern, T...
・Insulating layer.
Claims (1)
された絶縁層の表面に金属薄膜を形成する工程と、前記
金属薄膜の表面に感光性絶縁ペーストを塗布し乾燥させ
る工程と、前記感光性絶縁ペーストを露光および現像に
より所望する部分を取り除き開口部を形成する工程と、
前記金属薄膜を電極とし前記開口部に金属メッキにより
導体層を形成する工程と、前記耐熱性基板を８５０℃〜
１０００℃で焼成し前記絶縁ペースト下の金属薄膜部を
酸化させ絶縁体とするとともに前記絶縁ペーストを焼結
させ絶縁層とする工程とを含むことを特徴とする多層配
線基板の製造方法。a step of forming a metal thin film on the surface of a heat-resistant insulating substrate or an insulating layer formed on the heat-resistant insulating substrate; a step of applying and drying a photosensitive insulating paste on the surface of the metal thin film; a step of removing a desired portion of the paste by exposing and developing the paste to form an opening;
forming a conductor layer in the opening by metal plating using the metal thin film as an electrode;
A method for manufacturing a multilayer wiring board, comprising the steps of firing at 1000° C. to oxidize the metal thin film under the insulating paste to form an insulator, and sintering the insulating paste to form an insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61265480A JPH0644674B2 (en) | 1986-11-10 | 1986-11-10 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61265480A JPH0644674B2 (en) | 1986-11-10 | 1986-11-10 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63120499A true JPS63120499A (en) | 1988-05-24 |
| JPH0644674B2 JPH0644674B2 (en) | 1994-06-08 |
Family
ID=17417759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61265480A Expired - Lifetime JPH0644674B2 (en) | 1986-11-10 | 1986-11-10 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0644674B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6122692A (en) * | 1984-07-10 | 1986-01-31 | 日本電気株式会社 | Multilayer circuit board and method of producing same |
-
1986
- 1986-11-10 JP JP61265480A patent/JPH0644674B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6122692A (en) * | 1984-07-10 | 1986-01-31 | 日本電気株式会社 | Multilayer circuit board and method of producing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0644674B2 (en) | 1994-06-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |