JP2000013004A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JP2000013004A
JP2000013004A JP10173670A JP17367098A JP2000013004A JP 2000013004 A JP2000013004 A JP 2000013004A JP 10173670 A JP10173670 A JP 10173670A JP 17367098 A JP17367098 A JP 17367098A JP 2000013004 A JP2000013004 A JP 2000013004A
Authority
JP
Japan
Prior art keywords
solder resist
wiring board
printed wiring
solder
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10173670A
Other languages
Japanese (ja)
Inventor
Kiminori Ishidou
仁則 石堂
Shinichi Oba
進一 大場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP10173670A priority Critical patent/JP2000013004A/en
Publication of JP2000013004A publication Critical patent/JP2000013004A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To form a stable square solder dam between part mounting pads with a narrow gap. SOLUTION: An insulating substrate 1 where a part mounting pad 2, is coated with at least two kinds of photosolder resists 3 and 4 of different development capacities which are set to touch for exposure and development. Two or more kinds of solder resists 3 and 4 of different development speeds are coated in the order starting with higher development speed, so the development is faster as lower layers, approach with its relative development time shorter than when only one kind of solder resist is used.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、印刷配線板の製造
方法に関し、特に、相互間隔の狭小な部品実装用パッド
間に矩形なソルダーダムを形成する方法に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for forming a rectangular solder dam between component mounting pads having a small interval.

【0002】[0002]

【従来の技術】印刷配線板の製造方法には、相互間隔の
狭小な部品実装用パッド間に矩形なソルダーダムを形成
する方法がある。
2. Description of the Related Art As a method of manufacturing a printed wiring board, there is a method of forming a rectangular solder dam between component mounting pads having a small space between each other.

【0003】アンダーカットを抑制し、矩形なソルダー
ダムを形成する印刷配線板の製造方法が特開昭63−2
00594号公報に開示されている。特開昭63−20
0594号公報に開示された製造方法は、内部硬化性の
異なる二層の光硬化性ソルダーレジストを用いた方法で
あり、その製造工程を図2に示す。
A method of manufacturing a printed wiring board which suppresses undercut and forms a rectangular solder dam is disclosed in Japanese Patent Application Laid-Open No. 63-2.
No. 00594. JP-A-63-20
The production method disclosed in Japanese Patent No. 0594 is a method using two layers of photocurable solder resists having different internal curability, and the production process is shown in FIG.

【0004】特開昭63−200594号公報に開示さ
れた製造方法は、まず図2(a)に示されるように、絶
縁基板1に回路パターン7が形成され、次に図2(b)
に示されるように、内部光硬化性のソルダーレジスト8
が基板全面にスクリーン印刷によって15〜25μmの
膜厚に塗布され、70〜90℃で5〜10分間の乾燥が
行なわれる。
According to the manufacturing method disclosed in Japanese Patent Application Laid-Open No. 63-200574, a circuit pattern 7 is first formed on an insulating substrate 1 as shown in FIG.
As shown in the figure, the internal photocurable solder resist 8
Is applied to the entire surface of the substrate by screen printing to a thickness of 15 to 25 μm, and drying is performed at 70 to 90 ° C. for 5 to 10 minutes.

【0005】次に図2(c)に示されるように、内部光
硬化性のソルダーレジスト8上に表面光硬化性のソルダ
ーレジスト9がスクリーン印刷によって15〜25μm
の膜厚に塗布され、70〜90℃で15〜30分間の乾
燥が行なわれる。
Next, as shown in FIG. 2C, a surface light-curable solder resist 9 is formed on the internal light-curable solder resist 8 by screen printing to a thickness of 15 to 25 μm.
And dried at 70 to 90 ° C. for 15 to 30 minutes.

【0006】次に図2(d)に示されるように、マスク
フィルム5を介して200〜500mJ/cm2の紫外
線露光を照射し、1.1.1.トリクロロエタン等の溶
剤によって現像が行なわれ、所望なソルダレジストパタ
ーン6が得られる(図2(e))。
[0006] Next, as shown in FIG. 2 (d), 200-500 mJ / cm 2 ultraviolet light exposure is applied through the mask film 5 to obtain 1.1.1.1. Development is performed with a solvent such as trichloroethane, and a desired solder resist pattern 6 is obtained (FIG. 2E).

【0007】図2(e)に示されるソルダレジストパタ
ーン6は、上層に表面光硬化性、下層に内部光硬化性を
有しているため、ソルダーレジストの表面諸特性を損ね
ることなく、そのアンダーカットを抑制することが可能
となる。
The solder resist pattern 6 shown in FIG. 2 (e) has a surface photo-curing property in the upper layer and an internal photo-curing property in the lower layer. Can be suppressed.

【0008】[0008]

【発明が解決しようとする課題】ところで、印刷配線板
の部品実装用パッド間隙には、はんだ付け時のはんだブ
リッジやはんだボールの付着を防止するために、ソルダ
ーレジストを形成する必要があり、近年の電子機器の小
形化・高性能化に伴い、パッド間隙が年々狭小化してい
る。
By the way, it is necessary to form a solder resist in the gap between the component mounting pads of the printed wiring board in order to prevent the adhesion of solder bridges and solder balls during soldering. As electronic devices become smaller and have higher performance, pad gaps are becoming smaller year by year.

【0009】しかしながら、図2に示される硬化性の異
なるソルダーレジストを用いた製造方法では、微細な配
線パターン7と微細なソルダレジストパターン6を形成
することが困難を極めている。
However, it is extremely difficult to form a fine wiring pattern 7 and a fine solder resist pattern 6 in the manufacturing method using solder resists having different curability as shown in FIG.

【0010】本発明の目的は、狭小な間隙のパッド間に
安定した密着性に優れた矩形ソルダーレジストを形成す
る印刷配線板の製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a printed wiring board for forming a rectangular solder resist having stable and excellent adhesion between pads having a small gap.

【0011】[0011]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る印刷配線板の製造方法は、基板上の狭
小なスペース内にソルダーレジストをパターニングして
形成する印刷配線板の製造方法であって、現像速度の異
なる2以上のソルダーレジストを基板全面に塗布し、前
記ソルダーレジストに指触乾燥を行ない、露光,現像工
程を経て、基板上の狭小なスペース内にソルダーレジス
トをパターニングして形成するものである。
In order to achieve the above object, a method of manufacturing a printed wiring board according to the present invention is directed to a method of manufacturing a printed wiring board in which a solder resist is patterned and formed in a narrow space on a substrate. Then, two or more solder resists having different development speeds are applied to the entire surface of the substrate, and the solder resist is dried by touching, exposed and developed, and then patterned in a narrow space on the substrate. It is formed.

【0012】また現像速度の異なる2以上のソルダーレ
ジストは、上層より下層のものの現像速度を速く設定す
るものである。
The two or more solder resists having different developing speeds are set so that the developing speed of the lower layer is higher than that of the upper layer.

【0013】また現像速度の異なる2以上のソルダーレ
ジストは、酸価の違いによりアルカリ性現像液に対する
現像速度を異ならせるものである。
Two or more solder resists having different developing speeds have different developing speeds with respect to an alkaline developing solution due to a difference in acid value.

【0014】[0014]

【発明の実施の形態】以下、本発明の実施の形態を図に
より説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

【0015】図1において本発明に係る印刷配線板の製
造方法は、基板上の狭小なスペース内にソルダーレジス
トをパターニングして形成する印刷配線板の製造方法で
あり、基本的構成として、現像速度の異なる2以上のソ
ルダーレジスト3,4を基板1の全面に塗布し、ソルダ
ーレジスト3,4に指触乾燥を行ない、露光,現像工程
を経て、基板1上の狭小なスペース内にソルダーレジス
ト6をパターニングして形成するものである。
Referring to FIG. 1, the method for manufacturing a printed wiring board according to the present invention is a method for manufacturing a printed wiring board by patterning a solder resist in a narrow space on a substrate. Are applied to the entire surface of the substrate 1, and the solder resists 3 and 4 are dried by touching. After exposure and development processes, the solder resist 6 is placed in a narrow space on the substrate 1. Is formed by patterning.

【0016】また現像速度の異なる2以上のソルダーレ
ジスト3,4は、上層より下層のものの現像速度を速く
設定しており、現像速度の異なる2以上のソルダーレジ
スト3,4は、酸価の違いによりアルカリ性現像液に対
する現像速度を異ならせている。
The two or more solder resists 3 and 4 having different developing speeds are set so that the lower layer has a higher developing speed than the upper layer. The two or more solder resists 3 and 4 having different developing speeds have different acid values. The developing speed for an alkaline developing solution is made different.

【0017】次に、本発明に係る印刷配線板の製造方法
の具体例を実施形態として詳細に説明する。
Next, a specific example of the method for manufacturing a printed wiring board according to the present invention will be described in detail as an embodiment.

【0018】図1は、本発明の一実施形態に係る印刷配
線板の製造方法を工程順に示す断面図である。
FIG. 1 is a sectional view showing a method of manufacturing a printed wiring board according to an embodiment of the present invention in the order of steps.

【0019】図1(a)に示すように、ガラスエポキ
シ、またはガラスポリイミドで形成された有機絶縁材料
の絶縁基板1上に、部品実装用パッド2を形成する。
As shown in FIG. 1A, a component mounting pad 2 is formed on an insulating substrate 1 made of an organic insulating material made of glass epoxy or glass polyimide.

【0020】次に、図1(b)に示すように、第1のフ
ォトソルダーレジスト3を絶縁基板1の全面に10〜2
0ミクロンの膜厚にスクリーン印刷またはカーテンコー
ト法等により全面塗布する。
Next, as shown in FIG. 1B, a first photo solder resist 3 is applied to the entire surface of the insulating substrate 1 for 10 to 2 hours.
The entire surface is applied to a film thickness of 0 μm by screen printing or curtain coating.

【0021】図1(b)に示す第1のフォトソルダーレ
ジスト3はアルカリ性現像液に対する現像速度を高める
ため、ジペンタエリスリトール誘導体に5.6モルのア
クリル酸を付加させ、次に0.4モルの無水フタル酸ま
たは無水マレイン酸を反応させて得られる、酸価が60
〜100(mg・KOH/g)に調整されたアクリレー
ト樹脂を含むフォトソルダーレジストを用いる。
The first photo solder resist 3 shown in FIG. 1 (b) is prepared by adding 5.6 mol of acrylic acid to a dipentaerythritol derivative and then adding 0.4 mol of Of phthalic anhydride or maleic anhydride, the acid value of which is 60
A photo solder resist containing an acrylate resin adjusted to 100100 (mg · KOH / g) is used.

【0022】次に、絶縁基板1の全面に塗布した第1の
フォトソルダーレジスト3に対して70〜90℃で15
〜30分間の指触乾燥を行う。
Next, the first photo solder resist 3 applied on the entire surface of the insulating substrate 1 is heated at 70 to 90 ° C. for 15 minutes.
Dry to touch for ~ 30 minutes.

【0023】引き続いて、図1(c)に示すように、指
触乾燥した第1のフォトソルダーレジスト3上に第2の
フォトソルダーレジスト4を10〜20ミクロンの膜厚
にスクリーン印刷法またはカーテンコート法等により塗
布する。
Subsequently, as shown in FIG. 1C, a second photo solder resist 4 is screen-printed or curtain-coated on the first photo solder resist 3 having a thickness of 10 to 20 μm on the touch-dried first photo solder resist 3. It is applied by a coating method or the like.

【0024】第2のフォトソルダーレジスト4は、第1
のフォトソルダーレジスト3よりも現像速度を高めるた
め、ジペンタエリスリトール誘導体に5.6モルのメタ
アクリル酸を付加させ、次に、0.4モルの無水フタル
酸または無水マレイン酸を反応させて得られる、酸価が
30〜50(mg・KOH/g)に調整されたアクリレ
ート樹脂を含むフォトソルダーレジストを用いる。
The second photo solder resist 4 has a first
5.6 mol of methacrylic acid is added to the dipentaerythritol derivative and then reacted with 0.4 mol of phthalic anhydride or maleic anhydride in order to increase the development speed more than that of Photo Solder Resist 3 A photo solder resist containing an acrylate resin whose acid value is adjusted to 30 to 50 (mg · KOH / g) is used.

【0025】次に、第1のフォトソルダーレジスト3上
に塗布した第2のフォトソルダーレジスト4に対して7
0〜90℃で15〜30分間の指触乾燥を行う。
Next, the second photo solder resist 4 applied on the first photo solder resist 3
Dry to the touch at 0-90 ° C for 15-30 minutes.

【0026】以上の2工程を経て、絶縁基板1の部品実
装用パッド2,2間に現像速度の異なる2層からなるフ
ォトソルダーレジスト3,4を形成する。
Through the above two steps, two layers of photo solder resists 3 and 4 having different developing speeds are formed between the component mounting pads 2 and 2 of the insulating substrate 1.

【0027】2層のフォトソルダーレジスト3,4のう
ち、下層のフォトソルダーレジスト4は、上層のフォト
ソルダーレジスト3より現像速度が速く、上層より下層
の現像速度を速く設定している。
Of the two layers of the photo solder resists 3 and 4, the lower layer of the solder resist 4 has a higher developing speed than the upper layer of the solder resist 3, and the lower layer has a higher developing speed than the upper layer.

【0028】ここで、酸価の違いにより、第1のフォト
ソルダーレジスト3は、第2のフォトソレダーレジスト
4より1.5〜2倍程度に現像性を高めることが可能と
なっている。
Here, the developability of the first photo solder resist 3 can be improved to about 1.5 to 2 times that of the second photo solder resist 4 due to the difference in acid value.

【0029】次に、図1(d)に示すように、マイラー
フィルム5を介して積算露光量50〜200(mJ/c
2)のUV光4をフォトソルダーレジスト3,4に対
して照射する。
Next, as shown in FIG. 1D, the integrated exposure amount is 50 to 200 (mJ / c) through the mylar film 5.
m 2 ) UV light 4 is applied to the photo solder resists 3 and 4.

【0030】次に図1(e)に示すように、1%炭酸ナ
トリウム水溶液を用い、液温30℃、スプレー圧2〜3
(kg/cm2)、処理時間30秒〜90秒で現像を行
う。
Next, as shown in FIG. 1E, a 1% aqueous solution of sodium carbonate was used at a liquid temperature of 30 ° C. and a spray pressure of 2-3.
(Kg / cm 2 ), and development is performed for a processing time of 30 seconds to 90 seconds.

【0031】ハレーションや裏露光を発生させることな
く、矩形で密着性に優れたソルダーレジストパターン6
を隣接する部品実装用パッド2,2間に形成する。
A solder resist pattern 6 having a rectangular shape and excellent adhesion without causing halation or back exposure.
Is formed between adjacent component mounting pads 2.

【0032】[0032]

【発明の効果】以上説明したように本発明によれば、パ
ッド間隙の狭小な部品実装用パッドの間隙に、密着性の
良好なソルダーダムを安定して形成できる。
As described above, according to the present invention, a solder dam with good adhesion can be stably formed in the gap between the component mounting pads having a small pad gap.

【0033】その理由は、現像速度の異なる2種類以上
のソルダーレジストを、現像速度の高い順序で塗布され
ているため、下層に進む程に現像速度は速く、その相対
現像時間は、ソルダーレジストを1種類だけ用いた場合
に比べて短くすることができる。即ち、上層のソルダー
レジストがアンダーカットすることなく、下層方向に現
像が進行し、矩形で密着性に優れたソルダーダムを形成
することができる。
The reason is that, since two or more types of solder resists having different developing speeds are applied in the order of higher developing speed, the developing speed becomes higher as going to the lower layer, and the relative developing time becomes longer. It can be shorter than when only one type is used. That is, development proceeds in the lower layer direction without undercutting the upper layer solder resist, so that a rectangular solder dam having excellent adhesion can be formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態に係る印刷配線板の製造方
法を製造工程順に示す断面図である。
FIG. 1 is a sectional view illustrating a method for manufacturing a printed wiring board according to an embodiment of the present invention in the order of manufacturing steps.

【図2】従来例に係る印刷配線板の製造方法を製造工程
順に示す断面図である。
FIG. 2 is a cross-sectional view showing a method of manufacturing a printed wiring board according to a conventional example in the order of manufacturing steps.

【符号の説明】[Explanation of symbols]

1 絶縁基板 2 部品実装用パッド 3 第1のソルダーレジスト 4 第2のソルダーレジスト 5 マイラーフィルム 6 ソルダーレジストパターン DESCRIPTION OF SYMBOLS 1 Insulating board 2 Component mounting pad 3 First solder resist 4 Second solder resist 5 Mylar film 6 Solder resist pattern

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 基板上の狭小なスペース内にソルダーレ
ジストをパターニングして形成する印刷配線板の製造方
法であって、 現像速度の異なる2以上のソルダーレジストを基板全面
に塗布し、 前記ソルダーレジストに指触乾燥を行ない、 露光,現像工程を経て、基板上の狭小なスペース内にソ
ルダーレジストをパターニングして形成することを特徴
とする印刷配線板の製造方法。
1. A method of manufacturing a printed wiring board, comprising forming a solder resist in a narrow space on a substrate by patterning the solder resist, wherein two or more solder resists having different developing speeds are applied to the entire surface of the substrate. A method for manufacturing a printed wiring board, comprising: performing touch drying on a substrate; and performing exposure and development steps to pattern a solder resist in a narrow space on the substrate.
【請求項2】 現像速度の異なる2以上のソルダーレジ
ストは、上層より下層のものの現像速度を速く設定する
ことを特徴とする請求項1に記載の印刷配線板の製造方
法。
2. The method for manufacturing a printed wiring board according to claim 1, wherein the two or more solder resists having different developing speeds are set to have a higher developing speed for a lower layer than for an upper layer.
【請求項3】 現像速度の異なる2以上のソルダーレジ
ストは、酸価の違いによりアルカリ性現像液に対する現
像速度を異ならせることを特徴とする請求項2に記載の
印刷配線板の製造方法。
3. The method for manufacturing a printed wiring board according to claim 2, wherein the two or more solder resists having different developing speeds have different developing speeds with respect to an alkaline developer depending on a difference in acid value.
JP10173670A 1998-06-19 1998-06-19 Manufacture of printed wiring board Pending JP2000013004A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10173670A JP2000013004A (en) 1998-06-19 1998-06-19 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10173670A JP2000013004A (en) 1998-06-19 1998-06-19 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JP2000013004A true JP2000013004A (en) 2000-01-14

Family

ID=15964932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10173670A Pending JP2000013004A (en) 1998-06-19 1998-06-19 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JP2000013004A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100905568B1 (en) 2007-04-13 2009-07-02 삼성전기주식회사 Printed circuit board and method of manufacturing the same
KR101056404B1 (en) 2010-06-18 2011-08-11 아페리오(주) Method for manufacturing a solder resist dam
CN105338755A (en) * 2015-11-23 2016-02-17 深圳崇达多层线路板有限公司 Fabrication method of circuit board solder mask layer
CN105430933A (en) * 2015-12-22 2016-03-23 江苏博敏电子有限公司 Method for treating defects of half solder mask bridge in solder mask production process

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100905568B1 (en) 2007-04-13 2009-07-02 삼성전기주식회사 Printed circuit board and method of manufacturing the same
KR101056404B1 (en) 2010-06-18 2011-08-11 아페리오(주) Method for manufacturing a solder resist dam
CN105338755A (en) * 2015-11-23 2016-02-17 深圳崇达多层线路板有限公司 Fabrication method of circuit board solder mask layer
CN105338755B (en) * 2015-11-23 2018-04-24 深圳崇达多层线路板有限公司 A kind of production method of wiring board solder mask
CN105430933A (en) * 2015-12-22 2016-03-23 江苏博敏电子有限公司 Method for treating defects of half solder mask bridge in solder mask production process

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