JPH0642264B2 - Binary data memory - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary data memory, and more particularly to a binary data memory used in an arithmetic processing device that controls an arithmetic order by a data driving method.

(Prior Art and Its Problems) Conventionally, when a plurality of arithmetic processing mechanisms and input / output processing mechanisms are connected, a data flow processing device is fixed such as a multiplier, an adder, a memory access controller, an input / output controller, etc. A method has been developed and proposed in which an arithmetic (control) circuit having a single function is connected in a ring shape by a pipeline bus. In such a data flow processing device, it is necessary to select the type of arithmetic circuit and the order of arranging the arithmetic circuits to be optimum for a specific process, and the performance is remarkably deteriorated for other processes. There was a problem of doing. In addition, if the type and arrangement of the arithmetic units are changed according to the processing in this type of data flow processing device, the required types of arithmetic units increase and the cost increases. On the other hand, in this data flow processing device (described in Japanese Patent Laid-Open No. 58-70360), as shown in FIG. 2, the arithmetic circuit is multifunctionalized and integrated in a processor unit, and a transfer table memory is provided by a pipeline type bus. Two
2, parameter table memory 23, data memory 2
4, the queue memory 25 and the processor unit 26 are combined, and the data flow method is used for the binary operation.
When the control is performed using the initialized parameter table and the data memory, and the one equipped with the bus interface for inputting / outputting with the external circuit is regarded as one module, only the same module is connected in series. Therefore, a data flow processing device has been proposed, which has improved performance depending on the number of connections.

However, this data flow processing device has a transfer table memory 22 for storing the destination address of data.
A parameter table memory 23 that is accessed at the above address and stores an instruction, a data memory 24 that temporarily stores input data on one side of a binary operation, and a queue memory that waits for data from the data memory 25, a processor unit 26 for performing a binomial operation or a unary operation on the output of the queue memory and outputting it to the transfer table memory, a ring-shaped pipeline bus connecting them, the pipeline bus and an external bus. And a bus interface 21 for controlling the input / output of data between them, the processor unit operates according to an instruction arbitrarily set in the parameter table memory at the time of initialization. Is a binary operation (using two types of data Queue to hold the earlier arriving data until all the data of (input operation) are gathered, constant for constant operation, lookup table, transition table for state transition processing , Used to store input / output data. The write enable signal of the data memory 24 is input from the parameter table memory 23. When a binary operation instruction is designated and both data are collected, the input data from the parameter table memory 23 and the read data from the data memory 24 are simultaneously output to the queue memory 25.

The control by the data flow method in the binary operation is explained as follows.

That is, the number of input data to the processor unit 26 is one or two, and the number of output data is 1 to 16
Can be specified. The processing when the number of input data is one is called unary operation, and the processing when the number of input data is two is called binomial operation. Number of input data is 1 for unary operation
Therefore, it is not necessary to wait, but in the case of a binary operation, the operation that cannot be executed until the two pieces of data are complete, so the data that arrived first is saved in the binary queue in the data memory 24 and the wait is done. Then, when the data that arrives later arrives, the calculation in the processor unit 26 is started through the queue memory 25 together with the data read out from the binomial queue in the data memory. That is, the execution control of the data flow method is performed for the binary operation.

For example, when performing two kinds of binary operations of “A and B” and “A and C”, there are only two methods of preparing data A or treating A as an apparent constant and using it multiple times. It was However, the former method requires one instruction for duplication and the binary queue for the number of duplications, and the latter method uses a constant number, so that a part of the data memory is always occupied and a constant value There is a drawback that it is necessary to program the rewriting timing control with software.

(Object of the Invention) An object of the present invention is to eliminate the drawbacks of the conventional binary data memory and to provide a means for simplifying operation and programming when the same data is used, and effectively using the data memory. , To provide a binary data memory suitable for a data flow processing device.

(Structure of the Invention) According to the present invention, a data memory for storing data, and when a control signal added to input data instructs storage, the data is stored in the data memory in the order of input, and the control signal is read out. If instructed, the head data of the stored data in the data memory is read out and erased, and is output as a set data of the input data and the head data. If the control signal directs duplication, the stored data is stored. And a read control unit for producing duplicated data of the first data of the above and outputting it as a set of data together with the input data.

(Example) The Example of this invention is described with reference to drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, the present embodiment includes a data memory unit 10 in a data flow processing device, and a read control unit 11 that controls the data memory unit and is connected to a signal line 100. Signal line 100
Is a data input line, and the input data consists of a data value, an identifier, and a control signal. The data value of the input data is sent to the data memory unit 10 and the read control unit 11 through the signal line 10
It is input from 1.

On the other hand, the identifier and the control signal are provided on the signal lines 102 and 10 respectively.
3 is input to the read control unit 11. The read control unit 11 has a working memory inside and sets the contents of the working memory in advance before starting the process using the data value input from the signal line 101. FIG. 3 shows an example of a working memory composed of N words.

The input data identifier is used to specify one of the N words of the working memory. For example, if the identifier is n, the content of one word at address n is used for the operation as shown in FIG. FIG. 4 shows an example in which one word at the address n is composed of five fields. The first field 41 is a write address, and this value is a relative write address when writing the input data in the data memory, and is incremented (added by 1) when the writing is completed.

The second field 42 is the read address and this value is 2
This is a relative read address for reading the data of the other side of the term operation from the data memory 10, and there are cases where it is incremented after the completion of reading and cases where it is not incremented.

The third field 43 is a buffer size, and is used to set the size of the buffer area in the data memory 10 prepared for each identifier. When both the write address and the read address are incremented to reach the buffer size, they are cleared to zero at the next increment, so that the address value is rotated forward and the buffer area is effectively used.

The fourth field 44 is an offset address, which gives the head address in the data memory 10 of the buffer area for each identifier.

The fifth field 45 is a status and holds whether the last operation performed is a data memory read but a write. When the write address and the read address match, if the status is read, it means that the buffer is empty, and if the status is write, it means that the buffer is full.

From the read control unit 11 to the memory memory 10, the address is the signal line 104, and the read / write control signal is the signal line 10.
It is input by 5. The data read from the data memory 10 by the signal line 106 is output to the outside as binary data set data together with the input data of the signal line 100.

The specific operation of this embodiment will be described below. The data to be operated for the binary operation have the same identifier. However, the control signal added to the data includes 1 bit of information (store flag) for further identifying which of the two terms is the data. When the store flag is true, the input data is held in the order in which it is input to the data memory 10, but its address is an address whose write address is a relative value to the offset address in the working memory inside the read control unit 11. is there. After the write operation, the write address is incremented to indicate the next write address.

Next, when the store flag is false input data, the input data and the data held in the data memory unit 10 are output as the operated set data. However, the operation at that time differs depending on whether the count flag in the control signal added to the input data is true or false.

(1) When the count flag is true: Data is read from the data memory 10 from an address that is offset from the offset address by the read address, and is output as set data together with the input data. At this time, the read address is incremented and the next data of the read data is read for the input data to be read next.

(2) When the count flag is false: Data is copied from the data memory 10 from an address offset from the offset address by the read address, and is output as set data together with the input data. At this time, the read address is not incremented, and the same data as the read data is read for the input data to be read next.

FIG. 5 shows group data output for binary operation when the data to which the store flag (true indicates by S and false) and the count flag (true indicates by C, false by) arrives in numerical order. Is schematically shown.

As described above, according to the embodiment of the present invention, in the conventional data flow processing device (Japanese Patent Laid-Open No. 58-70360), when the same data is used in a plurality of binary operations, a duplication instruction is used to obtain the required number of data. There is no need to copy, the number of instructions can be saved, and the binary waiting buffer for each duplicated data becomes unnecessary, which can shorten the processing time and reduce the used area of the data memory. Further, according to the embodiment of the present invention, it is not necessary to program the timing for exchanging constant values by software, as compared with the case where the constant values are secured in the data memory.
The next value can be automatically read by the count flag added to the read data.

Note that the embodiment of the present invention can be applied to any data flow type arithmetic device which performs the binary waiting control.

(Effects of the Invention) As described above, the present invention simplifies calculation and programming when using the same data several times, can effectively use the data memory, shortens the processing time, and reduces the usage area of the data memory. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional data processing device, FIG. 3 is a diagram showing a working memory, and FIG.
FIG. 5 is a diagram showing the structure of words, and FIG. 5 is a schematic diagram showing the operation of the present invention. 10 ... Data memory unit, 11 ... Read control unit, 1
00-106 ... Signal lines.

Claims (1)

[Claims] 1. A data memory for storing data, and when a control signal added to input data instructs storage, the data is stored in the data memory in the order of input, and when the control signal instructs reading. The head data of the stored data in the data memory is read and erased, and is output as a set data of the input data and the head data, and when the control signal instructs duplication, the duplicated data of the head data of the stored data. And a read-out control section for outputting as a set data together with the input data, and a binary data memory.