JPS6159543A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the pressure on mounting against a common logic, and to facilitate the register read/write from a CPU and the like by providing a local memory, local memory read structure and register read/write control structure. CONSTITUTION:An exchange table between a virtual address corresponding to a logical mean of a register against all registers and a physical register address corresponding to the bit and byte unit, is stocked in a local memory 8. In case a read/write of the register is actuated by using a virtual register address from a SVP1 or a CPU3, a register read/write control part 2' reads a physical register address from an exchange table using a local memory read structure 26 from the memory 8. The obtained physical register address is dispatched to a register address conversion structure 25 in the control part 2' to read a physically diffused register, edit the read data corresponding to a virtual address and carry out the register write processing.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an information processing device, and particularly to an information processing device having a maintenance function suitable for easily reading/writing register contents from a panel or other processing device. It relates to a processing device.

[Background of the invention]

FIGS. 4 and 5 show register read/write logic according to the prior art. FIG. 4 is a conceptual diagram of register read/write logic, and FIG. 5 is a block diagram of register read/write logic. Conventionally, as shown in FIG. 4, register reading/writing in the CPU is carried out from the service processor 5VPI or the central processing unit CPU 3 via the data buses 5 and 6 and the data bus 4, and is attached to the CPU. Register read/write control unit 2
Activation of register read/write operations and register read/write data transfer are performed for the register read/write operations. Read register/:! The F write control unit 2 uses the data buses 4, 5.6 to control the register read/IF write and register read/write data to the CPU 3 by starting the register read/write operation from the 5VPI or the CPU 3. Make a transfer. The register read/write process will be explained in more detail with reference to FIG. The register read/write control unit 2 includes an address register 20 that holds register addresses, which are information necessary to perform register read/write processing, and a write data register 21 that holds register read data and register write data.Read data It has a register 22. 11 in the address register 20. The address of the register for which a read or write operation is performed in row 5 pair & is held, and the write data 1/ginuta 21 holds 1 byte of live data necessary to perform a write operation to the register, and the read data The register 22 holds one byte of read data from the target register after the read operation is completed. The register address structure is divided into a north address and a lower address. The L address specifies a flip-flop group in which the registers in the information processing device are collected in 1-byte units, and the lower address specifies the register within 1 byte of that flip-flop group. Specify bit.

Set the address to the address register 20 above.

Writing data to the write data register 21 is performed from 5VPI or CPU 3 via data bus 5 or 6 to data bus 4, and SVP 1 or C
The PU 3 sets the above data and starts a register read/write operation for the register read/write control unit 2. When the register read is finished, the PU 3 sends the read data from the read data register 22 via the data bus 4 to the data node ( The register read/write control unit 2 is read via the SVP bus 5 or 6.
Read and write operations are performed in units of 1 byte of data (8 data bits and 1 parity bit) by operation activation from CPU 1 or CPU 3. Address register 2 if a register write operation is activated.
The upper address of the contents of 0 is data no kusufu and 32
The clip prop group 30 is supplied to the upper address decoder 301 through
Register word selection signal 37 specifying 6 or 307
or 38 to enable the lower address decoder 302 or 303. Naori lip-flop groups are collected in units of one node. The lower address decoder 302 or 303 is supplied with the lower address through the data node 36, and receives a bit selection signal 39-O that specifies the bit-by-bit busy flip-flop in the flip-flop group 306 or 307 specified by the upper address.
or 39-1 or 39-7 or 39-8, and its bit selection signal 39-0 or 39-1 or 39-8.
7 or 39-8 and the write data selected from the write data register 21 according to the value of the lower address counter 23 through the write data line 34, and the write instruction sent from the write instruction clip-flop 24 through the data write instruction signal 33. AND with signal
and the objective flip-flop 1 where the AND condition is satisfied.
Write data to bit. By repeating the above register write operation 9 times by sequentially changing the lower address from 0 to 8, the data is written to 8 data bits and 1 parity bit in the 1-byte flip-flop group specified by the address. Write the write data in the data register 21. Changes in the lower address are performed by a register read/write machine provided within the register read/write mechanism 2 separately from the lower address portion within the address register 2! The data in the lower address counter 23, whose count-up is controlled by R2, is sent to the CPU 3 as a lower address 5, and the register read/write control mechanism 2 reads the data in the lower address counter 23 in the address register 20 (7) regardless of the lower address value. /ri23 to 0
This is achieved by changing the number from 8 to 8. When a register read operation is activated, the register word selection signal 37 or 38 is generated to enable the bit selector 304 or 305 in the same manner as the register write operation;
At the same time, by supplying the lower address to the bit selector 304 or 305 via the data bus 36, the flip-flop group 306 or 3 specified by the upper address is
The value of one bit of the flip-flop specified by the lower address in 07 is read out from the bit selector 304 or 305 and the read data line 35. It is sent to the register read/write mechanism 2 via the data bus 7. The register read/write mechanism 2 sets one bit of read data to the bit position in the read data register 22 specified by the value of the lower address input/26. The above read operation is performed in the same way as the write operation, the lower address is changed from O to 8, 1 byte (8 bits of data and 1 bit of parity) is read into the read data register 22, and 1 in the read data register 22 is read out. Byte data to 5vP1 or CPU3 data path 4,
5.6. By performing the above operations, register read/write is performed for any one byte. The information processing device has the above-described register read/write only logic in addition to the normal logic.

By the way, it is expected that current and future packaging technology for information processing devices will lead to higher density packaging and an increase in logical scale. That is, the number of flip-flops increases, and the number of register read/write dedicated logics such as address decoders and bit selectors required for register read/write also increases. It is also expected that the LSI rate within information processing devices will increase. Conventionally, flip-flop groups specified by high-order addresses are logically related ones that are collected and assigned high-order addresses, so flip-flop groups 307 in FIG. It is often the case that the upper addresses are assigned across LSIs. Then, as mentioned earlier, as information processing devices become more densely packed and have a high LSI, the number of clip-flops increases, and when upper addresses are assigned for logical correspondence, the number of LSIs in the flip-flop group increases, resulting in register reading/@ The read-only logic has become more complex and diverse, and the number of LSI pins used for the register read/write-only logic has also increased, with the register word selection signal 38 and the output line 311 of the bit selector 310 passing between the LSIs 30 and 31 in FIG. Read register as shown/? The number increases by exchanging signals between LSIs with write-only logic. This puts pressure on the number of LSI pins that can be used for normal logic, and the number of LSI pins that can be used for normal logic is reduced as LSIs become more highly integrated.
This will further reduce the number of I pins/logical scale ratio, and together with the complexity and diversification of register read/write only logic, the problem will arise that it will put pressure on normal logic.

Note that Japanese Patent Publication No. 58-53774 is a known example of the above-mentioned register read/write processing.

[Purpose of the invention]

The purpose of the present invention is to solve such problems by achieving uniform simplification of register read/8' read-only logic while realizing large-scale, high-density packaging of information processing devices, and improving implementation efficiency compared to normal logic. Reduce pressure and SVP or CPU
Read register from 1. An object of the present invention is to provide an information processing device that can easily perform writing operations.

[Summary of the invention]

In the IC+6 of the present invention, instead of collecting flip-flop groups specified by the register address in logical correspondence as shown in the prior art example, flip-flop groups are formed in correspondence with physical arrangement. % in information processing equipment that uses register addressing to eliminate the need for flip-flop groups to cross LSIs and uniformly simplify register read/write logic.
A local memory that can read and write data directly from the SVP and register read/write control mechanism, and a register address specified by the SVP or CPU that refers to the local memory and transfers data in the local memory to the register read/write mechanism. and a local memory read mechanism.

Register read/write is a register address conversion mechanism that reads and writes data to the register using the data supplied from the local memory read mechanism as a register address.
The write mechanism stores in local memory a register address that is associated with the physical location of the corresponding register for each bit of the logically associated register address designated by the SVP and CPU. Then, when there is a register read or write request from the SVP or CPU, read the register address corresponding to each pin of the requested address from the local memory, read the register using the read address, and then, in the case of a read request. performs bit-based data merging, and in the case of writing, the write data specified by the SVP or CPU is merged into the corresponding focus of the read data in a bit-based manner, and then the merged data is written to the register and written to the register.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a schematic diagram, and FIG. 2 is a detailed block diagram. 1.3 to 7 in FIGS. 1 and 2 are the same as those in the prior art example. 2 is a register read/write control unit, 8
is a local memory that can be referenced from 5vP1 and the register read/write control unit 2, 10 is a read/write path for data in the local memory 8 from 5VPI,
Reference numeral 9 indicates a data read/write path in the local memory 8 from the register read/write control unit 2, 26 indicates a local memory read mechanism provided within the register read/write control unit 2, and 25 indicates a path within the register read/write control unit 2. This figure shows the register address translation mechanism provided in the .

As shown in FIG. 1, according to this embodiment, the local memory 8
svp and register read/write control unit 2
Data can be read from the local memory read mechanism 26 in the local memory read mechanism 2.
By sending the data read from the local memory 8 by 6 to the register address converter [25, the register address converter 25 can use the data read from the local memory 8 for register address conversion processing. . In this embodiment, for all registers in an information processing device, register address conversion is performed between a virtual register address corresponding to the logical meaning of the register and a physical register address corresponding to the bit unit or byte unit of the virtual register address. The table is stored in the local memory 8. When register read/write is started from 5VPI or CPU 3 using a virtual register address, the register control unit 2 reads each of the virtual register addresses. The physical register address corresponding to bit + or] (can be obtained by reading the physical register address corresponding to bit+ite from the register address conversion table in the local memory 8 using the memory read mechanism 26.The physical register address obtained in this way By sending the address to the register address conversion mechanism 25 in the register read/write control unit 2, reading of physically distributed registers, editing of the read data to correspond to virtual register addresses, and register writing processing are performed. I can do things.

Next, a register read/write processing method when register address conversion is performed will be explained with reference to FIG. In this embodiment, in addition to the above-mentioned register address converter 25 and local memory reader 26, a virtual address register 27 is used.
．． Virtual address compatible stale data register 28. A virtual address corresponding read data register 29 is provided in the register read/write control section 2'. Register writing′
When performing a write operation, the 5VPI or CPU 3 sends the virtual register address to the virtual address register 27 via the data bus 5 or 6 and 4, writes the write data corresponding to the virtual register address to the virtual address corresponding write data register, and writes the data into the register. The read/write control unit 2 is prevented from starting a register write operation. In the register read/write control unit 2 that has been activated for register write operation, the virtual address register 2
The virtual register address is read from 0 and sent to the register address conversion mechanism 25. The register address translation mechanism 25 uses virtual register addresses to convert the local memory 8
The physical register address corresponding to the virtual register address is read from the register address translation table and set in the address register 20. In this embodiment, the register address conversion table in the local memory 8 allows searching for physical register addresses for each bit of the virtual register address, and the physical register addresses are sorted in the order of virtual register addresses. can be easily searched using virtual register addresses.

Next, using the physical register address set in the address register 20, first, one byte of the flip-flop group specified by the upper address is read from the register in the same manner as the register read operation described in the conventional example, and the read line 35 is read. 1 byte of data is sent to the register read/write control unit 2 through the register read/write controller 2 and set in the read data register 22.Next, 1 bit of write data corresponding to the virtual register address is sent from the virtual address corresponding write data register 28. Selected by the lower address of the virtual register address in the virtual address register 27, the destination in the read data register 22 is 1 specified by the upper address of the read physical register address.
The byte of data is merged into the bit position specified by the lower address of the physical register address in the address register 20 in the register address conversion mechanism 25, the merged 1 byte of data is set in the write data register 21, and the address register is 20 as the write address, write data register 2
By using 1 byte of data in 1 as write data and writing data to 1 byte of the target flip-flop group using the same method as the write operation shown in the conventional technology,
Writes 1-bit data specified by the virtual register address.

When performing a register write operation in 1-byte units, the lower address of the virtual register address is changed from O to 8 by the register read/write mechanism 2, and the above register write operation in 1-bit units is performed 9 times (data bit 8
This is achieved by performing the following steps: 1 time, 1 parity bit). Furthermore, if the register read operation activation is interrupted by the register read/write control unit 2K, the register read/write control unit 2 uses the register address conversion table in the local memory 8 and the local memory read mechanism 26 in the same way as register write. Then, the physical register address is determined using the virtual register address and set in the address register 20. Thereafter, data of one byte of the flip-flop group specified by the upper address of the physical register address in the address register 20 is read out and set in the data register 22 in the same manner as in the conventional example. Among the 1-byte data in the read data register 22, 1 bit specified by the lower address of the physical register address in the address register 20 is read, and the data is read out from the virtual address register 27 of the read data register 29 corresponding to the virtual address.
The bit position specified by the lower address of the virtual register address within is set, and the read operation of the 1-bit data specified by the virtual register address is completed. The above read operation can also be performed in units of 1 bit or in units of 1 byte, and the read operation in units of 1 byte is performed eight times in the same way as the write operation. The register read/write control unit 2 reads the data in the virtual address corresponding read data register 29 to 5VP1 or CPU3.
The data is transferred via the data bus 5.6.4 to complete the read process.

As explained above, register reading/writing is performed when virtual register addresses and physical register addresses are converted. However, in this case, the register read/write only logic in CPUa is such that the register address used to directly read or write the register is a physical register address created corresponding to the physical arrangement of the registers, and the upper address Since the flip-flop group specified by is grouped together within the LSI, the amount of logic is smaller than when the seven flip-flop groups are spread across LSIs, and the logic is the same between LSIs, making the logic simple. This makes it possible to reduce implementation pressure on normal logic.

Next, the register address conversion method in this embodiment will be explained with reference to FIG.

In FIG. 3, only the register address converter m25 and the local memory 8 are extracted, and the other parts depicted in FIGS. 1 and 2 are omitted. In this embodiment, a directory table 80. is stored in the local memory 8 as a register address conversion table. There are three types of data address table 81 and parity address table 820.

The data structure within the element of the directory table 80 includes a data address table 81 and a parity address table 820 in which the start addresses in the local memory 8 are stored. The data structure in the element of the data address table 81 has one byte processing identification bit (T bit), and the remaining part in the element stores the physical register address corresponding to each bit of the virtual register address that specifies this element. The data structure within the elements of the parity address table 82 is the structure of the elements and rows of the data address triple 81. Also 1. The register add conversion table 25 includes an adder 25o.

It has shifters 251, 252 and counter 253. Here, the function of the T bit in this embodiment will be explained. T
A bit is information indicating whether or not the flip-flop groups specified by the upper addresses of the two addresses are the same between the corresponding virtual register address and physical register address. In other words, when the T bit is O, it indicates that the 7 flip-flops in the flip-flop group specified by the upper address of the virtual register address are scattered in the flip-flop group divided by several sets of physical register addresses, and T When the bit is 1, it indicates that the 7 flip-flops in the flip-flop group specified by the upper address of the virtual register address exist as the same 79717071 group even when viewed from the physical register address. In other words, when the T bit is O, it means that the upper addresses of the physical register addresses assigned to the flip-flops in the 1-byte 7-lip-flop group specified by the upper address of the virtual register address differ by 1 bit, and the T bit When is 1, it means that the upper addresses of the physical addresses assigned to the 7 flip-flops in the 7 flip-flop group are all the same between the flip-flops. It should be noted that various configurations of the conversion table other than the above-mentioned embodiments are possible. Now, when a register read or write operation is activated, the register address conversion mechanism 25 first reads a virtual register address from the virtual address register 20. The register address conversion mechanism 25 divides the high-order address of the virtual register address into a fixed part and a conversion part, and first shifts the fixed part to the left by a number of bits according to the data width of the data in the directory table 80 using a shifter 251. The directory table 80 is searched using the fixed part of the directory table 80 as an address in the local memory 8, and if the lower address of the virtual register address specifies the data part of the flip-flop group specified by the upper address, the data address table is searched. The head address value is read out from the directory table 80 by selecting the head address value of the parity address table if the lower address of the virtual register specifies the parity part of the flip-flop group specified by the upper address. Next, the parts other than the fixed part of the virtual register address, that is, the upper address conversion part and the lower address, are shifted to the left by a number of bits in shift 252 according to the data width of the data in the data address table 81 or the parity address table 82, and after that shift, and the data address table first address value or the first seven address values of the parity address table read from the directory table 80 in the adder 250, and the addition result is added to the local address value of the data address table 81 or the parity address table 82. If the start address value read from the directory table 80 is the data address table start address value as an address in the memory, the data address table 81 is de-f
If the start address value read from the left table 80 is the parity address table start address value, the parity address table 82 is searched, and the upper address of the virtual register address used to search the data address table 81 or the parity address table 82 is obtained. A physical upper address translation unit and a physical lower address corresponding to the translation unit and the lower address are read from the data address table 81 or the parity address table 82. Finally, in the register address converter $25, the upper address fixed part of the virtual register address and the data address table 81 are merged into the physical upper address converter and the physical lower address read from the parity address table 82, and the physical register Setting the address in the address register 20 as an address is the register address conversion process for one bit of the virtual register address.

When performing a register read/write operation in 1-byte units, the counter 253 in the address conversion mechanism 25 converts the virtual lower address (from 0 to 8) into the virtual upper address sent from the virtual address register 27. The created address is merged with the upper address, and the merged address is used as a virtual address and address translation processing is performed. At this time, when the virtual lower address created by the counter 253 is O, the subsequent processing is controlled as follows based on the value of the T bit attached to the physical address obtained by searching the data address table 81. . If the T bit is 0, the value of the T bit is sent to the counter 253 through the signal line 256 and the counter is updated.

(The physical address is updated every time the physical address is read thereafter.) At the same time, the physical address obtained at that time is sent to the address register 20, and the register read or write operation for 1 bit described above for the virtual lower address O is performed. next,
Using the virtual lower address that was set to 1 by updating the counter 253 during the previous physical address search, address conversion processing is performed to obtain a physical address, and at the same time, the counter 253 is updated, and the physical address is sent to the address register 20 to obtain the virtual lower address. A register read or write operation for 1 is performed. Thereafter, address conversion processing and register read/''# write operations are performed in the same manner every time the virtual lower address changes from 2 to 8, and the 1-bit register address conversion process described above is converted to 1-byte register read or write. The motion is performed a total of 8 times.

If the T bit is 1, it is passed through signal line 256 to counter 2.
53, and updating of the counter is suppressed. Then, the physical address obtained at that time is sent to the address register 20, and thereafter, one byte worth of register read or write processing is performed using the address in the address register 20 in the same manner as in the conventional example. In other words, when the T bit is 1, only one address conversion process is performed for a 1-byte register read or write operation. Register address conversion processing is performed as described above, and although the table format in the local memory is made to correspond to bits of virtual register addresses in this embodiment, there are other register address conversions such as byte correspondence of virtual register addresses. Consider a table format. Further, the data format in the table does not only indicate addresses, but also allows information necessary for register address conversion processing to be stored, such as the T bit in this embodiment. Also, shifters 251 and 25
The shift value of 2 is determined by the data capacity of the table or the data width of the table element, and various values can be considered depending on the configuration of the table, and the shift value may be a fixed value or a variable value. Register address conversion mechanism 25
The logical configuration within can also take on various configurations depending on the register address conversion processing method.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to uniformly simplify register read/write only logic in an information processing device and reduce pressure on normal logic, thereby improving the logic quality of register read/write only logic. Furthermore, since the register values in the information processing apparatus can be easily read/written, it is also effective in improving the efficiency of maintenance and adjustment work of the information processing apparatus.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing FIG. 1 in detail, Figure 3 is a diagram showing a register address conversion table and a register address conversion mechanism,
FIG. 4 is a diagram showing a conventional example, and FIG. 5 is a detailed block diagram of the fourth conventional example. DESCRIPTION OF SYMBOLS 1... Service processor 2... Register read/write control unit 3... Central processing unit, 8... Local memory 9... Data bus, 20... Address register 21... Moss-filled data Register 22... Correction data register 23... Lower address counter 24... Write instruction flip-flop 2G... Local memory read/write mechanism 24... Write instruction signal generation flip-flop 25... Register address converter m 27...Virtual address register 28...Virtual address corresponding write register 29...
・Virtual address corresponding read registers 30, 31...
・LSI 32...Register address data bus 33...Write instruction signal line 34...Front/write data line 35...Read data line 36...Lower address data bus 37, 38, 39...・Register word selection signal 3
9-0.1, 7.8...Bit selection signal 301...
Upper address decoders 302, 303...lower address decoder 304
, 305... data selectors 306, 307...
Flip-flop group 80...Directory table 81...Data address table 82...Harness address table 250...Adders 251, 252...Sick. Figure 1, Figure 2, and Figure 10.

Claims (1)

[Claims] Comprised of a central processing unit (hereinafter abbreviated as CPU) and a service processor (hereinafter abbreviated as SVP), the CPU and SV
In an information processing device having a register read/write mechanism that reads and writes to a CPU register in response to a request from P, a local memory capable of directly reading and writing data from the SVP and the register read/write mechanism, and the SVP and CPU
A local memory read mechanism that allows the register read/write mechanism to read the contents of the local memory specified by the register address specified by the register address, and a register read and write function that uses the data read from the local memory as a register address. An information processing device characterized by being provided with a register read/write control mechanism for controlling the register read/write control mechanism. The register read/write control mechanism uses the data read from the local memory as a register address for a 1-bit register to read/write the register according to the value of a bit attached to the data used as a register address in the local memory. Information processing according to claim 1, characterized in that the register read/write operation is performed by controlling whether to perform a write operation or to perform a register read/write operation by using it as a register address for a multi-bit register. Device.