JPH06326102A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH06326102A
JPH06326102A JP13539893A JP13539893A JPH06326102A JP H06326102 A JPH06326102 A JP H06326102A JP 13539893 A JP13539893 A JP 13539893A JP 13539893 A JP13539893 A JP 13539893A JP H06326102 A JPH06326102 A JP H06326102A
Authority
JP
Japan
Prior art keywords
film
wiring
metal
metal film
tio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13539893A
Other languages
Japanese (ja)
Other versions
JP3283965B2 (en
Inventor
Tadashi Iijima
匡 飯島
Toshiko Ono
寿子 小野
Yukihiro Ushiku
幸広 牛久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13539893A priority Critical patent/JP3283965B2/en
Priority to DE4447597A priority patent/DE4447597B4/en
Priority to DE4400200A priority patent/DE4400200C2/en
Publication of JPH06326102A publication Critical patent/JPH06326102A/en
Priority to US08/480,733 priority patent/US5529954A/en
Priority to US08/588,511 priority patent/US5763953A/en
Application granted granted Critical
Publication of JP3283965B2 publication Critical patent/JP3283965B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To realize a practical low-resistance metallic wiring instead of an Al wiring by laminating a first metal film and a second metal film composed mainly of silver on a semiconductor substrate and forming a protective film containing the same metal as the first metal film to cover the surface of the second metal film. CONSTITUTION:An SiO2 film 2 is formed on a semiconductor substrate 1, and a groove for a buried wiring is formed in the SiO2 film 2. Then, a TiN film 3, a Ti film 4 and an Ag film 5 are formed sequentially on the whole face of the SiO2 film 2. Then, the TiN film 3, the Ti film 4 and the Ag film 5 in parts other than the groove part are removed, and a buried Ag wiring layer is formed. After that, an annealing operation is performed in an Ar gas atmosphere at 600 deg.C for 30 minutes, and a TiO2 film 6 is formed on the surface of the Ag film 5. Lastly, an interlayer insulating film 7 is deposited on the whole face, and the buried wiring is finished. Thereby, it is possible to restrain Ag from agglomerating in the Ag film 5, and wiring which utilizes the low resistivity of Ag can be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、配線材料にAgを使用
した半導体装置およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using Ag as a wiring material and a method for manufacturing the same.

【0002】[0002]

【従来の技術】近年、半導体装置の高集積化に伴い、配
線幅,配線膜厚の縮小化や多層配線化が進められてきて
いる。配線材料としては従来よりAlが用いられてき
た。しかし、素子の微細化によって配線断面積が縮小化
しても、信号電流の低減化が図られていないため、電流
密度が増加し、エレクトロマイグレ−ションによる断線
が問題となっている。また、多層配線化に伴い、配線は
複雑な熱履歴を受けるため、配線に加わる熱ストレスに
よるストレスマイグレ−ションによる断線も問題になっ
ている。
2. Description of the Related Art In recent years, with the high integration of semiconductor devices, reduction of wiring width and wiring film thickness and multilayer wiring have been promoted. Al has conventionally been used as a wiring material. However, even if the wiring cross-sectional area is reduced due to the miniaturization of the element, the signal current has not been reduced, so that the current density increases and disconnection due to electromigration poses a problem. Further, with the multi-layered wiring, the wiring undergoes a complicated thermal history, so that disconnection due to stress migration due to thermal stress applied to the wiring is also a problem.

【0003】そこで、Alよりも抵抗が低く、しかも、
エレクトロマイグレ−ションおよびストレスマイグレ−
ション耐性に優れた次世代配線材料として、Cu,Ag
の検討が始められている。しかし、Cuは約200℃の
低温でもその内部まで酸化されてしまう。このような酸
化は抵抗の増大を招くので防止する必要がある。
Therefore, the resistance is lower than that of Al, and
Electro migration and stress migration
Cu and Ag as next-generation wiring materials with excellent resistance to ionization
The examination of is started. However, Cu is oxidized even at the low temperature of about 200 ° C. Such oxidation causes an increase in resistance and must be prevented.

【0004】これを実現するために、Cuを保護膜で被
覆するという手法が提案されている(特開昭63−15
6341)。この技術は図9(a)に示すように、ま
ず、シリコン基板81上にSiO2 膜82を形成し、こ
のSiO2 膜82上にTi膜83,TiN膜84,Cu
膜85,TiN膜86からなる積層膜を形成する。
In order to realize this, a method of coating Cu with a protective film has been proposed (Japanese Patent Laid-Open No. 63-15).
6341). In this technique, as shown in FIG. 9A, first, a SiO 2 film 82 is formed on a silicon substrate 81, and a Ti film 83, a TiN film 84, and a Cu film are formed on the SiO 2 film 82.
A laminated film including the film 85 and the TiN film 86 is formed.

【0005】次に図9(b)に示すように、上記積層膜
の側面がTiN膜87で被覆されるように、全面にTi
N膜87を堆積する。
Next, as shown in FIG. 9B, the entire surface of the laminated film is covered with the TiN film 87 so that the side surface of the laminated film is covered with Ti.
The N film 87 is deposited.

【0006】最後に、上記積層膜の側面以外のTiN膜
87を選択的に除去することにより、Cu膜85がTi
膜86,87で被覆された構造のCu配線が得られる。
Finally, by selectively removing the TiN film 87 other than the side surface of the laminated film, the Cu film 85 becomes Ti.
A Cu wiring having a structure covered with the films 86 and 87 is obtained.

【0007】しかしながら、この方法は工程数が多く複
雑で実用が困難であるという問題がある。
However, this method has a problem that it has many steps and is complicated, and it is difficult to put it into practical use.

【0008】また、Cu膜を保護膜で被覆する他のCu
配線の形成方法として、熱処理を利用したものが提案さ
れている(特開昭64−59938)。これは図10
(a)に示すように、まず、絶縁膜91上に拡散バリア
メタル膜92,Cu・Ti合金膜93を順次堆積する。
[0008] Further, other Cu coating the Cu film with a protective film
A method using heat treatment has been proposed as a method for forming wiring (Japanese Patent Laid-Open No. 64-59938). This is
As shown in (a), first, a diffusion barrier metal film 92 and a Cu · Ti alloy film 93 are sequentially deposited on the insulating film 91.

【0009】次に図10(b)に示すように、拡散バリ
アメタル膜92,Cu・Ti合金膜93を配線状にパタ
ーニングする。
Next, as shown in FIG. 10B, the diffusion barrier metal film 92 and the Cu / Ti alloy film 93 are patterned into a wiring shape.

【0010】最後に、図10(c)に示すように、Nを
含むガス雰囲気中での熱処理によって、Cu・Ti合金
膜93中のTiをCu・Ti合金膜93の上面および側
面に拡散させ、Cu・Ti合金膜93を保護膜であるT
iN膜94および配線であるCu配線95に変える。
Finally, as shown in FIG. 10C, heat treatment in a gas atmosphere containing N diffuses Ti in the Cu.Ti alloy film 93 to the upper surface and side surfaces of the Cu.Ti alloy film 93. , Cu.Ti alloy film 93 as a protective film T
The iN film 94 and the Cu wiring 95 which is the wiring are changed.

【0011】しかしながら、この方法を用いて実際にT
iN膜93を形成してみると、低抵抗のCu配線95を
得るには熱処理温度を高くしなければならず、素子の拡
散層内の不純物が再拡散し、素子が劣化するという問題
があった。また、熱処理温度が低い場合には、Cu配線
95中にTiが残留し、配線抵抗が増大するという問題
があった。
However, using this method, the T
When the iN film 93 is formed, the heat treatment temperature must be raised in order to obtain the Cu wiring 95 having a low resistance, and there is a problem that impurities in the diffusion layer of the element are rediffused and the element is deteriorated. It was Further, when the heat treatment temperature is low, there is a problem that Ti remains in the Cu wiring 95 and the wiring resistance increases.

【0012】一方、Agは、大気中で約70℃以上の加
熱により、容易に凝集を起こすため、現在までほとんど
その検討がされていない。
[0012] On the other hand, Ag easily aggregates when heated to about 70 ° C or higher in the atmosphere, and thus its study has hardly been conducted until now.

【0013】[0013]

【発明が解決しようとする課題】上述の如く、次世代配
線材料としてCu,Agの検討が始められている。しか
し、Cuは約200℃の低温でもその内部まで酸化され
てしまう。そこで、Cuを保護膜で被覆するという技術
が提案された。
As described above, studies on Cu and Ag have begun as a next-generation wiring material. However, Cu is oxidized even at the low temperature of about 200 ° C. Therefore, a technique of coating Cu with a protective film has been proposed.

【0014】しかしながら、工程数が多く実用的でなか
ったり、配線抵抗を小さくするには高温熱処理が必要
で、この高温熱処理によって拡散層内の不純物が再拡散
し、素子が劣化するという問題があった。
However, there are problems that the number of steps is large and it is not practical, and that high-temperature heat treatment is required to reduce the wiring resistance, and that the high-temperature heat treatment re-diffuses impurities in the diffusion layer and deteriorates the element. It was

【0015】一方、Agは、大気中で約70℃以上の加
熱により、容易に凝集を起こすため、現在までほとんど
その検討がされていなかった。
On the other hand, Ag easily aggregates when heated to about 70 ° C. or higher in the atmosphere, and thus its study has hardly been conducted until now.

【0016】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、Al配線に代わる実用
的な低抵抗の金属配線を有する半導体装置およびその製
造方法を提供することにある。
The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor device having a practical low resistance metal wiring in place of an Al wiring and a method for manufacturing the same. is there.

【0017】[0017]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置は、半導体基板上に形成され
た第1の金属膜と、この第1の金属膜上に形成された銀
を主成分とする第2の金属膜と、この第2の金属膜の少
なくとも上面を被覆し、前記第1の金属膜の金属元素を
含む保護膜とを備えたことを特徴とする。
In order to achieve the above object, a semiconductor device of the present invention comprises a first metal film formed on a semiconductor substrate and a first metal film formed on the first metal film. A second metal film containing silver as a main component, and a protective film that covers at least the upper surface of the second metal film and contains the metal element of the first metal film are provided.

【0018】また、本発明の半導体装置の製造方法は、
半導体基板上に第1の金属膜を形成する工程と、この第
1の金属膜上に銀を主成分とする第2の金属膜を形成す
る工程と、所定元素が含まれるガス雰囲気中の熱処理に
よって、前記第1の金属膜中の一部の金属を前記第2の
金属膜の表面まで拡散させ、前記所定元素と前記第1の
金属膜中の一部の金属とからなる銀凝集防止用の保護膜
を前記第2の金属膜の表面に形成する工程とを備えたこ
とを特徴とする。
The semiconductor device manufacturing method of the present invention is
A step of forming a first metal film on a semiconductor substrate, a step of forming a second metal film containing silver as a main component on the first metal film, and a heat treatment in a gas atmosphere containing a predetermined element. To diffuse a part of the metal in the first metal film to the surface of the second metal film to prevent silver agglomeration consisting of the predetermined element and a part of the metal in the first metal film. Forming a protective film on the surface of the second metal film.

【0019】また、上記第1の金属膜はチタン膜である
ことが好ましい。更に、上記熱処理の温度は450℃以
上750℃以下で、上記所定元素は酸素であることが好
ましい。
The first metal film is preferably a titanium film. Further, it is preferable that the temperature of the heat treatment is 450 ° C. or higher and 750 ° C. or lower, and the predetermined element is oxygen.

【0020】[0020]

【作用】本発明の半導体装置によれば、銀を主成分とす
る第2の金属膜は、保護膜で被覆された分だけ銀の凝集
が抑制され、信頼性の向上が図れる。
According to the semiconductor device of the present invention, the second metal film containing silver as a main component suppresses the aggregation of silver by the amount covered by the protective film, thereby improving the reliability.

【0021】また、上記第2の金属膜は少なくともその
上面が保護膜で被覆されているので、積層配線化に有利
である。すなわち、第1の金属膜と第2の金属膜とから
なる本構造の配線層を層間絶縁膜を介して積層するなど
して、各配線層にコンタクトする接続配線用の深さの異
なるコンタクトホールを形成する際に、上記保護膜がエ
ッチングストッパ膜として使用することができるので、
異なる深さのコンタクトホールを一度に形成できる。
Further, since at least the upper surface of the second metal film is covered with the protective film, it is advantageous for forming a laminated wiring. That is, by forming a wiring layer of the present structure composed of a first metal film and a second metal film with an interlayer insulating film interposed, for example, contact holes with different depths for connecting wirings that contact each wiring layer. Since the protective film can be used as an etching stopper film when forming
Contact holes with different depths can be formed at once.

【0022】また、本発明者等の研究によれば、第1の
金属膜と銀を主成分とする第2の金属膜との積層膜にお
いて、第2の金属膜に対する第1の金属膜の金属の拡散
速度は、第1の金属膜の金属と、第2の金属膜の金属と
からなる化合物若しくは合金に対する第1の金属膜の金
属の拡散速度よりも十分速いことが分かった。これは主
として第2の金属膜の粒界等を経由して第1の金属膜の
金属が拡散するためと思われる。
Further, according to the research conducted by the present inventors, in the laminated film of the first metal film and the second metal film containing silver as a main component, the first metal film with respect to the second metal film is It was found that the diffusion rate of the metal was sufficiently higher than the diffusion rate of the metal of the first metal film to the compound or alloy composed of the metal of the first metal film and the metal of the second metal film. This is probably because the metal of the first metal film diffuses mainly via the grain boundaries of the second metal film.

【0023】このため、本発明の半導体装置の製造方法
によれば、熱処理工程において、主配線となる銀を主成
分とする第2の金属膜の表面に、保護膜を形成するのに
十分な量の第1の金属膜中の金属が拡散によって供給さ
れるため、第2の金属膜の表面に保護膜を形成できる。
Therefore, according to the method of manufacturing a semiconductor device of the present invention, in the heat treatment step, it is sufficient to form a protective film on the surface of the second metal film containing silver as the main component, which is the main wiring. Since the amount of the metal in the first metal film is supplied by diffusion, a protective film can be formed on the surface of the second metal film.

【0024】したがって、本発明の半導体装置の製造方
法によれば、配線材料として抵抗値は低いけど凝集を起
こしやすい銀を使用しても、主配線となる第2の金属膜
に形成される保護膜により、第2の金属膜の銀の凝集を
抑制できるので、低抵抗という銀の特性を生かした実用
的な金属配線を得ることができる。また、第1の金属膜
の金属の拡散速度が速いため、銀を主成分とする第2の
金属膜中に第1の金属が残ることは防止され、配線抵抗
を低く抑えることができる。
Therefore, according to the method for manufacturing a semiconductor device of the present invention, even if silver, which has a low resistance value but is prone to agglomeration, is used as the wiring material, the protection formed on the second metal film which becomes the main wiring. Since the film can suppress the aggregation of silver in the second metal film, it is possible to obtain a practical metal wiring that takes advantage of the characteristic of silver, which is low resistance. Further, since the metal diffusion rate of the first metal film is high, the first metal is prevented from remaining in the second metal film containing silver as a main component, and the wiring resistance can be suppressed low.

【0025】更に、第1の金属膜および第2の金属膜を
溝内に形成すれば、溝上部の第2の金属膜の上面部分に
選択的に十分な量の第1の金属膜中の金属を供給できる
ので、第2の金属膜の上面部分に選択的に保護膜を形成
できる。
Further, if the first metal film and the second metal film are formed in the groove, a sufficient amount of the first metal film in the upper surface portion of the second metal film above the groove can be selectively formed. Since the metal can be supplied, the protective film can be selectively formed on the upper surface portion of the second metal film.

【0026】したがって、図9に示した従来技術のよう
に、配線層を保護膜で覆うというプロセスに比べて、簡
単なプロセスで済む。
Therefore, as compared with the conventional technique shown in FIG. 9 in which a wiring layer is covered with a protective film, a simpler process is required.

【0027】[0027]

【実施例】以下、図面を参照しながら実施例を説明す
る。
Embodiments will be described below with reference to the drawings.

【0028】図1は、本発明の一実施例に係る埋込みA
g配線の形成方法を示す工程断面図である。また、図1
1〜図13は実際に形成された形状の断面構造を示すS
EM写真で、図11〜図13はそれぞれ図1(a)〜
(c)に対応している。
FIG. 1 shows an embedding A according to an embodiment of the present invention.
FIG. 6 is a process cross-sectional view showing the method for forming the g-wiring. Also, FIG.
1 to 13 show S showing a sectional structure of an actually formed shape.
11 to 13 are EM photographs, and FIG. 11 to FIG.
It corresponds to (c).

【0029】まず、図1(a)に示すように、シリコン
基板1上にSiO2 膜2を形成し、このSiO2 膜2に
埋込み配線用の溝を形成する。ここでは、絶縁膜として
SiO2 膜2を用いたが、他の絶縁膜、例えば、ポリイ
ミド膜を用いても良い。
First, as shown in FIG. 1A, a SiO 2 film 2 is formed on a silicon substrate 1, and a groove for a buried wiring is formed in the SiO 2 film 2. Although the SiO 2 film 2 is used as the insulating film here, another insulating film, for example, a polyimide film may be used.

【0030】次いで拡散バリア膜として厚さ70nmの
TiN膜3を形成する。このTiN膜3の成膜は、例え
ば、スパッタ法により行ない、その条件は、例えば、ス
パッタ時圧力10-1Pa、Ar/N2 比50/50%、
残留O2 濃度約10ppm以下、電流5Aとする。この
後、600℃の温度の熱処理によってTiN膜3をデン
シファイする。
Next, a TiN film 3 having a thickness of 70 nm is formed as a diffusion barrier film. The TiN film 3 is formed by, for example, a sputtering method under the following conditions: sputter pressure 10 −1 Pa, Ar / N 2 ratio 50/50%,
The residual O 2 concentration is about 10 ppm or less, and the current is 5A. After that, the TiN film 3 is densified by a heat treatment at a temperature of 600 ° C.

【0031】次いでTiN膜3上に厚さ50nmのTi
膜4(第1の金属膜)、厚さ400nmのAg膜5(第
2の金属膜)を順次形成する。Ti膜4,Ag膜5の成
膜は、例えば、スパッタ法により行ない、その条件は、
例えば、スパッタ時圧力10-1Pa、Ar100%、残
留O2 濃度約10ppm以下(Ti膜4,Ag膜5に共
通)、1.5A(Ti膜4)、1kW(Ag膜5)とす
る。それぞれのスパッタ工程は真空を破らず連続的に行
なうことが好ましい次に図1(b)に示すように、Ag
膜5を平坦化する。この平坦化は、Ag膜5をスパッタ
法により成膜する場合には、例えば、Ag膜5のスパッ
タ成膜中或いは成膜後に400℃のアニールを行なっ
て、Ag膜5をリフローし、平坦化する。
Next, a Ti film having a thickness of 50 nm is formed on the TiN film 3.
The film 4 (first metal film) and the Ag film 5 (second metal film) having a thickness of 400 nm are sequentially formed. The Ti film 4 and the Ag film 5 are formed by, for example, a sputtering method under the following conditions.
For example, the sputtering pressure is 10 −1 Pa, Ar 100%, residual O 2 concentration is about 10 ppm or less (common to Ti film 4 and Ag film 5), 1.5 A (Ti film 4), 1 kW (Ag film 5). It is preferable that each of the sputtering steps be continuously performed without breaking the vacuum. Next, as shown in FIG.
The film 5 is flattened. When the Ag film 5 is formed by a sputtering method, this flattening is performed by, for example, annealing at 400 ° C. during or after the Ag film 5 is formed by sputtering to reflow the Ag film 5 for flattening. To do.

【0032】次に図1(c)に示すように、溝部以外の
TiN膜3、Ti膜4、Ag膜5を除去して埋込みAg
配線層を形成する。これらTiN膜3、Ti膜4、Ag
膜5の除去は、ウエットエッチング,RIE,イオンミ
リング,研磨等により行なう。具体的には、ウエットエ
ッチングの場合には希硝酸溶液を用い、研磨の場合には
研磨材としてアルミナ若しくはシリカを用いる。
Next, as shown in FIG. 1C, the TiN film 3, the Ti film 4, and the Ag film 5 other than the groove are removed and the embedded Ag is removed.
A wiring layer is formed. These TiN film 3, Ti film 4, Ag
The film 5 is removed by wet etching, RIE, ion milling, polishing or the like. Specifically, a dilute nitric acid solution is used for wet etching, and alumina or silica is used as an abrasive for polishing.

【0033】ここでは、表面が平坦になるようにAg膜
5を除去したが、Ag膜5が溝表面の下になるようにし
ても良い。更に、後工程で溝部以外のTiN膜3、Ti
膜4、Ag膜5を除去しても不都合がなければ、本工程
で溝部以外のTiN膜3、Ti膜4、Ag膜5を残して
おいても良い。
Here, the Ag film 5 is removed so that the surface becomes flat, but the Ag film 5 may be located below the groove surface. Further, TiN film 3 other than the groove portion, Ti
If there is no problem even if the film 4 and the Ag film 5 are removed, the TiN film 3, the Ti film 4, and the Ag film 5 other than the groove may be left in this step.

【0034】この後、シリコン基板1をアニール用処理
室に搬入し、このアニール用処理室内を10-6Torr
以下の真空まで減圧する。
After that, the silicon substrate 1 is loaded into the annealing treatment chamber, and the annealing treatment chamber is set to 10 -6 Torr.
Reduce the pressure to the following vacuum.

【0035】次に図1(c)に示すように、O2 (所定
元素)を含む希ガス、例えば、Arガスを導入し、この
Arガス雰囲気中で600℃の温度で30分間アニール
を行ない、Ag膜5の上面にTiO2 膜6を形成する。
このアニール工程において、上記O2 の分圧は10-10
Torr以上、Arは常圧とする。このとき、図14
(c)に示すように、TiがAg膜5の表面まで拡散し
ていることが分かる。また、Ag膜5の上面部分のXP
Sスペクトルを求めたところ、図2に示すような結果が
得られ、Ag膜5の上面部分にはTiO2 膜6が形成さ
れていることを確認できた。
Next, as shown in FIG. 1C, a rare gas containing O 2 (predetermined element), for example, Ar gas is introduced, and annealing is performed in this Ar gas atmosphere at a temperature of 600 ° C. for 30 minutes. A TiO 2 film 6 is formed on the upper surface of the Ag film 5.
In this annealing step, the partial pressure of O 2 is 10 −10.
At or above Torr, Ar is at normal pressure. At this time, FIG.
As shown in (c), it can be seen that Ti has diffused to the surface of the Ag film 5. In addition, XP on the upper surface of the Ag film 5
When the S spectrum was obtained, the results shown in FIG. 2 were obtained, and it was confirmed that the TiO 2 film 6 was formed on the upper surface of the Ag film 5.

【0036】上記アニール工程でAg膜5の上面部分に
TiO2 膜6が形成されるのは、Ti膜4中のTiがA
g膜5中を拡散してAg膜5の表面に達し、この表面に
達したTiが雰囲気中のO2 と反応するからだと考えら
れる。
In the annealing process, the TiO 2 film 6 is formed on the upper surface of the Ag film 5 because the Ti in the Ti film 4 is A
It is considered that this is because it diffuses in the g film 5 and reaches the surface of the Ag film 5, and Ti reaching the surface reacts with O 2 in the atmosphere.

【0037】しかも、Ag膜5に対するTiの拡散速度
は、AgとTiとの化合物若しくは合金に対するTiの
拡散速度よりも十分速いので、本実施例のように拡散層
内の不純物の再拡散を防止できる600℃の低温度のア
ニールでも、保護膜の成膜に必要な量のTiをAg膜5
の表面に供給できる。
Moreover, since the diffusion rate of Ti into the Ag film 5 is sufficiently higher than the diffusion rate of Ti into the compound or alloy of Ag and Ti, re-diffusion of impurities in the diffusion layer is prevented as in this embodiment. Even if it is possible to anneal at a low temperature of 600 ° C., the amount of Ti necessary for forming the protective film can be reduced to the Ag film
Can be supplied to the surface.

【0038】図4は、AgとTiとからなる膜に対する
Tiの拡散速度が遅いことを示す図で、具体的には、ア
ニール前後におけるAgとTiとの化合物若しくは合金
のシート抵抗の変化を示す図である。ここで、膜厚は4
00nmである。
FIG. 4 is a diagram showing that the diffusion rate of Ti into the film composed of Ag and Ti is slow. Specifically, it shows the change in the sheet resistance of the compound or alloy of Ag and Ti before and after annealing. It is a figure. Here, the film thickness is 4
00 nm.

【0039】アニール前(曲線a)とアニール後(曲線
b)とでは、シート抵抗はあまり変わらず、アニールを
行なっても高シート抵抗のままである。これはTiの拡
散速度が遅く、Ag膜5とTi膜4との積層膜の場合の
ように、表面にTiが集まらず、AgとTiとの化合物
若しくは合金中に多くのTiが残るためである。
Before annealing (curve a) and after annealing (curve b), the sheet resistance does not change much, and the sheet resistance remains high even after annealing. This is because the diffusion rate of Ti is slow and, as in the case of the laminated film of the Ag film 5 and the Ti film 4, Ti does not collect on the surface and much Ti remains in the compound or alloy of Ag and Ti. is there.

【0040】これはAgとTiとの化合物若しくは合金
の場合、Tiの拡散タイプが拡散速度の遅い体拡散であ
るのに対し、Ag膜5とTi膜4との積層膜の場合、T
iの拡散タイプが拡散速度の速い粒界拡散であることに
起因している。
In the case of a compound or alloy of Ag and Ti, the diffusion type of Ti is body diffusion with a slow diffusion rate, whereas in the case of a laminated film of Ag film 5 and Ti film 4, T
This is because the diffusion type of i is grain boundary diffusion with a high diffusion rate.

【0041】ここで、750℃より高い温度でアニール
すると、図14(d)に示すように、AgとTiとが反
応し、空胴が発生するため、信頼性の低下を防止するに
は、上記アニールを750℃以下で行なう必要がある。
また、450℃より低い温度でアニールすると、図14
(b)に示すように、Ag膜5の表面にまでTiが拡散
せず、TiO2 膜6を形成できないので、TiO2 膜6
を確実に形成するには、上記アニールを450℃以上で
行なう必要がある。なお、図14(a)はAg膜5のス
パッタ堆積直後を示している。
Here, when annealing is performed at a temperature higher than 750 ° C., Ag reacts with Ti as shown in FIG. It is necessary to perform the above annealing at 750 ° C. or lower.
In addition, when annealing is performed at a temperature lower than 450 ° C., FIG.
As shown in (b), Ti is not diffused to the surface of the Ag film 5, it can not form a TiO 2 film 6, a TiO 2 film 6
In order to surely form the above, it is necessary to perform the annealing at 450 ° C. or higher. Note that FIG. 14A shows the Ag film 5 immediately after the sputter deposition.

【0042】したがって、TiO2 膜6を形成するに
は、450℃以上750℃以下の温度のアニールを行な
う必要がある。また、特に本実施例のように600℃程
度の低温度のアニールであれば、拡散層内の不純物の再
拡散はより効果的に抑制され、素子の劣化を防止でき
る。
Therefore, in order to form the TiO 2 film 6, it is necessary to anneal at a temperature of 450 ° C. or higher and 750 ° C. or lower. In particular, if annealing is performed at a low temperature of about 600 ° C. as in this embodiment, re-diffusion of impurities in the diffusion layer can be suppressed more effectively, and deterioration of the element can be prevented.

【0043】図15(a)は大気中でアニールを行なっ
た場合のAg膜の表面を示し、図15(b)は本実施例
の大気中でアニールを行なったAg膜の表面を示してい
る。図15から保護膜であるTiO2 膜6の存在によっ
て、Agの凝集が抑制され良好なAg配線層が形成され
ていることが分かる。また、TiO2 膜6はAgに対し
て拡散バリア膜として機能するので、Ag膜5中のAg
が後工程でSiO2 膜12上に形成される膜中に拡散す
るのを防止できる。
FIG. 15A shows the surface of the Ag film when annealed in the air, and FIG. 15B shows the surface of the Ag film annealed in the air of this embodiment. . It can be seen from FIG. 15 that the presence of the TiO 2 film 6, which is a protective film, suppresses Ag aggregation and forms a good Ag wiring layer. Further, since the TiO 2 film 6 functions as a diffusion barrier film against Ag, the Ag in the Ag film 5 is
Can be prevented from diffusing into the film formed on the SiO 2 film 12 in a later step.

【0044】また、本実施例の方法に従って作成した試
料(SiO2 膜,Ti膜,Ag膜,TiO2 膜の積層
膜)のRBSスペクトルを求めたところ、図3に示すよ
うに、Ag膜中のTiは検出限界(1atom%)以下であ
ることが分かった。
Further, when the RBS spectrum of the sample (a laminated film of SiO 2 film, Ti film, Ag film, and TiO 2 film) prepared according to the method of this embodiment was obtained, as shown in FIG. Was found to be below the detection limit (1 atom%).

【0045】図5は、本実施例の方法に従って作成した
Ag配線(曲線d)のエレクトロマイグレーション耐性
を示す図である。
FIG. 5 is a diagram showing the electromigration resistance of the Ag wiring (curve d) produced according to the method of this embodiment.

【0046】これはAg配線に1.6×107 A/cm
2 の電流を流し、電流を流す前後の抵抗値の変化(電流
を流した後の抵抗値/電流を流す前の抵抗値)を示して
いる。また、図5中、曲線cは比較例を示し、Ag配線
をTiO2 膜で被覆していない場合の抵抗値変化を示し
ている。
This is 1.6 × 10 7 A / cm for Ag wiring.
2 shows the change in the resistance value before and after the current is applied and the current is applied (the resistance value after the current is applied / the resistance value before the current is applied). Further, in FIG. 5, a curve c shows a comparative example, and shows a change in resistance value when the Ag wiring is not covered with the TiO 2 film.

【0047】この図5から本実施例のAg配線の場合に
は、電流を流してから103 秒以上経ってから急激に抵
抗変化率が大きくなり断線が発生するのに対して、比較
例の場合には、数秒後に抵抗変化率が急激に大きくなり
断線が発生していることが分かる。この結果から本実施
例のAg配線は非常にエレクトロマイグレーション耐性
に優れたものであることが分かる。
[0047] The present embodiment from FIG. 5 in the case of the Ag wiring, whereas the disconnection increases sharply resistance change ratio at a later since flowing a current 10 3 seconds or more occurs, the comparative examples In some cases, it can be seen that the resistance change rate suddenly increased after a few seconds and a wire break occurred. From this result, it can be seen that the Ag wiring of this example has a very excellent electromigration resistance.

【0048】最後に、図1(d)に示すように、全面に
例えばPSG等の層間絶縁膜7を堆積して埋込み配線工
程が終了する。
Finally, as shown in FIG. 1D, an interlayer insulating film 7 such as PSG is deposited on the entire surface, and the buried wiring process is completed.

【0049】以上述べたように、本実施例のAg配線の
形成方法によれば、拡散層内の不純物の再拡散を招かな
い温度のアニールにより、Ag膜5の表面にAgの凝集
を防止するためのTiO2 膜6を形成できる。したがっ
て、素子の劣化や信頼性の低下を招かずに、埋込みAg
配線が得られる。しかも、上記アニールによってもAg
膜5中にはほとんどTiは残留しないので、Agの低抵
抗性を損なうこともない。更に、Ag膜5の上面部分に
選択的にTiO2 膜6を形成できるので、図9に示した
従来技術のように、配線層を保護膜で覆うというプロセ
スに比べて、簡単なプロセスで済む。
As described above, according to the Ag wiring forming method of the present embodiment, Ag is prevented from aggregating on the surface of the Ag film 5 by annealing at a temperature that does not cause re-diffusion of impurities in the diffusion layer. Therefore, the TiO 2 film 6 can be formed. Therefore, the embedded Ag is prevented from deteriorating the element and reducing the reliability.
Wiring is obtained. Moreover, even if the above annealing is performed, Ag
Since almost no Ti remains in the film 5, the low resistance of Ag is not impaired. Further, since the TiO 2 film 6 can be selectively formed on the upper surface of the Ag film 5, a simple process is required as compared with the process of covering the wiring layer with the protective film as in the conventional technique shown in FIG. .

【0050】なお、本実施例ではArとO2 とを含むガ
ス雰囲気中でアニールを行なったが、その代わりに窒素
ガス雰囲気でのアニールによって、Ag膜5の表面を窒
化し、TiO2 膜6の代わりにTiN膜を形成しても、
TiO2 膜6と同様に良好な凝集耐性、拡散耐性が得ら
れた。
In the present embodiment, the annealing was performed in a gas atmosphere containing Ar and O 2 , but instead, the surface of the Ag film 5 was nitrided by annealing in a nitrogen gas atmosphere, and the TiO 2 film 6 was formed. If a TiN film is formed instead of
Similar to the TiO 2 film 6, good cohesion resistance and diffusion resistance were obtained.

【0051】ところで、比較のため、上記方法をCu
(400nm)/Ti(50nm)積層膜にも適用して
みた。図7は、このCu/Ti積層膜についてのアニー
ル温度とCu膜のシート抵抗との関係を示す特性図であ
る。なお、アニール時間は30分で、雰囲気はO2 を含
むArガス雰囲気である。
By the way, for comparison, the above method is applied to Cu.
It was also applied to a (400 nm) / Ti (50 nm) laminated film. FIG. 7 is a characteristic diagram showing the relationship between the annealing temperature and the sheet resistance of the Cu film for this Cu / Ti laminated film. The annealing time is 30 minutes and the atmosphere is an Ar gas atmosphere containing O 2 .

【0052】Cuの場合、図7から600℃程度以上シ
ート抵抗値は約100以上になってしまうが、Ag(4
00nm)/Ti(50nm)積層膜の場合、図6から
450℃以上の温度でシート抵抗値が約53以下とな
る。このようにCuの場合、シート抵抗が高くなるの
は、Ag膜に比べて、Cu膜中にTiが残り易く、この
残ったTiのために不純物による抵抗増大が生じている
からだと考えられる。特に600℃程度の温度から拡散
等が進み、保護膜が形成され始まるので、この効果が大
きくなる。
In the case of Cu, the sheet resistance value of about 600 ° C. or more becomes about 100 or more as shown in FIG. 7, but Ag (4
In the case of a (00 nm) / Ti (50 nm) laminated film, the sheet resistance value is about 53 or less at a temperature of 450 ° C. or more from FIG. It is considered that the reason why the sheet resistance is high in the case of Cu is that Ti is more likely to remain in the Cu film than in the case of the Ag film, and the resistance increases due to impurities due to the remaining Ti. In particular, since the diffusion and the like proceed from a temperature of about 600 ° C. and a protective film starts to be formed, this effect becomes large.

【0053】図8は、本発明の他の実施例に係る埋込み
Ag配線構造を示す図である。これは本発明を積層配線
に適用した例である。
FIG. 8 is a view showing a buried Ag wiring structure according to another embodiment of the present invention. This is an example in which the present invention is applied to laminated wiring.

【0054】これを形成工程に従い説明すると、まず、
シリコン基板1上にSiO2 膜2を形成した後、先の実
施例と同様に、TiN膜3,Ti膜4,Ag膜5および
TiO2 膜6,層間絶縁膜7を形成する。
This will be described according to the forming process. First,
After forming the SiO 2 film 2 on the silicon substrate 1, the TiN film 3, the Ti film 4, the Ag film 5 and the TiO 2 film 6, and the interlayer insulating film 7 are formed as in the previous embodiment.

【0055】次に層間絶縁膜7の表面に埋込み配線用の
溝を形成した後、TiN膜3,Ti膜4,Ag膜5およ
びTiO2 膜6の場合と同様な方法により、TiN膜3
a,Ti膜4a,Ag膜5aおよびTiO2 膜6aを形
成する。
Next, after a groove for a buried wiring is formed on the surface of the interlayer insulating film 7, the TiN film 3 is formed by the same method as that of the TiN film 3, the Ti film 4, the Ag film 5 and the TiO 2 film 6.
a, a Ti film 4a, an Ag film 5a and a TiO 2 film 6a are formed.

【0056】次に全面に層間絶縁膜8を堆積した後、T
iO2 膜6,TiO2 膜6aをエッチングストッパ膜と
して用い、これらTiO2 膜6,TiO2 膜6aが露出
するまで、層間絶縁膜7,8をエッチングする。このよ
うに層間絶縁膜8の表面からTiO2 膜6,TiO2
6aまでのそれぞれの距離が異なっていも、TiO2
6,TiO2 膜6aがエッチングストッパ膜として機能
するので、深さが異なる二つの溝を同時に形成できる。
Next, after depositing an interlayer insulating film 8 on the entire surface, T
Using the TiO 2 film 6 and the TiO 2 film 6a as etching stopper films, the interlayer insulating films 7 and 8 are etched until the TiO 2 film 6 and the TiO 2 film 6a are exposed. As described above, even if the distances from the surface of the interlayer insulating film 8 to the TiO 2 film 6 and the TiO 2 film 6a are different, since the TiO 2 film 6 and the TiO 2 film 6a function as an etching stopper film, the depth is Two different grooves can be formed at the same time.

【0057】最後に、溝内のTiO2 膜6,TiO2
6aを除去した後、接続配線7,7aを形成する。
Finally, after removing the TiO 2 film 6 and the TiO 2 film 6a in the groove, connection wirings 7 and 7a are formed.

【0058】かくして本実施例によれば、深さの異なる
コンタクトホールを同時に形成できるので、低抵抗で高
信頼の多層埋込みAg配線を簡単な工程で形成できる。
Thus, according to the present embodiment, since contact holes having different depths can be formed at the same time, it is possible to form a highly reliable multi-layered buried Ag wiring in a simple process.

【0059】なお、本発明は上述した実施例に限定され
るものではない。例えば、上記実施例では、埋込み配線
の場合について説明したが他の構造の配線にも適用でき
る。
The present invention is not limited to the above embodiment. For example, in the above embodiment, the case of the buried wiring has been described, but the present invention can be applied to the wiring of other structures.

【0060】また、上記実施例では、保護膜となる材料
としてTiを用いたが他の材料、例えば、Si,In,
Nb,Pb,Sb,Sn,Mg,Al,Cr,Be,Z
rを用いても良い。すなわち、上記実施例では、Agと
Tiとの組み合わせについて述べたが、要は配線層中に
保護膜となる物質が残らなければ、他の物質の組み合わ
せでも良い。
Although Ti is used as the material for the protective film in the above embodiment, other materials such as Si, In,
Nb, Pb, Sb, Sn, Mg, Al, Cr, Be, Z
You may use r. That is, in the above embodiment, the combination of Ag and Ti has been described, but the point is that other substances may be combined as long as the substance to be the protective film does not remain in the wiring layer.

【0061】その他、本発明の要旨を逸脱しない範囲
で、種々変形して実施できる。
In addition, various modifications can be made without departing from the scope of the present invention.

【0062】[0062]

【発明の効果】以上詳述したように本発明によればAg
膜中のAgの凝集を抑制できるので、低抵抗であるが凝
集が起こり易いため、現在までほとんど配線材料として
検討されていなかったAgを使用できるようになり、A
gの低抵抗性を生かした配線が得られる。
As described above in detail, according to the present invention, Ag
Since aggregation of Ag in the film can be suppressed, it has a low resistance but easily aggregates. Therefore, Ag, which has not been considered as a wiring material until now, can be used.
A wiring that takes advantage of the low resistance of g can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係わる埋込みAg配線の形
成方法を示す工程断面図。
FIG. 1 is a process cross-sectional view showing a method of forming a buried Ag wiring according to an embodiment of the present invention.

【図2】Ag膜の上面部分にTiO2 膜が形成されてい
ることを示すXPSスペクトル。
FIG. 2 is an XPS spectrum showing that a TiO 2 film is formed on the upper surface of the Ag film.

【図3】Ag膜中にTiが残っていないことを示すRB
Sスペクトル。
FIG. 3 is an RB showing that no Ti remains in the Ag film.
S spectrum.

【図4】AgとTiとの化合物に本発明の熱処理(アニ
ール)が有効でないことを表す熱処理前後のシート抵抗
の変化を示す図。
FIG. 4 is a diagram showing changes in sheet resistance before and after heat treatment, which shows that the heat treatment (annealing) of the present invention is not effective for a compound of Ag and Ti.

【図5】本発明によるエレクトロマイグレーション耐性
の向上を示す抵抗変化率と時間との関係を示す図。
FIG. 5 is a diagram showing a relationship between a rate of change in resistance and time showing improvement in electromigration resistance according to the present invention.

【図6】Agについてのアニール温度とシート抵抗との
関係を示す特性図。
FIG. 6 is a characteristic diagram showing the relationship between annealing temperature and sheet resistance for Ag.

【図7】Cuについてのアニール温度とシート抵抗との
関係を示す特性図。
FIG. 7 is a characteristic diagram showing the relationship between the annealing temperature and sheet resistance of Cu.

【図8】本発明の他の実施例に係る埋込みAg配線構造
を示す図。
FIG. 8 is a diagram showing a buried Ag wiring structure according to another embodiment of the present invention.

【図9】従来のCu配線の形成方法を示す工程断面図。FIG. 9 is a process cross-sectional view showing a conventional Cu wiring forming method.

【図10】従来の他のCu配線の形成方法を示す工程断
面図。
FIG. 10 is a process cross-sectional view showing another conventional Cu wiring forming method.

【図11】基板上に形成された微細パターンを表す写
真。
FIG. 11 is a photograph showing a fine pattern formed on a substrate.

【図12】基板上に形成された微細パターンを表す写
真。
FIG. 12 is a photograph showing a fine pattern formed on a substrate.

【図13】基板上に形成された微細パターンを表す写
真。
FIG. 13 is a photograph showing a fine pattern formed on a substrate.

【図14】基板上に形成された微細パターンを表す写
真。
FIG. 14 is a photograph showing a fine pattern formed on a substrate.

【図15】基板上に形成された微細パターンを表す写
真。
FIG. 15 is a photograph showing a fine pattern formed on a substrate.

【符号の説明】[Explanation of symbols]

1…シリコン基板 2…SiO2 膜 3,3a…TiN膜 4,4a…Ti膜(第1の金属膜) 5,5a…Ag膜(第2の金属膜) 6,6a…TiO2 膜 7,8…層間絶縁膜 81…シリコン基板 82…SiO2 膜 83,86,87…Ti膜 84…TiN膜84 85…Cu膜 91…絶縁膜 92…拡散バリアメタル膜 93…Cu・Ti合金膜 94…TiN膜 95…Cu配線1 ... Silicon substrate 2 ... SiO 2 film 3, 3a ... TiN film 4, 4a ... Ti film (first metal film) 5, 5a ... Ag film (second metal film) 6, 6a ... TiO 2 film 7, 8 ... Interlayer insulating film 81 ... Silicon substrate 82 ... SiO 2 film 83, 86, 87 ... Ti film 84 ... TiN film 84 85 ... Cu film 91 ... Insulating film 92 ... Diffusion barrier metal film 93 ... Cu.Ti alloy film 94 ... TiN film 95 ... Cu wiring

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に形成された第1の金属膜
と、 この第1の金属膜上に形成された銀を主成分とする第2
の金属膜と、 この第2の金属膜の少なくとも上面を被覆し、前記第1
の金属膜の金属元素を含む保護膜とを具備してなること
を特徴とする半導体装置。
1. A first metal film formed on a semiconductor substrate, and a second metal film containing silver as a main component formed on the first metal film.
And a metal film of at least the upper surface of the second metal film,
And a protective film containing a metal element of the metal film of.
【請求項2】半導体基板上に第1の金属膜を形成する工
程と、 この第1の金属膜上に銀を主成分とする第2の金属膜を
形成する工程と、 所定元素が含まれるガス雰囲気中の熱処理によって、前
記第1の金属膜中の一部の金属を前記第2の金属膜の表
面まで拡散させ、前記所定元素と前記第1の金属膜中の
一部の金属とからなる保護膜を前記第2の金属膜の表面
に形成する工程とを有することを特徴とする半導体装置
の製造方法。
2. A step of forming a first metal film on a semiconductor substrate, a step of forming a second metal film containing silver as a main component on the first metal film, and including a predetermined element. By heat treatment in a gas atmosphere, a part of the metal in the first metal film is diffused to the surface of the second metal film, and the predetermined element and the part of the metal in the first metal film are separated from each other. Forming a protective film formed on the surface of the second metal film, the manufacturing method of the semiconductor device.
【請求項3】前記第1の金属膜はチタンからなることを
特徴する請求項2に記載の半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 2, wherein the first metal film is made of titanium.
【請求項4】前記熱処理の温度が450℃以上750℃
以下であることを特徴する請求項3に記載の半導体装置
の製造方法。
4. The temperature of the heat treatment is 450 ° C. or higher and 750 ° C.
The method for manufacturing a semiconductor device according to claim 3, wherein:
JP13539893A 1993-01-05 1993-05-13 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3283965B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP13539893A JP3283965B2 (en) 1993-05-13 1993-05-13 Semiconductor device and manufacturing method thereof
DE4447597A DE4447597B4 (en) 1993-01-05 1994-01-05 Semiconductor device with improved wiring structure - comprises first metal foil on substrate, second metal foil contg. silver and a third foil layer of similar material to the first layer
DE4400200A DE4400200C2 (en) 1993-01-05 1994-01-05 Semiconductor device with improved wiring structure and method of manufacturing the same
US08/480,733 US5529954A (en) 1993-01-05 1995-06-07 Method of diffusing a metal through a silver electrode to form a protective film on the surface of the electrode
US08/588,511 US5763953A (en) 1993-01-05 1996-01-18 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13539893A JP3283965B2 (en) 1993-05-13 1993-05-13 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH06326102A true JPH06326102A (en) 1994-11-25
JP3283965B2 JP3283965B2 (en) 2002-05-20

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP13539893A Expired - Fee Related JP3283965B2 (en) 1993-01-05 1993-05-13 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3283965B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09186103A (en) * 1995-12-26 1997-07-15 Lg Semicon Co Ltd Structure of metal interconnection and forming method thereof
KR100373297B1 (en) * 1996-07-12 2003-02-25 가부시끼가이샤 도시바 Semiconductor device and method of manufacturing the same
JP2012156532A (en) * 2012-03-23 2012-08-16 Toshiba Corp Method for manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09186103A (en) * 1995-12-26 1997-07-15 Lg Semicon Co Ltd Structure of metal interconnection and forming method thereof
KR100373297B1 (en) * 1996-07-12 2003-02-25 가부시끼가이샤 도시바 Semiconductor device and method of manufacturing the same
JP2012156532A (en) * 2012-03-23 2012-08-16 Toshiba Corp Method for manufacturing semiconductor device

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