JPH06318958A - Method for digital data signal transmission - Google Patents

Abstract

PURPOSE: To suppress the generation of crosstalk to be a fault and to make avoidable the limitation of a line length to data transmission by transmitting signals with frequency with is one-half in the same array pattern as data signals as clock signals. CONSTITUTION: Clock signals T and the data signals D are supplied through input lines 5 and 6 to a coder 1 and new clock signals T' provided with half the frequency are led out from the clock signals T in the coder 1. After the transmission of a line 3, they are reproduced to the original clock signals T in a decoder 2 and the clock signals T and the data signals D are taken out by output lines 7 and 8. That is, in the case that a data rate is high, by reducing the frequency of the clock signals T to be transmitted, the limitation of the line length by dispersion or attenuation rapidly rising in the case that the frequency is high is avoided. Similarly, by shifting a clock edge to the time for changing data, the crosstalk of the clock signals T' to the data signals D is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for transmitting a digital data signal having an arbitrary word width and transmitting another synchronous clock signal in parallel therewith.

[0002]

2. Description of the Related Art It is already known to supply synchronous clock signals in parallel on separate lines or pairs of lines for digital data signals of arbitrary word width (European Patent 0364170 A2). In the case of a fault-free transmission, this makes it possible to reproduce the data very easily, so that no dedicated channel or line code is required. However, this known method has the following drawbacks. That is, there is a possibility of crosstalk which is an obstacle to the data signal due to the clock edge occurring during the transmission of the data word.

[0003]

SUMMARY OF THE INVENTION The object of the present invention is to reduce the occurrence of disturbing crosstalk and to increase the maximum possible line length for data transmission in a method such as the one mentioned at the outset. Is.

[0004]

According to the present invention, the above problem is solved by transmitting a signal having a half frequency with the same arrangement pattern of data signals as a clock signal.

The method of the invention according to the characterizing part of claim 1 has the following advantages. That is, when the data rate is high, the frequency of the clock signal to be transmitted is reduced (halved) by a factor of 2 to avoid the limitation of the line length due to attenuation or dispersion that sharply increases when the frequency is high. To be done. Similarly, shifting the clock edge to the time when the data change occurs has the advantage that crosstalk of the clock signal into the data signal is significantly reduced.

Further advantageous embodiments of the invention are specified in the dependent claims.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings.

In the block diagram for carrying out the method of the invention shown in FIG. 1, a coder 1 and a decoder 2 are shown, these two via two lines of arbitrary length. Are directly connected to each other. The coder 1 is supplied with the clock signal T or the data signal D in a known manner via separate input lines 5 and 6. In coder 1 (this circuit is described in detail in connection with FIG. 3), the clock signal T
From this, a new clock signal T'with a double clock period or half the frequency is derived. After transmission via line 3, the original clock signal T is regenerated in the decoder 2 (this circuit is explained in detail in connection with FIG. 4).
The clock signal T and the data signal D are taken out from the output lines 7 and 8. The clock signal T and the data signal D correspond to the input signals on the lines 5 and 6.

FIG. 2a shows a data signal D for a conventional transmission method, as well as a clock signal T directly adapted to the data. In this case, as you can easily see from the figure,
The data signal D to which the edge of the clock signal T belongs each time
It occurs in the center of the data word of. However, this is a drawback that the clock signal T cross-talks to the data signal D mentioned at the beginning.

This drawback is avoided by the approach shown in FIG. 2b and the new clock signal T'arrangement for the data signal D in the transmission method of the invention. In this case, the new clock signal T'has its frequency halved or its period period doubled, so that the edges of the clock signal T'coincide with the corresponding edges of the data signal in time. Be shifted. As a result, crosstalk of the clock signal T'to the data signal D is sufficiently avoided.

The coder 1 shown in FIG. 3 consists essentially of a plurality of storage elements in the form of D-flip-flops 11 and 12. The D-flip-flop 11 is connected as a frequency divider for halving the frequency of the clock signal T by a method known per se. As a result, the output 13 of the D-flip-flop 11 can take out a new clock signal T'of half the frequency. As a result, the new clock signal T'is located in time in the arrangement pattern of the data signal D, and similarly, the data signals Do to Dn-1 are passed through the storage element, that is, the D-flip-flop 12. Supplied. As a result, at the output 14 the data signals Do to Dn are delayed in time, but coincident with the new clock signal T '.
Up to -1 can be taken.

A circuit for recovering the original clock signal T for further processing of the data signal D is shown in FIG. In this case, a modified clock signal T'is applied to the input 16, which on the one hand is supplied to the first input of the EX-OR circuit 17 and, on the other hand, to the delay line 18 '. Is supplied to the second input side of this EX-OR circuit 17. The delay achieved by the delay time line 18 corresponds to half the duration of a data word of the data signal D. As a result, the original clock signal T can be taken out at the output 19 of the circuit 17.

[0013]

According to the present invention, when the data rate is high, the frequency of the clock signal to be transmitted is reduced by a factor of 2, so that the line length due to the attenuation or dispersion that rises sharply when the frequency is high. The restrictions are bypassed. Similarly, by shifting the clock edge to the time when data exchange takes place, crosstalk of the clock signal into the data signal is greatly reduced.

[Brief description of drawings]

FIG. 1 is a block circuit diagram for implementing the method of the present invention.

FIG. 2A is a data signal and a clock signal according to a conventional transmission method. b is a data signal and a clock signal according to the transmission method of the present invention.

FIG. 3 is a circuit diagram for generating a new clock signal.

FIG. 4 is a circuit diagram for reproducing an original clock signal.

[Explanation of symbols]

 1 coder 2 decoder 3 line 4 line 5 input side line 6 input side line 7 output side line 8 output side line 11 D-flip-flop 12 D-flip-flop 13 output side 14 output side 16 input side 17 EX-OR circuit 18 Delay time line 19 Input side

Claims (4)

[Claims] 1. A method for transmitting a digital data signal of arbitrary word width and further transmitting a separate synchronous clock signal in parallel therewith, comprising the same arrangement pattern of a data signal (D) as a clock signal (T). , A method for transmitting a digital data signal, characterized in that it transmits a half frequency signal (T '). 2. The method according to claim 1, wherein the frequency of the clock signal is halved before the transmission and is doubled again for the recovery of the original clock signal after the transmission. 3. The frequency reduction is effected in a known manner by a corresponding data input side control of a storage element clocked by a clock signal (T), and further by a data signal (D).
Are supplied via the same storage element which is correspondingly clocked with the clock signal (T). 4. The frequency multiplication is performed by an exclusive logical operation between a signal delayed by half the word width of the digital data signal (D) and an undelayed signal (T '). Method.