FR2665594A1 - METHOD FOR THE TRANSMISSION OF A DIGITAL DATA SIGNAL OF ANY WIDTH OF ANY WORD. - Google Patents

Abstract

a) Method for transmitting a digital data signal of any word width. b) Method characterized in that, as a clock signal (T), a signal (T ') of half frequency is transmitted in the same frame as the data signal (D). c) The invention relates to a method for transmitting a digital data signal of any word width.

Description

"Method for transmitting a digital data signal, a

  The invention is based on a method for transmitting a digital data signal of any wordwidth and in parallel with a separate synchronous clock signal, as is already known in parallel with a digital signal. data of any word width,

  together transmit a synchronous clock signal on a separate link or on a separate pair of links (EP 0 364 170 A 2) Thus, for a transmission without disturbances, a very simple data recovery is possible, so that a However, this known method has the disadvantage that, due to the flanks of the clock signal intervening during the transmission of the data words, a disturbing crosstalk of the clock signal on the Data signal is possible.

  The object of the present invention is, in the case of the process initially indicated, to reduce

  noticeably disturbing crosstalk and at the same time obtain an increase in the maximum possible link length for data transmission.

  The invention is characterized in that, as a clock signal, a half frequency signal is transmitted in the same frame as the signal

of data.

  The method according to the invention, with the characteristics mentioned above, has the advantage that by reducing, by a factor of 2, the frequency of the clock signal transmitted for high data rates, the limitations of the Because of the high damping at high frequencies, as well as because of the dispersion, the length of the connection is avoided. It is furthermore advantageous if the clock signal flanks are shifted to periods in which they also occur. data changes, the crosstalk of the clock signal on the data signal

be greatly reduced.

  According to another characteristic of the invention, before transmission, the frequency of the clock signal is divided by two, and this frequency is doubled again after transmission.

  to recover the initial clock signal.

  According to another characteristic of the invention, the halving of the frequency is effected, in a manner known per se, by appropriately controlling the data input of a synchronized memory element by the signal of clock, and that the data signals pass through memory elements accordingly

  identical synchronized by the clock signal.

  According to another characteristic of the invention, the doubling of the frequency is effected by exclusive-Or combination of the undelayed signal with the delayed signal of the half-word width of the

digital signal of data.

  An exemplary embodiment of the invention is shown in the attached drawings and will be exposed

  in more detail to the description below:

  FIG. 1 is a block diagram for implementing the method according to the invention, FIG. 2a shows the data signal and the clock signal of known transmission methods, FIG. 2b shows the signal of FIG. data and the clock signal of the transmission method according to the invention, Figure 3 shows a circuit for the production of the new clock signal, Figure 4 shows a circuit for the recovery.

the initial clock signal.

  The block diagram shown in FIG. 1 comprises an encoder 1 and a decoder 2 which are directly connected together via two links 3, 4 of any length to the encoder 1 are fed, in a manner known per se, and by via discrete input links 5 and 6, a clock signal T and / or data signals D In the encoder 1, the circuit of which will be described in more detail with reference to FIG. 3, a new signal Double-period or half-frequency clock T 'is derived from the signal T In the decoder 2, the circuit of which will be described in more detail in connection with FIG. 4, the initial clock signal T is recovered after its transmission by Via the link 3, the clock signal T and the data signals D, which correspond to the input signals on the links 5 and 6, can then be

the links 7 and 8 output.

  FIG. 2a shows a data signal D and a clock signal T directly adapted to the data for a transmission method of conventional type. As can easily be seen in this case, the side of the clock signal T appears each time in the middle of the corresponding data word of the data signal D This however causes the aforementioned drawbacks of the crosstalk of the clock signal T on the data signal D. These drawbacks are avoided with the type and the relative position. to the data signal D of the new clock signal T 'in the transmission method according to the invention In this case the frequency of the new clock signal T' is divided by two and the duration of its period doubled, while that its flanks are offset so that they coincide in time with the corresponding flanks of the data signal. As a result, a crosstalk of the clock signal T 'on the data signal D is in a

largely prevented.

  The encoder 1 represented in FIG. 3 essentially consists of several memory elements in the form of flip-flops D 11 and 12, the flip-flop D 11 being connected, in a manner known per se, to act as a frequency divider in order to to halve the frequency of the clock signal T The new clock signal T 'of frequency half is thus capable of being taken at the output 13 of the flip-flop D 11 So that from now on the new clock signal T' is also in time in the frame of the data signals D, the data signals Do to Dn-1 also pass through

  memory elements, namely flip-flops D 12.

  Thus, the data signals D 1 to D -1 delayed in time, but coinciding with the new clock signal T ', can be taken from

exits 14.

  A circuit enabling the recovery of the initial clock signal T for the subsequent processing of the data signals D is shown in FIG. 4. At the input 16 of this circuit, the modified clock signal T ', which is fed from 1 to a first input of an exclusive circuit Or 17, and secondly to a second input of this circuit 17 via a delay line 18 The delay obtained with this delay line 18 corresponds to half the duration of a data word of the data signal D Thus, the initial clock signal T

  may be taken at exit 19 of circuit 17.

Claims (1)

  A method for transmitting a digital data signal of any word width, and in parallel with a separate synchronous clock signal, characterized in that, as a clock signal (T), a signal (T ') of half frequency is transmitted in the same frame as the signal data (D).   A method according to claim 1, characterized in that prior to transmission the frequency of the clock signal is halved, and this frequency is doubled after transmission to recover the initial clock signal. 30) A method according to claim 2, characterized in that the division by two of the frequency is effected, in a manner known per se, by appropriately controlling the data input of a memory element synchronized by the clock signal (T), and that the data signals (D) pass through correspondingly identical memory elements synchronized by the clock signal. Method according to Claim 2, characterized in that the doubling of the frequency is effected by an exclusive combination of the signal (T ')   not delayed with the signal (T ') delayed by half   word width of the digital data signal (D).