JPS6047213A - System for correcting recording timing - Google Patents

Abstract

PURPOSE:To reduce remarkably a peak shift generated at reproduction of a recording pattern by the constitution that a recording timing correcting amount is to be changed in response to the recording pattern. CONSTITUTION:A shift register 10 inputting a recording timing clock 1 of a code word and a bit serial input data 2 of the code word, and a DA71 inputting each output signal and transmitting a bit serial signal data 3 of the code word whose timing corrected in response to the output signal are provided. The shift register 10 transfers sequentially the data 2 into shift registers in the timing of the clock 1, and a timing correction circuit 15 sets respectively the delay time of delay circuits 21-24 as T21-T24, maximum delay time T21 and minimum delay time T24, i.e., delay times of T21>T22>T23>T24. When the data is a pattern of 00001001, a data 3 is outputted in the slowest timing D2 and when the data is a pattern of 10010000, the data 3 is outputted in the fastest timing (E2).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording timing correction method, and more particularly to a recording timing correction method for correcting a timing shift during reproduction of data recorded on a medium.

In order to achieve high-density recording on magnetic media such as magnetic disk drives, the recording method is to record data between one bit "1" and the next bit "'1" in a magnetic recording code word converted from a data word. at least one bit “0”
There is a method based on self-clockable N RZ I variation that contains (1, 8) or (2,
7) This is a method commonly called run length limited variable length code word recording method (hereinafter abbreviated as 1-8 code or 2-7 code). If the ratio between I'min and the maximum magnetization reversal interval Tmax becomes large, a large pattern peak shift will occur during reproduction of the worst-case recording, and as shown in Fig. 1, the minimum magnetization reversal interval 'I' Reproduction waveform (independent waveform 101, 1
The synthesized waveform of 02) 103 generates a peak shift of 'rp, and has the drawback that data errors are likely to occur when demodulating the reproduced signal into bits.

The purpose of the present invention is to take into account the drawbacks of conventional recording methods,
An object of the present invention is to provide a recording timing correction method that can significantly reduce disk errors.

According to the present invention, a code word is a code word obtained by converting a data word used in magnetic recording, in which a bit "1" and the next bit "1" are converted.
In a self-clockable recording method in which the number of '0's included between the code word and the code word is a minimum of d and a maximum of 1, the bit position of the code word before recording is different from the corresponding bit of the code word. The (d+1)th bit to one side is “1”,
and others,! 7 pieces, the other is (d-1-n) bits is II
O++ continues (d+n+1>If the bit is "1", a recording timing correction method is obtained in which the recording timing correction amount is changed in accordance with 11.

According to the present invention, it is a code word obtained by converting a data word used in magnetic recording, and consists of a bit "'1" and the next bit "
In a self-clockable recording method in which the number of 0's contained between 1' and The (d+1) bit is '1' and the other bit is (d-1-n) '0' continues between the bits (d+
A recording timing correction method is obtained in which the recording timing correction amount is changed corresponding to n when the (n+1)th bit is '1'', and the correction amount is made the same when n is greater than or equal to m.

Furthermore, it is a code word obtained by converting a data word used in the magnetic recording of the present invention, and the number of 0's contained between a bit "1' and the next bit "1' is d at a minimum and d at a maximum. In a self-clockable recording method, if the bit position before recording is 1 and the bit position corresponding to the code word output is '1', and from now on to both (d+1 > bit th is '0'), the recording timing is corrected. A recording timing correction method is obtained which is characterized by the following.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 7 shows a recording timing correction device according to a first embodiment of the present invention, and FIG. 8 shows its time chart.

In FIGS. 7 and 8, this embodiment is applied to a 2-7 code recording method, and the code word obtained by converting the data word used for magnetic recording is bit “1”.
The number of 6°゛0'' included between and the next bit is the minimum d
(Indeed, this is the most unique recording method that allows for individual cell clocks.

In this embodiment, a shift register 10 inputs a recording timing clock 1 of a code word and bit serial input data 2 of a code word, and each output signal of the shift register 10 is input, and the timing is adjusted according to the output signal. Bit serial signal data 3 of the corrected code word is sent out. Delay circuits 21 to 24, AND circuits 41 to 46, and OR circuit 7
1.

The shift register 10 sequentially transfers the data 2 within the shift register at the timing of the clock 1, and the timing correction circuit 15 adjusts the delay times of the delay circuits 21 to 24 by 1. ~
T! 4, and the delay time is T! , is the maximum and the delay time T! 4
is the minimum, that is, the delay time T* <>Tt 2 >T
Set t a >Tt 4.

This timing correction circuit 15 outputs signals (5) and (8) when the output signals (1) and (2) of the shift register are '0''.
When is 1", that is, when the data has a pattern of 00001001, the output signal 5 of the shift register passes through the delay circuit 21, AND circuit 41, and OR circuit 71, and at the latest timing D2, data 3 is outputted and shifted. When the output signals (1), (5) and (8) of the register are '1' and the output signal (2) is '0', that is, the data is 10.
In the case of the pattern 001001, the output signal (5) of the shift register is configured to pass through the delay circuit 22, the AND circuit 42, and the OR circuit 71 and output data 3 at the second latest timing (Dl).

Furthermore, this timing correction circuit 51 is configured such that when the output signals (2), (5) and (8) of the shift register are '1', the output signal (5) is '1' and the output signals (2) and (8) are '1'. is 0”
, that is, data 1001001 or 0001
When the pattern is 000, the output signal of the shift register (
5) is the delay circuit 23, the AND circuit 43 or r↓44, and the ON correction circuit 15 when the output signals (2) and (9) of the shift register are 1''' and the output signal (8) is 0'', that is, the data When the pattern is 10010001, the output signal (5) of the shift register is sent to the delay circuit 23 and the AND circuit 4.
5. Second earliest timing through OR circuit 71 (
El) outputs data 3, and when the output signals (2) and (5) of the shift register are still 1" and the output signals (8) and (9) are "0", that is, data 1001000.
When the pattern is 0, the shift register output signal (5)
is configured to output data 3 through the AND circuit 46 and the OR circuit 71 at the earliest timing (E2).

Here, the timing correction circuit 15 uses the earliest timing (E) based on the normal timing (N).
2) and the second earliest timing (El) are the apparent upper timing in the leading direction, and the slowest timing (D2) and the second slowest timing (1) 1) are the apparent upper timing and the backward direction. It has been corrected to.

That is, the above 00001001 pattern and 100
The 01001 pattern corrects the timing in the lag direction, and the 10010001 pattern corrects the timing in the advance direction.

This example is! This is effective when using a 4FK Hakumo head. Isolated EIL in case of thin film head! /iAs shown in Figure 3, undersudded (indicated by hunting in the figure) 20
Because of the presence of 0, the peak shift is maximum in a specific pattern. The pattern in which the peak shift is maximum is a Shiba turn where the maximum point of the undershoot of the labor waveform shown in Fig. 4 is located at the zero cross point of the differential waveform of the corresponding pit as shown in Fig. 5, and 3 T - 5T butter 7 (1001
00001) Tonal.

Here, in order to explain the amount of peak shift, the second
See diagram. FIG. 2 shows the differential waveform of the reproduced waveform shown in FIG. 1, and the differential waveform of the rising waveform 101 is 11
1, similarly 102 corresponds to 112, and 103 corresponds to 113.

If the voltage of the rising waveform 112 at the same point in time is Vl, then the peak shift Tp at this time is t Tp-'--xV... River... (1 ) is approximated by 〒dv.

In other words, since the peak shift is determined by the voltage of the adjacent bit at the zero-crossing point of the relevant bit and the slope of the zero-crossing point of the assigned bit, if the slope of the zero-crossing point is constant, the peak shift is is proportional to the magnitude of the voltage of the adjacent bit.

Therefore, the worst pattern peak shift TP shown in FIG.
, is expressed as i Tp, dvX(vs +v,) (2).

The case of 3T・4T (10010001) pattern is shown in Fig. 6i, and the peak shift at this time) Tp,, medium dv'
(Vs Vs) (3) It is expressed as follows. As can be seen by comparing equations (2) and (3), Tp3. is larger, and the difference is also large.

Other patterns 3T/6T (100100000
01) In the case of 3T/7 T (10010000001), a large peak shift occurs because the undershoot overlaps with the zero cross point of the corresponding bit, as in the 3T/5T pattern, but the amount is smaller than the 3T/5T pattern. Therefore, as in this example, the 3T/4T pattern (100
10001 still is 10001001) and 3T/3T or more pattern (10010000... or...00
By changing the timing correction amount between 001001), the optimum timing correction can be obtained.

FIG. 9 shows a recording timing correction device showing a second embodiment of the present invention. Both the apparatus of this embodiment and the above-mentioned embodiments are applied to the 2-7 code recording system, as in the above-mentioned embodiments. In FIG. 9, this embodiment is a shift register 1.
1, and a timing correction circuit 16 including delay circuits 25 to 34, AND circuits 47 to 57, and an OR circuit 72.

The shift register 11 inputs the recording timing clock 1 of the code word and the bit serial data 2 of the code word, and input data 2 has a delay time T of the timer 34 when the clock 0 is input.
~T, 4, and the delay time T□<T! 6 < Tty
<Tts <Two <Tso <Ta1 < Tsg
<Ts s <Ts 4 is set, and the bit serial pig 3 of the samurai code word after timing correction is sent out according to this delay time.

Therefore, in this embodiment, when the corresponding bit is 1'' and the (d+1)th bit to one side is also 1'', the (d-1) bit to the other side is 1''.
When the 1-n) bit is "0" and the (d-1-n+1)th bit is 1', the amount of correction is changed according to n, and an example of the pattern is shown in FIG.

The actual peak shift will vary slightly depending on n.
, n can significantly reduce the peak shift.

FIG. 11 shows a recording timing correction device according to a third embodiment of the present invention, and FIG. 12 shows a time chart thereof.

In FIG. 11, this embodiment includes a shift register 12, a timing correction circuit 17 composed of delay circuits 35 to 39, AND circuits 58 to 63, and an OR circuit 73, and the shift register 12 records code words. A timing clock 1 and bit serial data 2 of the code word are input, and the timing correction circuit 17 retrieves the bit serial data 3 of the code word after timing correction.

The timing correction circuit 17 sets the delay time of the delay circuits 35 to 39 to T. −18g, and the delay time of each delay circuit is Ts.
y>Ta? >Tsg, >Ts e >Ts a
It is set as follows.

In this embodiment, for example, there are six types of correction timing, and the patterns are ooα01001 and D2(
slowest), 10001001 fD ] - (second slowest), 1001001teN (/ --= r le)
El at 10010001 (3rd fastest), 00010
00 is E3 (2nd, earliest), 10010000 is E
2 (earliest). D2 in this example. DI,
E.1. E2 is D2. of the first embodiment. Di, E'l,
This is the same as E2, and the explanation will be omitted here.

1001001 (3T pattern) and 0001000 (
The reason why the correction amount is changed between the magnetization patterns (patterns of 4T or more) is because a peak shift occurs even in front-back symmetrical magnetization patterns, and the cause is the asymmetry of the solitary wave and the influence of the recording demagnetizing field. be. In this case, the peak shift amount is 3
Since the repetition pattern of T is the maximum, and the repetition pattern of 4T or more is small and the difference is small, it is sufficient to correct the timing between 3T and 4T.

Therefore, according to this embodiment, it is possible to take into account the worst pattern due to under-shorting and also reduce the peak shift that occurs in a symmetrical magnetization pattern.

In addition, in the embodiments of the present invention, the first to third embodiments
By combining these embodiments with each other, it is possible to further reduce the peak shift and achieve higher density magnetic recording.

As explained above, the present invention is configured to change the recording timing deviation correction amount according to the recording pattern, thereby significantly reducing the peak shift that occurs during reproduction of the recording pattern, and converting the reproduced signal into bits. This has the remarkable effect of increasing the density of magnetic recording without causing data errors during demodulation.

[Brief explanation of drawings]

Figure 1 shows the relationship between the recording pattern that causes a peak shift and the reproduced waveform, Figure 2 shows the differential waveform of the reproduced waveform in Figure 1, and Figure 3 shows the isolated reproduced waveform in the thin film head. Figure 4 is a diagram showing its differential waveform, Figure 5 is a diagram showing the worst pattern and its reproduced differential waveform, Figure 6 is a diagram showing another pattern and its reproduced differential waveform, and Figure 7 is a diagram showing the reproduced differential waveform. FIG. 8 is a block diagram showing a recording timing correction device according to a first embodiment of the invention, FIG. 8 is a diagram showing an actuator time chart thereof, and FIG. Fig. 10 is a block diagram showing the relationship between shift) L/register force and correction in Fig. 9, Fig. 11
The figure is a block diagram showing a recording timing correction device according to a third embodiment of the present invention, and FIG. 12 is a diagram showing a time chart thereof. 1...Recording timing clock, 2...
・Bit serial data input, 3...Bit serial data output, 10-12...Shift register, 21-39...Delay circuit, 4-63...
...AND circuit, 71-73...OR circuit. Dedicated 1 figure 2 figure, -"%v 3 figure 4 camellia 5 figure 0 Ob10010000+00Q-・ 6 figure 8 figure to-yri + JLflJLJ mouth 1 SJUIK- 1
lll:-2l2lnininny17r Figure 7 Figure 10 ■ Stick ■ Figure 12 Data output h3

Claims (3)

[Claims] (1) A code word converted from a data word used in magnetic recording, which is a code word that is converted from a data word used in magnetic recording.
In a self-clockable recording method in which the number of 0's included between the code word and the code word is a minimum of d and a maximum of d, the bit position of the code before recording is between the corresponding bit of the code word and the The (d+1.) bit of
“o” follows, and the (d+n-1-1)th bit is “1”
”, the recording timing correction method is characterized in that the recording timing correction amount is changed in accordance with n. (2) A code word obtained by converting a data word used in magnetic recording, in which the number of 0s contained between bit 1' and the next bit "'1" is at least d and at most 0. In some self-clockable recording systems, the bit positions of the codeword of a record are the same as the corresponding bit of the codeword and the (
d+1) bit is 1" and the other is (d-)n
) '0' continues between bits (d-4-n+1) If the bit is '1', the recording timing correction amount is changed corresponding to n, and if n is m or more, the shading correction amount is A recording timing correction method according to claim 1, characterized in that the recording timing is corrected. (3) A code word obtained by converting a data word used in magnetic recording, in which the number of 0s contained between a bit "1" and the next bit "1" is at least d and at most 0. In the self-clockable recording method, when the bit position of the code word for recording is 1" for the code word output bit and the (d+1)th bit from now on to both sides is 60", the recording timing is corrected. A recording timing correction method according to claim (1), characterized in that: