JPH04353604A - Recording-timing correction circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit quantity of timing correction circuits for recorded data in a magnetic recording and replay circuit by reducing the number of delay circuits to one. CONSTITUTION:The pattern of a signal data 1 to be recorded is discriminated by a correction-amount selection circuit 5; the delay corresponding to respective correction-amount data 6 is added; a serial data 10 whose timing has been corrected is obtained. Since it is not required to prepare the number of delay circuits corresponding to the number of required timings, the quantity of circuits is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording timing correction method, and more particularly to a recording timing correction method suitable for correcting timing deviations that occur when reproducing data recorded on a magnetic recording medium.

0002

[Prior art] The conventional technology is, for example, Japanese Patent Application Laid-open No. 60-472.
As described in No. 13, data bits in which a peak shift is expected are identified in advance from the pattern of data to be recorded, and the amount and direction of the recording timing are corrected to cancel the peak shift.

0003

[Problems to be Solved by the Invention] In digital magnetic recording, a peak pulse is generated from a voltage waveform (reproduction waveform) generated in an electromagnetic transducer element called a head, and a peak pulse is generated from the pulse train through a data discrimination window created by a PLL circuit. It is common to obtain playback data. As the recording density increases, the peak shift due to interference in the reproduced waveform increases, and if the peak pulse exceeds the discrimination window, a reproduction error occurs. The timing margin within this discrimination window is called the phase margin, and is an indicator of the performance of the device. One of the means for reducing peak shift is recording timing correction (write precompensation). This is a method in which data bits in which a peak shift is expected are identified in advance from the pattern of data to be recorded, and the recording timing is corrected by shifting the amount and direction so as to cancel out the peak shift. Here, as the recording density increases, the amount of interference of the reproduced waveform increases, and a large amount of correction is required. In addition, the magnetic materials used are also transitioning to elements that make full use of thin film technology, so the reproduced waveform includes the effects of pseudo gaps and mander shoot, and the patterns that generate peak shifts are becoming more complex. You need to prepare the timing. These requirements increase the amount of delay and the number of delay circuits in the timing correction circuit. For example, when gate delays of logic circuits are used, a very large number of gates are required. An object of the present invention is to configure a circuit with as few gates as possible.

0004

[Means for Solving the Problems] The above object is achieved by configuring one delay circuit instead of using one delay circuit exclusively for generating various timings.

[0005]

[Operation] FIG. 1 is a functional block diagram showing the operation of the present invention.

FIG. 2 is a functional block diagram of a conventional system.

Serial data string 1 and clock 2 to be recorded are entered into shift register 3. Based on the combination of outputs 4 of the shift registers, the correction amount selection circuit identifies which pattern, selects the correction amount for that pattern from among the correction amount data 6 of each pattern, and supplies it to the delay circuit 8. The delay circuit 8 delays the central output 9 of the shift register by the selected correction amount 7 and outputs it. As a result, the serial data string 10 with proper timing correction for each pattern can be generated using one delay circuit.

In FIG. 2, correction amount data 6 and delay circuits 8 are prepared according to various patterns, one of them is selected by the correction amount selection circuit 5 from the output of the shift register, and the timing-corrected data 10 is It's something you get. In this case, delay circuits must be prepared for the required number of timings, which increases the amount of circuitry.

[0009]

Embodiment An embodiment is shown in FIGS. 3 to 5, and FIG. 3 shows the overall configuration. FIG. 5 is a time chart of this. Serial data 1 to be recorded enters the shift register 3 together with the clock 2. The output 4 of the shift register is sent to a correction amount selection circuit 5 that identifies the pattern. The correction amount selection circuit 5 can be composed of an AND circuit and an OR circuit depending on the target pattern. The data 6 of each pattern is composed of a register, and contains data indicating the amount of delay of each pattern. The data selector 11 outputs data 7 selected from the data 6 of each pattern by the output of the correction amount selection circuit. The delay circuit 8 determines a delay amount based on the selected data 7, and outputs the shift register output 9 delayed by the determined delay amount. As a result, the corrected serial data 10 with different delay amounts depending on the pattern
is obtained. Furthermore, if it is desired to change the correction amount, the correction amount can be changed arbitrarily by simply changing the contents of the register of data 6 of each pattern.

FIG. 4 shows an example of the configuration of a delay circuit. The timing of the shift register output 9 is shifted by the gate delay depending on the number of stages passing through the buffer 12. An arbitrary timing can be obtained using the decoder 13, AND 14, and OR 15 based on the data 7 selected from among them.

FIG. 5 is a time chart. 4-1, 4-2, and 4-3 show part of the output of the shift register in which the recording data 1 is taken in at the clock 2. At the timing 4-1, the value of the select input of the data selector 11 is determined, and at the timing 4-2, one set of input input data is selected and becomes the selected data 7. 4-
The output of No. 3 is the same as No. 9 and is input to the delay circuit. The amount of delay corresponds to the data 7 selected at this time, and the output 10 becomes serial data whose timing differs by d1, d2, and d3, respectively, depending on the data pattern.

0012

According to the present invention, a recording timing correction circuit that requires many types of timing can be configured with only one delay circuit, so that the circuit scale can be reduced.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of the present invention.

FIG. 2 is a functional block diagram of a conventional system.

FIG. 3 is an overall configuration diagram of the embodiment.

FIG. 4 is a diagram showing an example of a delay circuit.

FIG. 5 is a time chart.

[Explanation of symbols]

1... Serial data to be recorded, 2... Clock, 3...Shift register, 5...Correction amount selection circuit, 6...Correction amount data for each pattern, 8...Delay circuit, 10...Corrected serial data.

Claims (1)

[Claims] Claim 1: In a circuit for generating recorded data used when recording digital data of an apparatus for magnetically recording and reproducing digital data, a single delay circuit is used to generate recorded data corrected at various timings. A recording timing correction circuit that makes it possible to generate