JP2663721B2 - Write compensation circuit and magnetic storage device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write compensation circuit,
In particular, the present invention relates to a write compensation circuit of a magnetic storage device using a thin film head and a magnetic storage device using the write compensation circuit.

[0002]

2. Description of the Related Art An example of a conventional write compensation circuit will be described with reference to FIG. As shown in FIG. 7, the conventional write compensation circuit receives write data 701 and a control clock signal 702, outputs a shift register output signal 703 as a signal of the center bit to the delay circuit 74, and A shift register 71 for outputting the state of the other bits except for the bit to the pattern decoder 72, and an output signal 704 of the pattern decoder 72, and information for delaying the phase of the center bit corresponding to the input signal to the delay circuit 74. Judgment circuit 7 to output
3, a delay circuit control signal 705 which is information of the determination circuit 73, and a signal of the center bit of the shift register out of the shift register output signal 703.
And a delay circuit 74 for outputting a signal obtained by delaying the output signal of the shift register 71 in accordance with the information of 7
06 indicates pre-shift write data output from the delay circuit 74.

Next, the operation will be described. When writing information, the write data 701 is input to the shift register 71 in order to correct the peak shift adapted to the waveform when writing in advance the peak shift that would occur when reading with a magnetic head, The waveform is discriminated by the pattern decoder 72, and the peak shift which may be caused by the waveform is corrected and written.

[0004]

The problem to be solved is that the conventional write compensation circuit corrects the peak shift according to the waveform pattern, so that the data read from the thin film head has an isolated waveform caused by the thin film head. The point is that the peak shift due to the undershoot is not corrected. Further, if the conventional technique is used to correct the peak shift due to the undershoot of the isolated waveform, the number of data patterns increases, the circuit becomes large, and the circuit becomes more complicated.

[0005]

According to the write compensation circuit of the present invention, when data is read, the peak shift caused by the data pattern is written in advance by correcting the time during which the peak shift occurs when writing the data. A shift register to which write data and a control clock signal are inputted, wherein a signal of a center bit is outputted to a first delay means, and a first bit and a last state are outputted to a decoder; Outputting the state of the shift register from the center except for the bit and the center bit to the first counting means,
A shift register for outputting the state of the shift register after the center except for the last bit and the center bit to the second counting means; and a shift register for shifting the shift register from the center excluding the first bit and the center bit of the shift register. A first state for inputting the state of the register and outputting information corresponding to the polarity of the first bit and the center bit of the shift register to the decoder
Counting means, and the state of the shift register after the center excluding the last bit and the center bit of the shift register, and information corresponding to the polarity of the last bit and the center bit of the shift register. Counting means for outputting the first state and the last state of the shift register, output information of the first counting means, output information of the second counting means, and a control clock signal. A decoder for converting and outputting a signal corresponding to the phase shift amount of the center bit, and a signal of the state of the center bit of the shift register, wherein the write data passes through the shift register and the first and second counts. First delay means for inputting to the means, delaying by the time from being processed by the decoder to being output from the determination means, an output signal of the decoder and a clock control signal Determining means for outputting to the second delay means information for delaying the phase of the center bit in accordance with the output signal of the decoder; and information of the determining means and the output signal of the first delay means. And a second delay means for outputting a signal obtained by delaying the output signal of the first delay means in accordance with the information of the determination means. Further, a write compensation circuit according to another aspect of the present invention is a shift register to which write data and a control clock signal are inputted, wherein the shift register outputs a signal of a center bit to a first delay means, and The state of the shift register in the range selected by the first selection means from the first bit removed to the center bit is output to the first selection means, and the state of the shift register from the last bit excluding the center bit to the middle bit is output. The state of the shift register in the range selected by the second selection means up to the bit is output to the second selection means, and the state of the shift register from the center excluding the first bit and the center bit to the first is stored in the first selection means. And a shift register for outputting the state of the shift register after the center except for the last bit and the center bit to the second counting means. Control means for outputting information corresponding to the position of the undershoot of the isolated waveform caused by the corresponding head; and a first information between the output information of the control means and the first bit excluding the center bit and the center bit. And the state of the shift register in the range selected by the selection means is selected, the bits of the shift register are selected in accordance with the output information of the control means, and the state of the selected bit is output to the decoder. And input the output information of the control means and the state of the shift register in a range to be selected from the last bit excluding the center bit to the center bit, corresponding to the output information of the control means. Second selecting means for selecting a bit of the shift register and outputting the state of the selected bit to the decoder; The state of the shift register before the center excluding the bit and the information of the control means are inputted, and the polarity of the bit of the shift register corresponding to the information output from the control means and the polarity of the center bit are inputted. First counting means for outputting the obtained information to the decoder, the state of the shift register after the center excluding the last bit and the center bit of the shift register, and the information of the control means. Second counting means for outputting to the decoder information corresponding to the polarity of the bit of the shift register corresponding to the information output from the means and the central bit, and the first and second selecting means selected by the first and second selecting means. The state of the shift register, the output information of the first and second counting means and the control clock signal are input, and a signal corresponding to the phase shift amount of the central bit is determined. A decoder for outputting to a stage, an output signal of the decoder and a control clock signal, and determining means for outputting, to the second delay means, information for delaying the phase of the center bit in accordance with the output signal of the decoder And the signal in the state of the bit at the center of the shift register until the write data is input to the first and second counting means through the shift register, processed by the decoder and output from the determination means. First delay means for delaying by a time, information of the determination means and an output signal of the first delay means are input, and the first signal is supplied according to the information of the determination means.
And a second delay means for outputting a signal obtained by delaying the output of the delay means. A write compensation circuit according to still another aspect of the present invention is a shift register to which write data and a control clock signal are inputted, wherein the shift register outputs a signal of a center bit to a first delay unit, and The state of the shift register before the center excluding the center bit is output to the first counting means, and the state of the shift register after the center excluding the last bit and the center bit is output to the second counting means. A shift register that outputs the first bit and the last bit to the decoder, and outputs the bit state of the center bit neighborhood to the pattern decoder, and a shift from the center except for the first bit and the center bit of the shift register. First counting means for inputting the status of the register and outputting to the decoder information corresponding to the polarity of the first bit and the center bit of the shift register; The state of the shift register after the center excluding the last bit and the center bit of the shift register is input, and information corresponding to the polarity of the last bit and the center bit of the shift register is output to the decoder. Counting means, a bit state near the center bit of the shift register, and a pattern decoder for outputting information corresponding to the bit pattern near the center bit to the determination means; a first state and a last state of the shift register. A decoder which inputs a state, output information of the first and second counting means and a control clock signal, and outputs a signal corresponding to a phase shift amount of a center bit to a determination means; The state signal is written as the write data is input to the first and second counting means through the shift register,
First delay means for delaying by the time until it is processed by the decoder and output from the determination means, and output information of the pattern decoder, an output signal of the decoder, and a control clock signal are input, and corresponding to the information. Determination means for outputting information for delaying the phase of the center bit to the second delay means, and information from the determination means and an output signal from the first delay means, and And second delay means for outputting a signal obtained by delaying the output signal of the first delay means. Further, a write compensation circuit according to another aspect of the present invention is a shift register to which write data and a control clock signal are inputted, wherein the shift register outputs a signal of a center bit to a first delay means, and The state of the shift register in the range selected by the first selection means from the first bit removed to the center bit is output to the first selection means, and the state of the shift register from the last bit excluding the center bit to the middle bit is output. The state of the shift register in the range selected by the second selection means up to the bit is output to the second selection means, and the state of the shift register from the center excluding the first bit and the center bit is stored in the first selection means. Shift to output to the counting means, to output the state of the shift register after the center except the last bit and the center bit to the second counting means, and to output the bit state near the center bit to the pattern decoder; Control means for inputting a register and address information and outputting information corresponding to a position of an undershoot of an isolated waveform caused by a head corresponding to the address information; and output information of the control means and a central bit are removed. The state of the shift register in a range to be selected from the first bit to the center bit is input, and the bits of the shift register are selected according to the output information of the control means, and the state of the selected bit is changed. First selection means for outputting to the decoder, and the output information of the control means and the state of the shift register in a range to be selected from the last bit excluding the center bit to the center bit; And a second bit for selecting a bit of this shift register in accordance with the output information of the shift register and outputting the state of the selected bit to the decoder.
Selecting means, and inputting the state of the shift register and the information of the control means from the center excluding the first bit and the center bit of the shift register, and corresponding to the information output from the control means. First counting means for outputting information corresponding to the polarity of the bit of the shift register and the center bit to the decoder; and a shift register of the shift register after the center excluding the last bit and the center bit of the shift register. Inputting the state and the information of the control means,
Second counting means for outputting to the decoder information corresponding to the polarity of the bit of the shift register and the center bit corresponding to the information output from the control means, and selection of the first and second selection means A decoder which inputs the state of the shift register, the output information of the first and second counting means, and the control clock signal, and outputs an output corresponding to the phase shift amount of the center bit of the shift register to the determining means; A pattern decoder for inputting a bit state near the center bit of the shift register and outputting information corresponding to the bit pattern near the center bit to the determination unit; and a write data signal for the state of the center bit of the shift register. Through the shift register
And first delay means for delaying the time inputted to the second counting means, processed by the decoder and outputted from the determination means, output information of the pattern decoder, output signal of the decoder, and control clock signal. Determining means for outputting information for delaying the phase of the center bit corresponding to the information to the second delay means; and inputting the information of the determining means and the output signal of the first delay means. And
A second delay unit for outputting a signal obtained by delaying the output signal of the first delay unit in accordance with the information of the determination unit. Further, in the write compensation circuit according to still another aspect of the present invention, in any one of the above inventions, in each of the counting means, the state of the shift register is input, the magnetization reversal is counted, and whether the number is an odd number or an even number is determined. Is output to the decoder.

[0006]

In the present invention, when reading data,
The peak shift caused by the data pattern is written by correcting the time at which the peak shift occurs when writing data in advance.

[0007]

FIG. 1 is a block diagram showing an embodiment of a write compensation circuit according to the present invention. In FIG. 1, reference numeral 1 denotes a shift register which receives a control clock signal 102 and write data 101 synchronized with the control clock signal 102. The shift register 1 transmits a signal of a central bit to a delay means (5). And outputs the states of the first bit and the last bit to the decoder (4), and outputs the state of the shift register from the center to the previous shift register excluding the first bit and the center bit to the counting means (2). The shift register outputs the state of the shift register after the center except for the bit and the center bit to the counting means (3). Reference numeral 2 denotes a counting circuit. The counting circuit 2 inputs the state of the shift register from the center except for the first bit and the center bit of the shift register 1 and inputs the first bit and the center bit of the shift register. And a counting means for outputting information corresponding to the polarity to the decoder (4). Reference numeral 3 denotes a counting circuit. The counting circuit 3 inputs the state of the shift register 1 after the center excluding the last bit and the center bit of the shift register 1, and outputs the last bit of the shift register 1 and the center of the shift register 1. The counting means outputs information corresponding to the polarity of the bit to the decoder (4). Reference numeral 4 denotes the first state and the last state of the shift register 1, the output information of the counting means (2), the output information of the counting means (3), and the control clock signal 102, which correspond to the phase shift amount of the center bit. A decoder 5 converts the signal into a signal and outputs the signal. The delay circuit 5 converts the signal of the state of the center bit of the shift register 1 into the write data 101 through the shift register 1 and counting means (2), ( The delay means is configured to delay by a time from being input to 3) to being processed by the decoder 4 and output from the determination means (6). 6
Is a judgment circuit, and the judgment circuit 6 receives the output signal of the decoder 4 and the clock control signal 102, and
And a determination means for outputting information for delaying the phase of the center bit to the delay means (7) in accordance with the output signal.
Reference numeral 7 denotes a delay circuit. The delay circuit 7 receives the information of the judging means (6) and the output signal of the delay means (5), and outputs the output of the delay circuit 5 in accordance with the information of the judging means (6). It constitutes delay means for outputting a signal obtained by delaying the signal. The delay circuit 7 outputs the pre-shift write data 109
To a write circuit (not shown).

The shift register 1 receives the write data 101 and the control clock signal 102 as inputs, and inputs T ₀ of the shift register output signal 103 to the delay circuit 5 and T _A and T _B of the shift register output signal 103 to the decoder 4.
In the T _-1 ~T _{B + 1} of the shift register output signal 103 to the counter circuit 2, T ₁ of the shift register output signal 103 through T
_A-1 is output to the counting circuit 3, respectively. Further, the decoder 4 is provided with the shift register output signals T _B and T _A and the counting circuit 2.
, An output signal 105 of the counting circuit 3, and a control clock signal 102, and a decoder output signal 106 is output to the determination circuit 6. The determination circuit 6 receives the decoder output signal 106 and the control clock signal 102 and outputs a delay circuit control signal 107 to the delay circuit 7. Further, the delay circuit 5 outputs the shift register output signal 103
The delay circuit output write data 108 to T ₀ and the control clock signal 102 as inputs and outputs to the delay circuit 7, the pre-shift write data 1 as an input delay circuit output write data 108 the delay circuit 7 and the delay circuit control signal 107
09 is output to the write circuit.

The embodiment shown in FIG. 1 is for compensating for a peak shift due to a reproduction waveform peculiar to a thin film head.
Small peak shift due to conventional pattern effect, no need for conventional write compensation, small variation in thin film head characteristics, small variation in T _R ′, T _F ′, select shift register position If you do not need to.

FIG. 2 is a block diagram showing another embodiment of the present invention. In FIG. 2, 1 is write data 101
And a control clock signal 102. The shift register outputs the signal of the center bit to the delay means (15), and selects from the first bit excluding the center bit to the center bit (15). The state of the shift register in the range selected by 8) is output to the selection means (8), and the shift of the range selected by the selection means (9) is performed from the last bit excluding the center bit to the center bit. The state of the register is output to the selection means (9), the state of the shift register from the center excluding the first bit and the center bit is output to the counting means (10), and the last bit and the center bit are excluded. The shift register outputs the state of the shift register after the center to the counting means (11). Reference numeral 12 denotes a control circuit, which constitutes control means for inputting an address signal 110 as address information and outputting information corresponding to a position of an undershoot of an isolated waveform caused by a head corresponding to the address information. I have. Reference numeral 8 denotes a selection circuit. The selection circuit 8 is a shift register in a range selected by the selection means (8) between the output information of the storage means (12) and the first bit excluding the center bit and the center bit. 1 is input, the bit of the shift register 1 is selected according to the output information of the control means (12), and the selection means outputs the state of the selected bit to the decoder. 9 is a selection circuit, which inputs the output information of the control means (12) and the state of the shift register 1 in a range to be selected from the last bit excluding the center bit to the center bit; A selecting means for selecting a bit of the shift register 1 in accordance with the output information of the control means (12) and outputting the state of the selected bit to the decoder. Reference numeral 10 denotes a counting circuit. The counting circuit 10 inputs the state of the shift register 1 before the center excluding the first bit and the center bit of the shift register 1 and information of the control means (12). Means (1
The counting means outputs information corresponding to the polarity of the bit of the shift register 1 corresponding to the information output from 2) and the polarity of the center bit to the decoder. Numeral 11 denotes a counting circuit. The counting circuit 11 inputs the state of the shift register 1 after the center excluding the last bit and the center bit of the shift register 1 and information of the control means (12). The counting means outputs to the decoder information corresponding to the polarity of the bit of the shift register 1 and the center bit corresponding to the information output from the means (12). Reference numeral 13 inputs the state of the shift register 1 selected by the selectors (8) and (9), the output information of the counters (10) and (11), and the control clock signal 102. A decoder for outputting a signal corresponding to the amount of phase shift to the determination means;
The determination circuit 14 receives the output signal of the decoder 13 and the control clock signal 102, and outputs information for delaying the phase of the center bit corresponding to the output signal of the decoder 13 to the delay means (16). Means.
Reference numeral 15 denotes a delay circuit. The delay circuit 15 outputs a signal in the state of the central bit of the shift register 1 and write data passes through the shift register 1 and counting means (10) and (11).
, And processed by the decoder 13 and determined by the determination means (14).
A first delay means for delaying the time from the output to the output. Reference numeral 16 denotes a delay circuit.
Is a delay means for receiving the information of the determination means (14) and the output signal of the delay means (15), and outputting a signal obtained by delaying the output of the delay means (15) according to the information of the determination means (14). Is composed. 2, reference numeral 103 denotes a shift register output signal, and reference numeral 111 denotes a signal from the control circuit 12.
R> the control signal of the selection circuit and the counting circuit to be output, 11
2 and 113 are output signals of the selection circuits 8 and 9;
4 and 115 are output signals of the counting circuits 10 and 11,
116 is a decoder output signal, 117 is delay circuit output write data, 118 is a delay circuit control signal output from the determination circuit 14, and 119 is preshift write data output from the delay circuit 16 to an external write circuit. In the embodiment shown in FIG. 2, the position of the shift register 1 can be selected corresponding to the address in the embodiment shown in FIG.

FIG. 3 is a block diagram showing still another embodiment of the write compensation circuit according to the present invention. 3, reference numeral 1 denotes a write data 101 and a control clock signal 102.
, And outputs the signal of the center bit to the delay circuit, and outputs the state of the shift register 1 from the center except for the first bit and the center bit to the counting means (17), The state of the shift register 1 after the center excluding the last bit and the center bit is counted by the counting means (1
8), outputs the first bit and the last bit to the decoder, and outputs the bit state near the center bit to the pattern decoder. Reference numeral 17 denotes a counting circuit. The counting circuit 17 inputs the state of the shift register 1 from the center excluding the first bit and the center bit of the shift register 1, and inputs the first bit and the center bit of the shift register 1. To output information corresponding to the polarity to the decoder to the decoder. 18 is a counting circuit,
The counting circuit 18 inputs the state of the shift register 1 after the center excluding the last bit and the center bit of the shift register 1, and corresponds to the polarity of the last bit and the center bit of the shift register 1. The counting means outputs information to the decoder. Reference numeral 19 denotes a pattern decoder for inputting the bit state near the center bit of the shift register 1 and outputting information corresponding to the bit pattern near the center bit to the determination circuit. Reference numeral 20 denotes the first state and the last state of the shift register 1. Counting means (17), (18)
And a control clock signal 102, and outputs a signal corresponding to the phase shift amount of the center bit to the determination circuit. Reference numeral 21 denotes a delay circuit. A write signal is sent to the counting means (1
7) and (18), processed by the decoder 20,
A delay means for delaying the time until the signal is output from the determination circuit is configured. Reference numeral 22 denotes a judgment circuit.
Numeral 2 is a judging means for receiving the output information of the pattern decoder 19, the output signal of the decoder 20, and the control clock signal 102 and outputting information for delaying the phase of the center bit to the delay means (23) in accordance with the information. Make up. 23
Is a delay circuit, and the delay circuit 23 is a determining means (22)
And the output signal of the delay means (21) are input, and the delay means (2) corresponding to the information of the determination means (22) is input.
The delay means outputs a signal obtained by delaying the output signal of 1). In FIG. 3, reference numeral 103 denotes a shift register output signal, and reference numerals 121 and 122 denote counting circuits 1.
7 and 18 are output signals, and 123 is the pattern decoder 1
Reference numeral 9 denotes an output signal, reference numeral 124 denotes a decoder output signal, reference numeral 125 denotes a delay circuit output write data, reference numeral 126 denotes a delay circuit control signal output from the determination circuit 22, and reference numeral 127 denotes a pre-shift write output from the delay circuit 23 to an external write circuit. Show data. The embodiment shown in FIG. 3 is such that the embodiment shown in FIG. 1 can be used together with the conventional write compensation for a peak shift due to a data pattern.

FIG. 4 is a block diagram showing another embodiment of the write compensation circuit according to the present invention. In FIG. 4, the same reference numerals as those in FIG.
01 and a control clock signal 102. The shift register receives a central bit signal as delay means (31).
And outputs the state of the shift register 1 in a range selected by the selection means (25) from the first bit excluding the center bit to the center bit to the selection means (25). The state of the shift register 1 in the range selected by the selection means (26) from the last bit excluding the center bit to the center bit is output to the selection means (26), and the state of the shift register 1 from the center excluding the first bit and the center bit is output from the center. The state of the previous shift register 1 is output to the counting means (27), the state of the shift register 1 after the center excluding the last bit and the center bit is output to the counting means (28), and the bits near the center bit are output. This is a shift register that outputs the state to the pattern decoder. 25 is a selection circuit, which inputs the output information of the control means (12) and the state of the shift register 1 in the range to be selected from the first bit excluding the center bit to the center bit, The bit of the shift register 1 is selected according to the output information of the control means (12),
The selection means outputs the state of the selected bit to the decoder. Reference numeral 26 denotes a selection circuit.
Inputs the output information of the control means (12) and the state of the shift register 1 in a range selected from the last bit excluding the center bit to the center bit, and corresponds to the output information of the control means (12). A selection means for selecting a bit of the lever shift register 1 and outputting the state of the selected bit to the decoder. Reference numeral 27 denotes a counting circuit. The counting circuit 27 inputs the state of the shift register 1 from the center excluding the first bit and the center bit of the shift register 1 and information of the control means (12). Means (1
The counting means outputs information corresponding to the polarity of the bit of the shift register 1 corresponding to the information output from 2) and the polarity of the center bit to the decoder. Numeral 28 denotes a counting circuit which receives as input the state of the shift register after the center excluding the last bit and the center bit of the shift register 1 and information of the control means (12). The counting means outputs information corresponding to the polarity of the bit of the shift register 1 corresponding to the information output from (12) and the polarity of the center bit to the decoder. Reference numeral 29 denotes the state of the shift register 1 selected by the selection means (25) and (26) and the counting means (27) and (2).
8) Input the output information and the control clock signal 102,
A decoder 30 for outputting an output corresponding to the phase shift amount of the center bit of the shift register 1 to the determination circuit. A decoder 30 inputs the bit state near the center bit of the shift register 1 and outputs information corresponding to the bit pattern near the center bit. A pattern decoder for outputting to the decision circuit, 31 is a delay circuit,
The delay circuit 31 converts the signal of the state of the bit at the center of the shift register 1 into the counting means (27) and (28) through the shift register 1 and is processed by the decoder 29. This constitutes a delay means for delaying the time until the operation is completed. Reference numeral 32 denotes a judgment circuit which outputs the output information of the pattern decoder 30, the output signal of the decoder 29, and the control clock signal 102.
And outputs the information for delaying the phase of the center bit corresponding to the information to the delay means (33). Reference numeral 33 denotes a delay circuit. The delay circuit 33 receives the information of the judging means (32) and the output signal of the delay means (31). The delay circuit (31) corresponds to the information of the judging means (32). And a delay means for outputting a signal obtained by delaying the output signal of (1). And shift register 1
Is the control clock signal 102 and the control clock signal 10
2, the shift register output signal 1 which is the output signal of the shift register 1
03, a pattern decoder 30, a selection circuit 25, a counting circuit 27, a counting circuit 28, a selection circuit 26, and a delay circuit 31
Output to The pattern decoder 30 is a shift register 1
Of the shift register output signal 103 which is the output of
_-1 through T shift register output signal 10 to _E and T ₁ through T _D
3 and the control clock signal 102, and outputs a pattern decoder output signal 130, which is an output signal of the pattern decoder 30, to the determination circuit 32. On the other hand, the control circuit 1
2 inputs the address signal 110 and outputs the control signal 111a to the selection circuit 25 and the counting circuit 27,
b is output to the selection circuit 26 and the counting circuit 28. The selection circuit 25 outputs T _{B + L to} T _B of the shift register output signal 103.
Shift register output signal 103 and control signal 11 up to _B
A selection circuit output signal 132 which is an output of the selection circuit 25 is output to the decoder 29 with 1a as an input. Selection circuit 26
Is the shift register output signal 103 from T _{AN to} T _A of the shift register output signal 103 and the control signal 111b.
And outputs the selection circuit output signal 133, which is the output of the selection circuit 26, to the decoder 29. Then, the counting circuit 27 outputs T _{-1 to} T ₁ of the shift register output signal 103.
Shift register output signal 103 up to _{B + 1} and control signal 1
A counter circuit output signal 134, which is an output of the counter circuit 27, is output to the decoder 29 with the input 11 a. Counting circuit 2
8 is T _{1 to} T _A−1 of the shift register output signal 103.
Up to the shift register output signal 103 and the control signal 111
The count circuit output signal 135 which is the output of the count circuit 28 is output to the decoder 29 with b as an input. This decoder 2
9 is a selection circuit output signal 132 and a counting circuit output signal 13
4, selection circuit output signal 133, counting circuit output signal 135
And the control clock signal 102 as an input, the decoder 2
9 is output to the decision circuit 32.
Output to The determination circuit 32 receives the pattern decoder output signal 130, the decoder output signal 136, and the control clock signal 102 as inputs, and outputs a delay circuit control signal 137 output from the determination circuit 32 to the delay circuit 33. And
The delay circuit 31 outputs T
_{With 0} and the control clock signal 102 as inputs, the delay circuit output write data 138 output from the delay circuit 31 is output to the delay circuit 33. The delay circuit 33 receives the delay circuit control signal 137 and the delay circuit output write data 138 as inputs, and outputs the pre-shift write data 139 output from the delay circuit 33 to a write circuit (not shown).

Next, the operation of the embodiment shown in FIG. 4 will be described. First, the control clock signal 10 is supplied to the shift register 1.
2 and the write data 101 synchronized with the control clock signal 102, the shift register 1 sets the level of the write data 101 (“1”... High level, “0”).
... outputs a low level) to T _B of the shift register output signal 103, this level is sent to the high-order register for each input of the control clock signal 102. In this embodiment, the shift register 1 has registers from the highest order T _A to the lowest order T _B , and outputs the value of each register as the shift register output signal 103. Here, it is assumed that when the level of the write data 101 is “1”, a magnetization transition exists (when the level is “1”, the direction of the current flowing through the magnetic head of the magnetic disk device is switched).
The pattern decoder 30 controls the shift register 1 from T _{-1 to} T _E.
And shift register output signals 103 from T _{1 to} T _D are inputted, and the positions where the levels of the registers from T _{−1 to} T _E and T _{1 to} T _D are “1” are determined, and the positions are determined according to the positions. And outputs a pattern decoder output signal 130. That is, the pattern decoder 30 determines the data pattern of the write data 101 and outputs an output corresponding to the pattern as the pattern decoder output signal 130. A method of a conventional write compensation circuit is to obtain write data for which write compensation has been performed by changing the delay time of the write data in accordance with the pattern decoder output signal 130. Then, the selection circuit 25 is a control signal from the shift register output signal 103 to T _B ~T _B + _L input 1
One is selected according to 11a, and the level is output as a selection circuit output signal 132. The counting circuit 27 counts the number of registers in which the level of the register from the register one level higher than the register selected by the selection circuit 25 to T _-1 is "1" by the control signal 111a and whether the number is odd. It is determined whether the number is an even number, and the result is output as a counting circuit output signal 134. For example, a level “1” is output for an even number, and a level “0” is output for an odd number. The selection circuit 26 selects one of the input shift register output signals 103 from T _{A to} T _{AN in} accordance with the control signal 111b, and sets the level thereof to the selection circuit output signal 133.
Output as Counting circuit 28 counts the number of register-level registers from register 1箇下position from the register selection circuit 26 is selected by the control signal 111b to T ₁ is "1", even or the number thereof is an odd number Is determined, and the result is output as a counting circuit output signal 135. The decoder 29 outputs the selection circuit output signal 132
, Counting circuit output signal 134 and selection circuit output signal 13
The decoder output signal 136 is output in accordance with the level of the counter signal 3 and the output signal 135 of the counting circuit. The determination circuit 32 receives the input pattern decoder output signal 130 and the decoder output signal 13
6, the delay time of the write data is determined, and the delay circuit control signal 13 for controlling the delay circuit 33 in the subsequent stage is determined.
7 is output. The delay circuit 33 receives the delay circuit control signal 1
37, the input delay circuit output write data 138 is delayed for a predetermined time, and the pre-shift write data 1
39 is output. The delay circuit 31 is a pattern decoder 3
0, the input shift register output signal 103 is delayed by the number of clocks of the control clock signal 102 required for processing of the decoder 29 and the determination circuit 32, and output as delay circuit output write data 138. The control circuit 12 receives the address signal 110 as an input and outputs a control signal 111a and a control signal 111b according to the input.

Next, the contents of each signal will be described with reference to FIGS. 5 and 6 and Table 1 below.

[0015]

[Table 1]

First, a solitary wave of a reproduced waveform when a thin film head is used is as shown in FIG. 5A, and a waveform of the solitary wave after its differentiation is as shown in FIG. 5B. . At this time, if the positions of the portions A and B separated from the magnetization transition of the center point P by T _F ′ and T _R ′ overlap other magnetization transitions, a peak shift occurs at that position. Now, considering the basis of the T ₀ of the output signal 103 of the shift register 1, as shown in FIG. 6, when there is another magnetic transition from T ₀ after T _R 'before or T _F', the bit T ₀ Affected by that. The direction of the peak shift caused by the influence is the polarity of the magnetization transition before T ₀ and T _R 'or after T ₀ and T _F ', that is, the direction of the magnetization transition before T ₀ and T _R 'or after T _F '. The opposite occurs depending on how many magnetization transitions are present between the odd and even numbers. Therefore, the number of magnetization reversals (the number of levels “1”) is determined before and after by the counting circuit 27 and the counting circuit 28, respectively. Since the sizes of T _F ′ and T _R ′ change depending on the position of the head and the cylinder, the position of an arbitrary register of the shift register 1 can be selected by the selection circuit 25 and the selection circuit 26. At this time, the selection circuit output signal 132, the counting circuit output signal 134, and the selection circuit output signal 1
Table 1 shows the state of the decoder output with respect to the state of the counter circuit output signal 135. At this time, the decoder output signal 136 has nine outputs. In Table 1, N is the peak shift 0, D is the delay side, and E is the advance side.
Then, the selection circuit output signal 132 and the selection circuit output signal 1
Numeral 13 indicates “0” no magnetization transition and “1” magnetization transition, and the counting circuit output signal 134 and the counting circuit output signal 135
Is an odd number of "0" and an even number of "1", Dr and Df are delay sides, and Er and Ef are advance sides.

When the effects of T _F ′ and T _R ′ are substantially equal, ie, Er = Ef = −Dr = −Df, E = Er = E
f, D = Dr = Df, there are five ways. Then, the judgment circuit 32 calculates a peak shift obtained by adding both the peak shift peculiar to the thin film head and the peak shift due to the conventional pattern effect, and controls the delay circuit 33. With the write compensation circuit having such a configuration, optimal write compensation can be performed for a reproduction waveform unique to a thin film head.
It can be used together with the conventional write compensation for the pattern effect. Further, it is possible to cope with a difference in undershoot position due to a difference in head characteristics and a head position. And in any of the embodiments shown in FIGS.
Each counting means can input the state of the shift register, count the number of magnetization reversals, and output information on whether the number is odd or even to the decoder. Further, a magnetic storage device can be configured using the write compensation circuit of the embodiment shown in FIGS.

[0018]

As described above, in the write compensation circuit of the present invention, when data is read, the peak shift caused by the pattern is written in advance by correcting the time during which the peak shift occurs when writing the data. With this configuration, it is possible to perform write compensation for a peak shift caused by a reproduction waveform peculiar to a thin film head, and to use this write compensation in combination with the write compensation for a peak shift caused by a conventional data pattern. This has the effect that compensation can be made, and it is also possible to cope with differences in the characteristics of the thin film head. In addition, each of these advantages allows the peak shift amount to be effectively reduced, so that the error rate can be reduced and the margin for the data clock is increased,
This has the effect of improving reliability.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a write compensation circuit.

FIG. 2 is a block diagram showing another embodiment of the write compensation circuit.

FIG. 3 is a block diagram showing still another embodiment of the write compensation circuit.

FIG. 4 is a block diagram showing another embodiment of the write compensation circuit.

FIG. 5 is a waveform diagram showing a reproduction waveform when the thin film head used for explaining the operation in FIG. 4 is used.

FIG. 6 is an explanatory diagram of a shift register used for explaining the operation in FIG. 4;

FIG. 7 is a block diagram showing an example of a conventional write compensation circuit that does not use the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register 2, 3 Counting circuit 4 Decoder 5 Delay circuit 6 Judgment circuit 7 Delay circuit 8, 9 Selection circuit 10, 11 Counting circuit 12 Control circuit 13 Decoder 14 Judgment circuit 15, 16 Delay circuit 17, 18 Counting circuit 19 Pattern decoder Reference Signs List 20 decoder 21 delay circuit 22 determination circuit 23 delay circuit 25, 26 selection circuit 27, 28 counting circuit 29 decoder 30 pattern decoder 31 delay circuit 32 determination circuit 33 delay circuit

Claims (6)

(57) [Claims] 1. A write compensation circuit for writing a peak shift caused by a data pattern when reading data by correcting a time at which the peak shift occurs when writing the data in advance. The input shift register outputs a signal of a center bit to a first delay means, outputs a state of a first bit and a last bit to a decoder, and outputs a signal from a center except for a first bit and a center bit. A shift register that outputs the state of the shift register to the first counting means, and outputs the state of the shift register after the center except for the last bit and the center bit to the second counting means; Enter the previous state of this shift register from the center, excluding the middle bit and the first bit of this shift register. First counting means for outputting information corresponding to the polarity of the shift register to the decoder, and the state of the shift register after the center excluding the last bit and the center bit of the shift register, and Second counting means for outputting information corresponding to the polarity of the last bit and the center bit of the register to the decoder; first state and last state of the shift register; output information of the first counting means; A decoder which receives the output information of the second counting means and the control clock signal, converts the signal into a signal corresponding to the phase shift amount of the center bit, and outputs the signal; A first delay which delays data by a time until the data is input to the first and second counting means through the shift register, processed by the decoder and output from the determination means. Means for inputting an output signal of the decoder and a clock control signal, and outputting to the second delay means information for delaying the phase of the center bit in accordance with the output signal of the decoder; And the second delay means for outputting a signal obtained by delaying the output signal of the first delay means in accordance with the information of the determination means. A write compensation circuit, comprising: 2. A write compensation circuit for writing a peak shift caused by a data pattern when reading data by correcting a time at which the peak shift occurs when writing data in advance. And outputs the signal of the center bit to the first delay means, and the range selected by the first selection means from the first bit excluding the center bit to the center bit. Is output to the first selecting means, and the state of the shift register in the range selected by the second selecting means from the last bit excluding the center bit to the center bit is output to the first selecting means. 2, and outputs the state of the shift register from the center to the previous shift register excluding the first bit and the center bit to the first counting means.
A shift register for outputting the state of the shift register after the center except for the last bit and the center bit to the second counting means, and an undershoot of an isolated waveform caused by a head which receives address information and is caused by a head corresponding to the address information. Control means for outputting information corresponding to the position; and a shift register in a range selected by the first selection means between the output information of the control means and the first bit excluding the center bit and the center bit. Of the shift register according to the output information of the control means, and outputs the state of the selected bit to the decoder.
And the state of the shift register in the range selected from the last bit excluding the center bit to the center bit, and the output information of the control means, Second selecting means for selecting a bit of the shift register and outputting a state of the selected bit to a decoder; and a shift register preceding the shift register except for a first bit and a center bit of the shift register. The first counting means for inputting the state of the control means and the information of the control means and outputting to the decoder information corresponding to the polarity of the bit of the shift register corresponding to the information output from the control means and the center bit. And the state of the shift register after the center excluding the last bit and the center bit of the shift register and the information of the control means are inputted. Second counting means for outputting to the decoder information corresponding to the polarity of the bit of the shift register corresponding to the information output from the shift register and the center bit, and the shift selected by the first and second selecting means. A decoder which receives a register state, output information of each of the first and second counting means, and a control clock signal, and outputs a signal corresponding to the phase shift amount of the central bit to the judging means; Determining means for receiving a signal and a control clock signal and outputting information for delaying the phase of the center bit to the second delay means in accordance with the output signal of the decoder, and the state of the center bit of the shift register The write data is input to the first and second counting means through this shift register, processed by the decoder, and output from the determination means. First delay means for delaying by the time until, the information of the determination means and the output signal of the first delay means are input, and the output of the first delay means is delayed according to the information of the determination means. And a second delay means for outputting the generated signal. 3. A write compensation circuit for writing a peak shift caused by a data pattern when reading data by correcting a time at which the peak shift occurs when writing the data in advance. The input shift register outputs the signal of the center bit to the first delay means, and outputs the state of the shift register from the center excluding the first bit and the center bit to the first counting means. , The state of the shift register after the center excluding the last bit and the middle bit is output to the second counting means, the first bit and the last bit are output to the decoder, The shift register output to the decoder and the state of the shift register from the center excluding the first bit and the center bit of this shift register are entered. First counting means for outputting to the decoder information corresponding to the polarities of the first bit and the center bit of the shift register, and a counter from the center excluding the last bit and the center bit of the shift register. A second counting means for inputting the state of the shift register to the decoder and outputting information corresponding to the polarity of the last bit and the center bit of the shift register to the decoder; A pattern decoder for inputting and outputting information corresponding to a bit pattern in the vicinity of the center bit to the judging means; a first state and a last state of the shift register; and output information of the first and second counting means. A decoder for receiving a control clock signal and outputting a signal corresponding to the phase shift amount of the center bit to the determination means; A first delay unit for delaying a bit state signal by a time until write data is input to the first and second counting units through the shift register, processed by the decoder, and output from the determination unit; Determining means for receiving output information of the pattern decoder, an output signal of the decoder, and a control clock signal, and outputting to the second delay means information for delaying the phase of the center bit in accordance with the information; A second delay for inputting the information of the determination means and the output signal of the first delay means and outputting a signal obtained by delaying the output signal of the first delay means in accordance with the information of the determination means; And a means for compensating for writing. 4. A write compensation circuit for writing a peak shift caused by a data pattern when reading data by correcting a time at which the peak shift occurs when writing data in advance. And outputs the signal of the center bit to the first delay means, and the range selected by the first selection means from the first bit excluding the center bit to the center bit. Is output to the first selection means, and the state of the shift register in the range selected by the second selection means from the last bit excluding the center bit to the center bit is output to the second selection means. Output to the selection means of
The state of the shift register before the center except for the first bit and the center bit is outputted to the first counting means, and the state of the shift register after the center except for the last bit and the center bit is outputted to the second counting means. And a shift register for outputting the bit state near the center bit to the pattern decoder, and inputting address information and outputting information corresponding to the position of an undershoot of an isolated waveform caused by a head corresponding to the address information. Control means for inputting the output information of the control means and the state of the shift register in a range selected from the first bit to the center bit excluding the center bit, corresponding to the output information of the control means; First selecting means for selecting a bit of the lever shift register and outputting the state of the selected bit to a decoder; The state of the shift register in a range to be selected from the last bit excluding the center bit to the center bit is input, and the bits of the shift register are selected according to the output information of the control means, and are selected. Second selecting means for outputting the state of the selected bit to the decoder;
The state of the shift register before the center excluding the first bit and the center bit of the shift register and the information of the control means are inputted, and the bits of the shift register corresponding to the information output from the control means are inputted. First counting means for outputting information corresponding to the polarity of the shift register and the center bit to the decoder, the state of the shift register after the center excluding the last bit and the center bit of the shift register, and the control means Second counting means for receiving as input the information corresponding to the polarity of the bit of the shift register corresponding to the information output from the control means and the polarity of the center bit to the decoder; The state of the shift register selected by the second selecting means, the output information of the first and second counting means, and the control clock signal are inputted, and the central clock is inputted. A decoder for outputting an output corresponding to the amount of phase shift of the shift register to the judging means, and a pattern for inputting a bit state near the center bit of the shift register and outputting information corresponding to the bit pattern near the center bit to the judging means. A decoder and a signal of a state of a bit at the center of the shift register are written into the first and second counting means through the shift register.
First delay means for delaying the time until the signal is processed by the decoder and output from the determination means; and input information of the pattern decoder, output signal of the decoder, and control clock signal. Determining means for outputting information for delaying the phase of the center bit to the second delay means, and information of the determining means and an output signal of the first delay means are input and correspond to the information of the determining means. And a second delay means for outputting a signal obtained by delaying the output signal of the first delay means. 5. The method according to claim 1, wherein
In each counting means, the state of the shift register is input,
A write compensation circuit which counts magnetization reversals and outputs information on whether the number is an odd number or an even number to a decoder. 6. A magnetic storage device using the write compensation circuit according to claim 1.