JP3099849B2 - Recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording apparatus used in a device for processing digital signals such as a digital VTR.

[0002]

2. Description of the Related Art In a magnetic recording apparatus such as a VTR, a head goes off a track during reproduction, so that a head output is reduced and an error is increased so that a normal screen cannot be reproduced. Therefore, it is necessary for the head to accurately follow the target track, that is, to maintain the tracking of the head. Particularly, in a home digital VTR or the like, the track is narrowed in order to perform recording for a long time, and it is required to maintain the head tracking more accurately.

[0003] As means for detecting the deviation of the tracking of the head, the crosstalk of the pilot signals from the preceding and succeeding tracks is compared by using the pilot signal of each track, so that the tracking of the head can be performed before or after the tracking. There is the following method for detecting whether the position is shifted.

The recording signal is divided into three types of F0 and F shown in FIG.
1. Modulation is performed at the time of recording so as to have the frequency characteristics of the F2 pattern. The modulation to the F0 pattern is performed at an amplitude level (hereinafter referred to as a frequency) at the frequencies f1 and f2 of the recording signal.
Portion of a small a component), i.e. with a notch
It is done like this . The modulation to the F1 pattern is performed by f
In one frequency, fractional frequency component is greater, i.e. has a pilot signal, is performed to have a notch at a frequency of f2. Modulation of the F2 pattern, f
It has a Oite notch to 1 of frequency, you on the frequency of f2
It is made to have a pilot signal to have.

A recording signal is modulated and recorded so that the pattern becomes F0, F1, F0, F2 for each track as shown in FIG. When the F0 pattern is reproduced, the F
1, due to the crosstalk of the pilot signal from the F2 pattern, there are peaks in the frequency components of f1 and f2. When the head deviates from the center of the F0 pattern and shifts to the side of the F1 pattern, the crosstalk of the pilot signal from the F1 pattern becomes larger than the crosstalk from the F2 pattern, and as a result, the frequency component of f1 of the reproduced signal becomes larger, The frequency component of f2 becomes smaller. And conversely
When the head is shifted to the F2 pattern side, the F2 pattern
The crosstalk of these pilot signals from the F1 pattern
Is greater than the crosstalk of the
The frequency component of f2 increases, and the frequency component of f1 decreases.
Disappears. Bandpass filter for extracting the frequency component of f1
And a band-pass filter for extracting the frequency component of f2
The head is positioned at the body by comparing both outputs.
Side can be determined from the position. Also,
Switches detect crosstalk from adjacent tracks,
The frequency component inherent in the reproduced signal is
Prevent interfering with Stoke detection.

Conventionally, such F0, F1 and F2 patterns are performed by controlling the connection of 0 and 1 in a binary sequence to be recorded. Hereinafter, this method will be described. First, input data is transmitted every m bits (m:
(Even number), and a bit of 0 is added to the head to input to the precoder.
I modulated. Similarly, one bit is added to the head of the input data, input to the precoder, and subjected to interleaved NRZI modulation. The characteristic of the precoder is expressed by (Equation 1), which is used for performing a known partial response detection at the time of decoding, and when the polarity of the special bit is inverted, the polarity inversion is propagated as shown in (Equation 1). By doing so, the change of the frequency characteristic due to the change of the polarity of the special bit acts. The inserted 0 or 1 bit is hereinafter referred to as a special bit.

[0007]

## EQU1 ## b _k = _ak + b _k-2 (+ is exclusive OR) where { _ak } is a precoder input data sequence,
{B _k } is a precoder output data sequence. Extract the frequency component of the precoder output and set the special bit to 0
The frequency component of the precoder output when the special bit is 1 and the frequency component of the precoder output when the special bit is 1 are compared, and the precoder output closer to the desired frequency characteristic is set as the output of the recording device, so that the output data having the desired frequency characteristic Get the series.

FIG. 2 shows an example of an input data sequence, a special bit, and an output data sequence when interleaved NRZI is performed when m = 10. By inverting the polarity of the special bit, the polarity of the next bit following the special bit is inverted according to (Equation 1). By reversing the polarity of the next bit following the special bit, the polarity of the next bit following the next bit following the special bit is reversed. In this way, by reversing the polarity of the special bit,
The polarity of the odd-numbered bit counted from the special bit is inverted. This inversion continues until the odd-numbered bit counted from the special bit is a new special bit. That is, by inverting the polarity of a special bit, the polarity of the odd-numbered bit counted from the special bit is inverted by m. A bit that is inverted by inverting the polarity of the special bit is hereinafter referred to as an effective bit of the special bit. (M + 1)
Since the number of the bit is a new special bit C, the inversion does not propagate. The bit that is inverted when the special bit A is inverted is the (m + 1) bit indicated by ●.

FIG. 10 shows a block diagram of a conventional recording apparatus. The input data is added with bit 0 at the beginning by a 0 precoder 51 and subjected to precoding. Similarly, the input data is pre-coded by adding a bit 1 to the head by one precoder 52. The output of the 0 precoder 51 is input to the frequency component extraction circuit 53 for every (m + 1) bits, and the frequency component of the data is extracted. The output of one precoder 52 is input to the frequency component extraction circuit 54 for every (m + 1) bits, and the frequency component of the data is extracted. The output of the frequency component extraction circuit 53 and the output of the frequency component extraction circuit 54 are input to the comparison circuit 55, and the polarity of the special bit closer to the desired frequency characteristic is selected.
The outputs of the 0 precoder 51 and the 1 precoder 52 are input to the output selection circuit 56, and the data precoded by the special bit determined by the comparison circuit 55 is output.

In the conventional recording apparatus having the above configuration,
The frequency characteristics of data obtained by precoding a total of (m + 1) bits of the input m bits and the special bit added at the head are obtained by the frequency component extraction circuits 53 and 54.

[0011]

However, in the above-described method of extracting a frequency component in units of (m + 1) bits and determining a special bit, the number of effective bits is only m / 2 + 1 per m. The remaining m / 2 bits have already been determined by the previous special bits. Therefore, the difference in the frequency component due to the change of the special bit is small, and it is difficult to obtain better characteristics, that is, to obtain a frequency characteristic with a large notch.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a recording apparatus that generates a notch portion and a pilot signal with better characteristics in consideration of the above-mentioned conventional problems.

[0013]

According to the present invention, a one-bit zero is added to every m bits of an input data sequence, and a one-bit one is added to a sequence obtained by interleaved NRZI modulation and every m bits of the input data sequence. In two sequences obtained by addition and interleaved NRZI modulation ,
Bit extraction means for extracting and outputting bits whose bit polarities are inverted when bit 0 is added and bit 1 is added, and N frequency components for the output of the bit extraction means And an output selecting means for selecting one of the two series whose frequency components increase or decrease more based on at least these extracted components and outputting an output data series. It is a recording device.

[0014]

According to the present invention, in the above configuration, a special bit is inserted for every m bits of the input data sequence, interleaved NRZI modulation is performed, and a data sequence with N frequency components increased or decreased is output.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

First, the concept of the present invention will be described. FIG.
4 shows a relationship between an input data sequence and a precoder output sequence in interleaved NRZI modulation. One special bit is inserted for every m bits of the input data sequence. The input data sequence is precoded by the precoder according to (Equation 1). Therefore, when the polarity of the special bit is inverted, the even-numbered bit counted from the special bit is inverted. When the polarity of the special bit A is inverted, the even-numbered bits from the special bit A are inverted. However, the bits subsequent to the special bit C are determined by the special bit C. There are only m + 1 bits of ● bits of the precoder output sequence in FIG. The bit of ○ has no effect even if the polarity of the special bit A is inverted. Conventionally, a frequency component is extracted in units of (m + 1) bits (one word) starting from a special bit to determine a special bit. According to this method, when the polarity of the special bit A is inverted, attention is paid to (m +
1) Among the bits, the polarity of m / 2 + 1 bits represented by ● is inverted, but the polarity of m / 2 bits represented by ○ does not change. That is, the m / 2 bits are fixed bits that are not changed by the special bit A. By the presence of the fixed bits, the change of the frequency component due to the inversion of the special bit is inhibited,
As a result, it becomes difficult to obtain a desired frequency characteristic. Also, the m / 2 bit of the next word has a bit whose polarity is inverted by inverting the polarity of the special bit A, but this section is not taken into account in the calculation of the frequency component. Therefore, by calculating the frequency component only for the special bit and the bit affected by the special bit, the change in the polarity of the special bit can be made larger, the change in the frequency component becomes larger, and the characteristics are better. Notches or pilots can be generated. In FIG. 2, the special bit A is calculated by calculating the frequency component of only the
Determine the polarity of According to this method, the number of bits for calculating the frequency component is (m + 1) bits unchanged from the conventional one.
The circuit scale of the frequency component calculation does not change. In addition, since the special bit is inverted, all bits used for frequency component extraction are inverted.
In this case, it is also necessary to invert the precode data at the time of (1), and it is not necessary to obtain both precode data.

(Embodiment 1) FIG. 1 is a block diagram of Embodiment 1 of the present invention. The configuration and operation will be described below. The bit extracting circuit 1 (bit extracting means) adds 1 bit of 0 to every m bits of the input data sequence, and adds 1 bit of 1 to every m bits of the input data sequence and the sequence obtained by the interleaved NRZI modulation to perform interleaving. In the two sequences obtained by the NRZI modulation, a case where the bit 0 is added and a case where the bit 1 is added, the sequence when the bit special bit is inverted and the special bit of the bit is 0 are special. This is a means for outputting a sequence when the bit is 1. The output when the special bit is 0 is input to the frequency component extraction circuit 2 (frequency component extraction means).
Frequency components are extracted. The output of the bit extraction circuit 1 when the special bit is 1 is input to the frequency component extraction circuit 3, and N frequency components when the special bit is 1 are extracted. The outputs of the frequency component extraction circuit 2 and the frequency component extraction circuit 3 are input to the comparison circuit 4.
The comparison circuit 4 compares the outputs of the frequency component extraction circuits 2 and 3 and determines a special bit closer to a desired frequency characteristic. The output selection circuit 5 (output selection means) selects and outputs an output sequence when the special bit of the bit extraction circuit 1 is 0 and an output sequence when the special bit is 1 according to the output of the comparison circuit 4.

Since the output of the bit extraction circuit 1 when the special bit is 0 and the output when the special bit is 1 are inverted, only one of them is output and the other is inverted. May be obtained by doing so.

(Embodiment 2) A case where the bit extraction circuit 1 is composed of a precoder 7 and a shift register 8 and the output selection circuit 5 is composed of a bit inversion circuit 10 will be described. FIG. 3 shows this block diagram. The input data sequence is input to the bit insertion circuit 6. In the bit insertion circuit 6, bit 0 is inserted every m bits. The output of the bit insertion circuit 6 is input to the precoder 7. As shown in FIG. 4, the precoding 7 is performed by taking an exclusive OR with the input two bits before. The output of the precoder 7 is input to a 2m + 1-stage shift register 8. One bit of precoded data is input to the shift register every clock. As shown in FIG. 5, when a special bit is input to the last stage of the shift register 8, the output of the odd-numbered stage from the input side is input to the inverting circuit 9 and the frequency extracting circuit 2. At this time, the effective bits of the special bits are at odd-numbered stages of the shift register 8. The inverting circuit 9 inverts the input to obtain precoded data when the special bit is 1, and outputs the data to the frequency extracting circuit 3. The frequency extraction circuit 2 and the frequency extraction circuit 3 respectively extract N frequency components of the precoded data when the special bit is 0 and the precoded data when the special bit is 1, and input the N frequency components to the comparison circuit 4. Is done. Comparison circuit 4
So when the special bit is 0 and the special bit is 1
The polarity of the special bit is determined by comparing the frequency components at the time. The output of the last stage of the shift register 8 is input to the inversion circuit 10. Since the output of the last stage of the shift register 8 is precoded data when the special bit is 0, it is necessary to invert this output when the special bit is 1. The inverting circuit 10 outputs the output of the last stage of the shift register 8 as it is when the special bit is determined to be 0, and inverts and outputs when the special bit is 1. In this way, compared to the conventional
A recording apparatus having better characteristics can be realized.

In the bit insertion circuit, bit 0 is inserted every m bits, but bit 1 may be inserted.

In the output selection circuit 5, when the special bit is 1 and the special bit is 1 for the precoded data, the output is inverted and output. May be prepared, and selected and output according to the polarity of the determined special bit.

(Embodiment 3) In the embodiment 2, the valid bits of the special bits are extracted from the precoded data. As can be seen from FIG. 2, the effective bits at the time of precoding are the odd-numbered bits of the input data and the even-numbered bits of the bits input before, assuming that the data is input in m bits in parallel. You can see that there is.
That is, special bits and valid bits can also be extracted by applying the precode shown in FIG. 7 to the even-numbered bits of the previously input data and the odd-numbered bits of the input data. it can. The above configuration will be described. FIG. 6 shows this block diagram.

The data input in m-bit parallel is input to the bit extraction circuit 1. The input data is divided into an odd-numbered bit and an even-numbered bit by an odd / even dividing circuit 20, and the even-numbered bit is further divided by a delay circuit 21.
The data is delayed by one processing period and input to the precoder 22. The precoder 22 precodes the special bit as 0. FIG. 7 shows the configuration of the precoder. The precoded data is input to the frequency component extraction circuit 2,
The N frequency components when the special bit is precoded with 0 are extracted. Also, it is input to the inversion circuit 23. The inverting circuit 23 inverts the data pre-coded with the special bit being 0, makes the data pre-coded with the special bit being 1, and inputs the data to the frequency component extracting circuit 3. The frequency component extraction circuit 3 extracts N frequency components of the data precoded with the special bit being 1. The outputs of the frequency component comparing circuits 3 and 4 are
Is input to The comparison circuit 4 determines the polarity of the special bit by comparing the frequency component and the DC component of the data precoded with the special bit being 0 and the data precoded with the special bit being 1. The output of the precoder 22 is also input to the output selection circuit 5. The input of the odd-numbered bits of the output selection circuit 5 is delayed by one processing period by the delay circuit 24. The input of the even-numbered bits of the output selection circuit 5 and the output of the delay circuit 24 are input to the output synthesis circuit 25. The output synthesizing circuit 25 rearranges the odd bits and the even bits in order. When the special bit is 0, the output is directly performed. When the special bit is 1, the output is inverted and output. In this way, when the input is a parallel input, a small-scale and high-speed circuit can be realized.

In the precoder 22, the precoding is performed by setting the special bit to 0, but the precoding may be performed by setting the special bit to 1.

The precoded data when the special bit is 1 is obtained by inverting the precoded data when the special bit is 0. However, two sets of a precoder and a shift register are used, and the special bit is obtained. Precoded data may be obtained independently for 0 and 1 respectively.

In the output selection circuit 5, when the special bit is 0 and the special bit is 1 for the precoded data, the special bit is inverted and output. May be prepared, and selected and output according to the polarity of the determined special bit.

Each means of the present invention can be realized by software using a computer, or can be realized by using a dedicated hardware circuit having each function.

[0028]

As is apparent from the above description,
The recording apparatus of the present invention inserts a special bit for every m bits of an input data sequence,
Since ZI modulation is performed and a data sequence in which the number of N frequency components is increased or decreased is output, there is an advantage that notch and pilot signals with better characteristics can be generated. Therefore, it has great utility in fields such as home digital VTRs where narrow tracks are required for long-time recording.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a precoder input sequence and a precoder output sequence.

FIG. 3 is a block diagram of the second embodiment.

FIG. 4 is a configuration diagram of the precoder.

FIG. 5 is a configuration diagram of the shift register.

FIG. 6 is a block diagram of the third embodiment.

FIG. 7 is a configuration diagram of a precoder according to the second embodiment.

FIG. 8 is a frequency characteristic diagram of the recording waveform.

FIG. 9 is a track pattern diagram of the recording waveform.

FIG. 10 is a block diagram of a conventional recording apparatus.

[Explanation of symbols]

 1 bit extraction circuit (means) 2 frequency component extraction circuit (means) 3 frequency component extraction circuit (means) 4 comparison circuit (means) 5 output selection circuit (means)

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-4-255969 (JP, A) JP-A-4-268258 (JP, A) JP-A-5-327515 (JP, A) JP-A-5-327515 244558 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20/10 G11B 20/14 G11B 5/09 G11B 15/467 H03M 5/06 H03M 7/14

Claims (3)

(57) [Claims] 1. A sequence obtained by adding one bit of 0 to every m bits of an input data sequence, and a sequence obtained by interleaved NRZI modulation and a one bit of 1 to each m bits of the input data sequence, and performing interleaved NRZI modulation. Bit extracting means for extracting and outputting bits in which the polarity of the bits is inverted between a case where bit 0 is added and a case where bit 1 is added, in the two obtained sequences; Frequency component extracting means for extracting N frequency components with respect to the output, and selecting one of the two sequences in which the frequency component increases or decreases more based on at least these extracted components to output data. A recording apparatus comprising: output selection means for outputting a sequence. 2. A bit extracting means, comprising: a bit 0 inserting means for inserting 0 bits for every m bits of the input data sequence; a precoder for performing NRZI modulation on an output of the bit 0 inserting means; and an output of the precoder. 2. The recording apparatus according to claim 1, further comprising: a shift register for delaying the recording. 3. A bit extracting means for delaying an even-numbered bit of m bits of the input data sequence,
2. The recording apparatus according to claim 1, further comprising: a precoder for adding interleaved NRZI modulation by adding 0 or 1 bit to the odd-numbered bits of the input data sequence and the output of the delay unit.