JPH06310866A - Multilayer wiring board and its manufacture - Google Patents

Multilayer wiring board and its manufacture

Info

Publication number
JPH06310866A
JPH06310866A JP9731293A JP9731293A JPH06310866A JP H06310866 A JPH06310866 A JP H06310866A JP 9731293 A JP9731293 A JP 9731293A JP 9731293 A JP9731293 A JP 9731293A JP H06310866 A JPH06310866 A JP H06310866A
Authority
JP
Japan
Prior art keywords
film
layer
forming
conductor
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9731293A
Other languages
Japanese (ja)
Other versions
JP3080508B2 (en
Inventor
Terutake Kato
輝武 加藤
Hirotake Nakayama
浩偉 仲山
Yoshiko Iwamoto
由子 岩本
Satoru Hashimoto
悟 橋本
Mamoru Morita
守 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9731293A priority Critical patent/JP3080508B2/en
Publication of JPH06310866A publication Critical patent/JPH06310866A/en
Application granted granted Critical
Publication of JP3080508B2 publication Critical patent/JP3080508B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To prevent the reaction of a wiring layer and an insulating layer without increasing manufacturing processes in a multilayered wiring board wherein the wiring interlayer insulating film is an organic polymer insulating film, and realize a multilayered wiring board of high reliability. CONSTITUTION:On a ceramic board 1, wiring conductor (copper) 3 whose surface is flat is formed by electrolytic plating, via a base conductor film 2. The wiring conductor 3 surface is covered with a reaction preventing film 4 by nonelectrolytic plating, and the film 4 surface is covered with an anti-oxidant film 8, which is desirably formed by, e.g. substitution plating of gold. Since the surface layer part of the reaction preventing film 4 as the base is dissolved and the left part is plated with gold, so that a special surface treatment for cleaning the surface is made unnecessary. Further a polyimide interlayer insulating film 6 is formed, holes for wiring connection are formed, and a base conductor film 7 is formed. The forming processes from the wiring conductor (copper) 3 to the base conductor film 7 are repeated by the number of time corresponding with the number of lamination layers of wiring.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多層配線基板及びその
製造方法に係り、特に例えば交換機や電子計算機に用い
られるマルチチップモジュ−ル等のようにLSIチップ
を多数実装する高密度実装配線に好適な多層配線基板及
びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board and a method for manufacturing the same, and more particularly to a high-density mounting wiring for mounting a large number of LSI chips such as a multi-chip module used in an exchange or a computer. The present invention relates to a suitable multilayer wiring board and a manufacturing method thereof.

【0002】[0002]

【従来の技術】電子計算機、交換機等の大容量化、高速
化等の処理能力向上のため、複数のLSIベアチップや
微小回路部品を高密度実装するマルチチップモジュ−ル
実装技術の開発が進展している。この種のモジュ−ルの
実装に供される多層配線基板としては、小誘電率絶縁層
と低抵抗配線層とを有する多層配線基板を用いることが
必須の要件である。このような条件を満足するものとし
て銅を配線層、ポリイミド絶縁層を層間絶縁膜とする多
層配線基板が知られている。なお、この種の多層配線基
板を、ここでは銅−ポリイミド多層配線基板と称する。
2. Description of the Related Art Development of multi-chip module mounting technology for high-density mounting of a plurality of LSI bare chips and minute circuit components is progressing in order to improve processing capacity such as increasing capacity and speed of electronic computers and exchanges. ing. As a multilayer wiring board used for mounting this type of module, it is essential to use a multilayer wiring board having a small dielectric constant insulating layer and a low resistance wiring layer. A multi-layer wiring board that uses copper as a wiring layer and a polyimide insulating layer as an interlayer insulating film is known to satisfy such conditions. This type of multilayer wiring board is referred to as a copper-polyimide multilayer wiring board here.

【0003】以下、この銅−ポリイミド多層配線基板を
代表例とする従来の基板構造及びその製造方法につい
て、製造工程図を示した図2にしたがって説明する。図
2は、図2(a)に示すように、セラミック基板1上に
無電解銅めっき、又はクロム/銅スパッタにより下地導
体膜2を形成する。
A conventional board structure, which is a representative example of this copper-polyimide multilayer wiring board, and a method of manufacturing the same will be described below with reference to FIG. In FIG. 2, as shown in FIG. 2A, a base conductor film 2 is formed on a ceramic substrate 1 by electroless copper plating or chromium / copper sputtering.

【0004】次に図2(b)に示すように、下地導体膜
2上の配線形成領域2aを除いた部分2b上にレジスト
パターン5を形成した後、配線形成領域2aに電解銅め
っきにより銅導体層3を形成し、さらにその上に電解ク
ロムめっきにより反応防止膜4(銅−ポリイミドの反応
防止)を積層し配線層を得る。
Next, as shown in FIG. 2B, a resist pattern 5 is formed on a portion 2b of the underlying conductor film 2 excluding the wiring formation region 2a, and then copper is formed on the wiring formation region 2a by electrolytic copper plating. A conductor layer 3 is formed, and a reaction preventive film 4 (copper-polyimide reaction preventive) is further laminated thereon by electrolytic chromium plating to obtain a wiring layer.

【0005】次に図2(c)に示すように、絶縁層形成
のためレジストパターン5を除去した後、露出した不要
な下地導体膜2bをエッチングにより除去し、配線層を
覆うように全面にポリイミド絶縁層6を形成する。
Next, as shown in FIG. 2C, after removing the resist pattern 5 for forming an insulating layer, the exposed unnecessary underlying conductor film 2b is removed by etching, and the entire surface is covered so as to cover the wiring layer. A polyimide insulating layer 6 is formed.

【0006】そして、図2(d)に示すように、同一基
板上に形成された配線層間を低接続抵抗で接続し、第2
の配線層を形成するため、先ず配線層上のポリイミド絶
縁層6に穴を開け、露出した反応防止膜4の主要部をエ
ッチングにより除去し、さらに露出した導体層3の表層
部の酸化物除去を行った後、露出した接続部からポリイ
ミド絶縁層6上に第2の配線層の下地導体膜7を形成す
る。
Then, as shown in FIG. 2D, the wiring layers formed on the same substrate are connected with a low connection resistance,
In order to form the wiring layer, first, a hole is made in the polyimide insulating layer 6 on the wiring layer, the exposed main portion of the reaction preventive film 4 is removed by etching, and the oxide on the exposed surface portion of the conductor layer 3 is removed. After that, the base conductor film 7 of the second wiring layer is formed on the polyimide insulating layer 6 from the exposed connection portion.

【0007】次に図2(b)〜図2(d)工程を繰返す
ことにより、図2(e)に示したポリイミド絶縁層6を
層間絶縁膜とし、銅を配線層とする3層配線構造の多層
配線基板が形成される。
Next, by repeating the steps of FIGS. 2 (b) to 2 (d), a three-layer wiring structure in which the polyimide insulating layer 6 shown in FIG. 2 (e) is used as an interlayer insulating film and copper is used as a wiring layer Is formed.

【0008】なお、この種の技術に関連するものとして
は、例えば、日経マイクロデバイス1989年2月号、
第50頁〜第60頁が挙げられる。
[0008] Incidentally, as a technique related to this type of technology, for example, Nikkei Microdevices February 1989 issue,
Pp. 50-60.

【0009】[0009]

【発明が解決しようとする課題】しかし、上記従来の技
術によれば以下に指摘するような課題がある。 すなわち、銅−ポリイミド反応防止膜4は銅導体3の
表面にのみ形成され、その側面には形成されない。それ
故、例えばカルボルキシル基を含むポリイミドを用いた
場合、カルボルキシル基が酢酸化するため、銅導体3と
ポリイミド絶縁層6とが直接接触している部分では、こ
の酢酸により銅−ポリイミド反応が生じてしまう。した
がって、銅導体2の側面とポリイミド絶縁層6の接触を
防がなくてはならない。
However, the above-mentioned conventional techniques have the following problems. That is, the copper-polyimide reaction preventive film 4 is formed only on the surface of the copper conductor 3 and not on the side surface thereof. Therefore, for example, when a polyimide containing a carboxyl group is used, the carboxyl group is acetic acid, so that in the portion where the copper conductor 3 and the polyimide insulating layer 6 are in direct contact, the acetic acid causes a copper-polyimide reaction. I will end up. Therefore, contact between the side surface of the copper conductor 2 and the polyimide insulating layer 6 must be prevented.

【0010】さらに図2(d)に示したように、配線
層間接続部形成時おいて、反応防止膜4のエッチング除
去、露出した銅導体3表層部の酸化膜除去工程が必要と
なり、この時、反応防止膜4のオ−バ−エッチングが生
じ易いという問題がある。
Further, as shown in FIG. 2D, a step of etching away the reaction preventive film 4 and a step of removing the oxide film on the exposed surface portion of the copper conductor 3 are required at the time of forming the wiring interlayer connection portion. However, there is a problem that over-etching of the reaction preventive film 4 is likely to occur.

【0011】また、セラミック基板上に直接形成する
配線層では、セラミック基板表面の凹凸が銅導体3表面
の凹凸に影響し、これにより凹の部分でその上に反応防
止膜4として形成するクロムの膜厚にむらが生じて薄い
ところが発生し、銅−ポリイミドが反応し易くなる。
Further, in the wiring layer formed directly on the ceramic substrate, the irregularities on the surface of the ceramic substrate affect the irregularities on the surface of the copper conductor 3, whereby the chromium formed on the concave portion as the reaction preventive film 4 is formed. The film thickness becomes uneven and a thin portion is generated, and the copper-polyimide easily reacts.

【0012】また、ポリイミド絶縁層6上に第2配線
層を形成する際に、下地導体膜7を形成するが、従来技
術の無電解めっきではポリイミド絶縁層6とめっき導体
7との密着性を得るためポリイミド絶縁表面を粗化する
工程が必要となり、工程数が増加する。
Further, the base conductor film 7 is formed when the second wiring layer is formed on the polyimide insulating layer 6, but in the conventional electroless plating, the adhesion between the polyimide insulating layer 6 and the plated conductor 7 is improved. In order to obtain it, a step of roughening the polyimide insulating surface is required, and the number of steps is increased.

【0013】また、めっきの代わりにスパッタでクロ
ム/銅下地導体膜(2、7)を形成する場合でもエッチ
ング等による工程数が増加し、高価なスパッタ装置も必
要となる。このため安価な配線基板を得るには、工程数
を増加させずに密着力を増加させる手法が必要となる。
Further, even when the chromium / copper base conductor film (2, 7) is formed by sputtering instead of plating, the number of steps such as etching is increased, and an expensive sputtering device is required. Therefore, in order to obtain an inexpensive wiring board, it is necessary to increase the adhesion without increasing the number of steps.

【0014】したがって、本発明の目的はこれら従来の
問題点を解決することにあり、その第1の目的は配線層
の表面及び側面をも含めて反応防止膜と酸化防止膜とを
順次被覆して2層構造とすることにより、配線層とポリ
イミド絶縁層との反応を防止し信頼性の高い多層配線基
板を実現することにあり、第2の目的は工程数を低減し
た製造方法を実現することにある。
Therefore, an object of the present invention is to solve these conventional problems, and the first object of the present invention is to sequentially coat a reaction preventing film and an antioxidant film including the surface and the side surface of a wiring layer. The purpose of the present invention is to realize a highly reliable multilayer wiring board by preventing the reaction between the wiring layer and the polyimide insulating layer by adopting a two-layer structure. The second purpose is to realize a manufacturing method with a reduced number of steps. Especially.

【0015】[0015]

【課題を解決するための手段】上記第1の目的は、セラ
ミック基板上の下地導体膜を介して形成された配線層の
表面及び側面に、反応防止膜と酸化防止膜とを積層被覆
し、層間絶縁膜として有機高分子絶縁層を形成して成る
多層配線基板により、達成される。有機高分子絶縁層と
しては、ポリイミドが最適であるが、その他例えば感光
性ポリイミド、ポリイミドシリコン、ラダーシリコン
(ポリラダーオルガノシロキサン)、ポリアミド等の周
知の有機絶縁材料が用いられる。以下の説明では、ポリ
イミドを代表例として説明する。
A first object of the present invention is to laminate a reaction-preventing film and an anti-oxidizing film on the surface and the side surface of a wiring layer formed on a ceramic substrate via an underlying conductor film, This is achieved by a multilayer wiring board formed by forming an organic polymer insulating layer as an interlayer insulating film. Polyimide is most suitable for the organic polymer insulating layer, but other well-known organic insulating materials such as photosensitive polyimide, polyimide silicon, ladder silicon (poly ladder organosiloxane), and polyamide are used. In the following description, polyimide will be described as a typical example.

【0016】そして好ましくは、ポリイミドからなる層
間絶縁膜上に下地導体膜を介して新たな配線層の形成を
繰返し、第2の配線層、第3の配線層といった多層配線
層を積層するに際しては、平坦化された層間絶縁膜上
に、絶縁微粒子を含有した有機高分子絶縁膜を微粒子径
より薄く形成して、微粒子を表面に固定することにより
絶縁層表面を凹凸化することである。この表面凹凸化に
より、新たな配線層を形成する際に設ける下地導体膜
は、層間絶縁膜に強固に接続され、接着性が格段に向上
する。表面凹凸化の代換え技術として、絶縁層表面を研
磨する方法もあるが、それよりも微粒子を固定する方が
簡便で好ましい。
Further, preferably, when a new wiring layer is repeatedly formed on the interlayer insulating film made of polyimide with the underlying conductor film interposed therebetween, when laminating the multilayer wiring layers such as the second wiring layer and the third wiring layer. That is, an organic polymer insulating film containing insulating fine particles is formed thinner than the fine particle diameter on the flattened interlayer insulating film, and the fine particles are fixed to the surface to make the surface of the insulating layer uneven. Due to the surface unevenness, the underlying conductor film provided when forming a new wiring layer is firmly connected to the interlayer insulating film, and the adhesiveness is remarkably improved. As a substitute technique for making the surface uneven, there is a method of polishing the surface of the insulating layer, but fixing the fine particles is easier and more preferable than that.

【0017】なお、絶縁微粒子としては、絶縁物であれ
ばいずれのものでもよいが、ポリイミド等の層間絶縁膜
を形成する樹脂の微粒子を用いることが望ましく、平均
粒径1〜5μm程度のものが使用される。
As the insulating fine particles, any insulating material may be used, but it is preferable to use fine particles of resin such as polyimide for forming an interlayer insulating film, and those having an average particle diameter of about 1 to 5 μm. used.

【0018】また、反応防止膜としては、ポリイミド等
の層間絶縁膜と反応し難いめっき導体膜が用いられ、例
えば膜厚1〜5μm程度のニッケル、クロム等の無電
解、もしくは電解めっきが用いられるが、実用的には無
電解ニッケルめっきが特に好ましい。
As the reaction preventive film, a plated conductor film such as polyimide which is difficult to react with the interlayer insulating film is used. For example, electroless plating such as nickel or chromium having a film thickness of 1 to 5 μm or electrolytic plating is used. However, in practice, electroless nickel plating is particularly preferable.

【0019】また、酸化防止膜としては、耐酸化性の導
体であればよく、通常は金の薄膜(例えば0.5μm以
下)が用いられる。後述する製造方法との関係(工程簡
略化と信頼性の向上)から特に無電解置換めっきが好ま
しい。
As the anti-oxidation film, any oxidation resistant conductor may be used, and normally a gold thin film (for example, 0.5 μm or less) is used. Electroless displacement plating is particularly preferable in view of the relationship with the manufacturing method described later (process simplification and reliability improvement).

【0020】上記第2の目的は、セラミック基板上に
下地導体膜を介して電解めっきにより第1の配線導体層
を形成する工程と、前記導体層上に反応防止膜と酸化
防止膜とを、めっき法により順次積層し、前記第1の配
線導体層の表面全体をこれらの2層膜で被覆する工程
と、全面に層間絶縁膜として有機高分子絶縁層を形成
する工程と、前記第1の配線導体層上の層間絶縁膜に
回路形成用の開口部を形成する工程と、前記回路形成
用の開口部を含む層間絶縁膜上に下地導体膜を介して第
2の配線導体層を形成する工程とを有すると共に、引
き続き前記乃至の工程を多層配線の積層数に見合っ
た回数分だけ繰返す工程とを有して成る多層配線基板の
製造方法により、達成される。
The second object is to provide a step of forming a first wiring conductor layer on a ceramic substrate through an underlying conductor film by electrolytic plating, and a reaction prevention film and an oxidation prevention film on the conductor layer. A step of sequentially stacking by a plating method and covering the entire surface of the first wiring conductor layer with these two-layer films; a step of forming an organic polymer insulating layer as an interlayer insulating film on the entire surface; A step of forming an opening for forming a circuit in an interlayer insulating film on the wiring conductor layer, and forming a second wiring conductor layer on the interlayer insulating film including the opening for forming the circuit via a base conductor film. And a step of repeating the above-mentioned steps by the number of times corresponding to the number of laminated multilayer wirings.

【0021】そして好ましくは、上記の層間絶縁膜と
して有機高分子絶縁層を形成する工程の後に引き続い
て、絶縁微粒子を含有した有機高分子絶縁膜を微粒子
径より薄く形成して、微粒子を表面に固定することによ
り絶縁層表面を凹凸化する工程を付加して成る多層配線
基板の製造方法により、達成される。
Preferably, subsequently to the step of forming the organic polymer insulating layer as the interlayer insulating film, an organic polymer insulating film containing insulating fine particles is formed thinner than the fine particle diameter, and the fine particles are formed on the surface. This is achieved by a method for manufacturing a multilayer wiring board, which includes a step of making the surface of the insulating layer uneven by fixing.

【0022】[0022]

【作用】本発明の作用を銅−ポリイミド多層基板を代表
例として説明すると、銅配線導体層上に反応防止膜と酸
化防止膜とを、めっき法により順次積層し、前記第1の
銅配線導体層の表面全体をこれらの2層膜で被覆する
が、先ず、反応防止膜はめっき法により形成するため、
銅配線導体層の全表面を一様に覆うことができ、銅配線
導体層とポリイミドとは直接接触することがないので、
両者の反応を完全に防止することができる。
The operation of the present invention will be described with reference to a copper-polyimide multilayer substrate as a typical example. A reaction preventing film and an oxidation preventing film are sequentially laminated on a copper wiring conductor layer by a plating method to form the first copper wiring conductor. The entire surface of the layer is covered with these two-layer films. First, since the reaction preventive film is formed by the plating method,
Since the entire surface of the copper wiring conductor layer can be uniformly covered and the copper wiring conductor layer and the polyimide do not come into direct contact with each other,
Both reactions can be completely prevented.

【0023】次に、酸化防止膜の形成であるが、これも
めっき法により形成するため、特に好ましい置換めっき
法によれば、下地となる反応防止膜の表層部が酸化され
ても、めっき形成時に反応防止膜の表層部が溶解する一
方から酸化防止膜がめっきされて来るので、酸化防止膜
のめっきの進行と共に反応防止膜表層部の酸化物は必然
的に除去される。したがって、特別のエッチング工程を
施さずに反応防止膜の表層部を除去し、清浄化すること
ができる。
Next, regarding the formation of an anti-oxidation film, since this is also formed by a plating method, a particularly preferred displacement plating method forms a plating film even if the surface layer portion of the reaction-preventing film which is the base is oxidized. Since the antioxidant film is plated from the one side where the surface layer of the reaction preventive film is dissolved, the oxide in the surface layer part of the reaction preventive film is inevitably removed as the plating of the antioxidant film progresses. Therefore, the surface layer portion of the reaction preventive film can be removed and cleaned without performing a special etching process.

【0024】さらに、従来は配線層間接続部形成時に、
反応防止膜エッチングや銅導体表面処理工程を必要とし
ていたが、本発明では何れも不要となり、配線層間接続
部形状不良の解消、また配線層間接続部形成工程が簡略
化できる。
Further, conventionally, when forming a wiring interlayer connecting portion,
Although the reaction preventive film etching and the copper conductor surface treatment process are required, none of them are required in the present invention, and the wiring interlayer connection portion shape defect can be eliminated, and the wiring interlayer connection portion forming step can be simplified.

【0025】さらに、配線層間絶縁層上に絶縁微粒子を
含有した有機高分子絶縁膜を微粒子径より薄く形成して
微粒子を表面に固定することにより、層間絶縁層表面を
容易に凹凸化することができ、その結果、第2の配線層
形成時に下地導体層を例えば無電解めっきで形成する際
には、この表面凹凸により配線層間絶縁層に対する無電
解めっきの密着力を、より増加させることができる。
Further, by forming an organic polymer insulating film containing insulating fine particles thinner than the fine particle diameter on the wiring interlayer insulating layer and fixing the fine particles on the surface, the surface of the interlayer insulating layer can be easily roughened. As a result, when the underlying conductor layer is formed by, for example, electroless plating when forming the second wiring layer, the adhesion of the electroless plating to the wiring interlayer insulating layer can be further increased due to the surface irregularities. .

【0026】また、セラミック基板上の配線層を電解め
っきで形成することにより、セラミック基板表面の凹凸
を平坦化でき反応防止膜の被覆性がより向上し、結果と
して銅−ポリイミド反応を効果的に防止できる。
Further, by forming the wiring layer on the ceramic substrate by electrolytic plating, the irregularities on the surface of the ceramic substrate can be flattened, and the coverage of the reaction preventive film can be further improved, resulting in an effective copper-polyimide reaction. It can be prevented.

【0027】[0027]

【実施例】以下、図面にしたがって本発明の一実施例を
説明する。 〈実施例1〉図1は、本発明の一実施例となる多層配線
基板の構造及び製造工程を示す工程断面図である。な
お、ここでは、本発明の特徴点を明瞭とするため、必要
に応じ従来例を示した図3及び図4を補助図面として使
用する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. <Embodiment 1> FIG. 1 is a process sectional view showing the structure and manufacturing process of a multilayer wiring board according to an embodiment of the present invention. Here, in order to clarify the characteristic point of the present invention, FIGS. 3 and 4 showing conventional examples are used as auxiliary drawings as necessary.

【0028】図1(a)に示した工程により、セラミッ
ク基板1上に、周知のスパッタ成膜法にしたがい膜厚
0.1μmのクロム層と膜厚0.1μmの銅層との2層
膜で構成される下地導体膜2を形成する。
By the process shown in FIG. 1A, a two-layer film including a chromium layer having a film thickness of 0.1 μm and a copper layer having a film thickness of 0.1 μm is formed on the ceramic substrate 1 according to a well-known sputtering film forming method. A base conductor film 2 composed of is formed.

【0029】次に、図1(b)に示した工程により、下
地導体膜2上の2aで示した第1の配線層形成領域を除
いた層間絶縁膜形成領域2bにレジストパターン5を形
成する。これに引き続き、セラミック基板1の表面凹凸
をめっき時のレベリング効果により平坦化し易い電解銅
めっきを行い、表面が平坦な膜厚5μmの銅導体3を形
成する。
Next, by the process shown in FIG. 1B, a resist pattern 5 is formed in the interlayer insulating film forming region 2b except the first wiring layer forming region 2a on the underlying conductor film 2. . Subsequent to this, electrolytic copper plating is performed to easily flatten the surface irregularities of the ceramic substrate 1 by the leveling effect at the time of plating to form a copper conductor 3 having a flat surface and a film thickness of 5 μm.

【0030】これに対して従来技術では、図3(a)に
示すように、セラミック基板1上に、スパッタ成膜法に
より、下地導体膜2としてクロム/配線導体層3として
銅/反応防止膜4としてクロムを順次成膜し、そらに配
線層形成用マスクとしてレジストパターン5を選択的に
形成する。次いで図3(b)に示すように、これらの3
層膜をエッチングにより配線分離し回路形成を行なう
が、この際スパッタ成膜法では、セラミック基板1の表
面の凹凸が、銅導体3の表面に下地のクロム2ではカバ
−できない凹凸が形成され、それが反応防止膜4の成膜
に大きく影響して、図示のように、成膜不良部(ポリイ
ミド−銅接触部)11が発生する。それ故、図3(c)
に示すように、層間絶縁膜6としてポリイミドを形成す
ると、反応防止膜4の成膜不良部並びにポリイミド−銅
接触部11が存在することから銅導体3の表面とポリイ
ミド6との反応は避けられない。
On the other hand, in the prior art, as shown in FIG. 3A, chromium is used as the base conductor film 2 / copper is used as the wiring conductor layer 3 / reaction preventive film is formed on the ceramic substrate 1 by the sputter deposition method. Chromium is sequentially formed as 4 and a resist pattern 5 is selectively formed thereon as a wiring layer forming mask. Then, as shown in FIG.
Wiring is separated from the layer film to form a circuit. In this case, in the sputtering film forming method, irregularities on the surface of the ceramic substrate 1 and irregularities that cannot be covered by the underlying chromium 2 are formed on the surface of the copper conductor 3. This greatly influences the film formation of the reaction preventive film 4, and as shown in the figure, a film formation defect portion (polyimide-copper contact portion) 11 occurs. Therefore, FIG. 3 (c)
As shown in FIG. 5, when polyimide is formed as the interlayer insulating film 6, the reaction between the surface of the copper conductor 3 and the polyimide 6 is avoided because the defective film forming portion of the reaction preventing film 4 and the polyimide-copper contact portion 11 exist. Absent.

【0031】次に、図1(c)の工程に示すように、レジ
ストパターン5を除去し、銅導体3をマスクとして層間
絶縁膜形成領域2bに露出した下地導体膜(クロム/銅
の2層膜)2をエッチング除去し、配線分離を行う。次
いで反応防止膜4として無電解めっきによりニッケルを
銅導体3の表面に2μm形成し、表面を完全にニッケル
めっきでカバ−する。この様にして反応防止膜4により
銅−ポリイミド反応を完全に防止することができる。
Next, as shown in the step of FIG. 1C, the resist pattern 5 is removed and the copper conductor 3 is used as a mask to expose the underlying conductor film (two layers of chromium / copper) in the interlayer insulating film formation region 2b. The film 2 is removed by etching to separate the wiring. Next, as the reaction preventing film 4, nickel is formed on the surface of the copper conductor 3 by 2 μm by electroless plating, and the surface is completely covered by nickel plating. In this way, the reaction preventing film 4 can completely prevent the copper-polyimide reaction.

【0032】次に図1(d)の工程に示すように、反応
防止膜4上に酸化防止膜8として置換めっきにより金を
0.1μm形成する。この工程は、本発明においては以
下に詳述するように工程を簡略化する上で特に重要な工
程である。
Next, as shown in the step of FIG. 1D, 0.1 μm of gold is formed as an antioxidant film 8 on the reaction preventive film 4 by displacement plating. In the present invention, this step is a particularly important step in simplifying the step as described in detail below.

【0033】従来の方法では図4(d)に示すように、
絶縁層6に層間配線接続用の穴を形成する時に、酸化膜
等を除去するため反応防止膜4及び銅導体3表面のエッ
チングを行なうが、その際、この図に見られるように反
応防止膜4のオーバーエッチング等の層間接続用の穴形
状に不良が発生し易い。これを改善するため、図4
(e)に示すように反応防止膜4のエッチング後に、ポ
リイミドからなる層間絶縁膜6を再度ウエット、又はド
ライエッチングにより穴の開口径を拡大し、クロムから
なる反応防止膜4を露出させていた。しかし、この方法
では銅導体3の表面が汚れたり、ポリイミド6の表面の
変質などにより、次の第2の配線層形成工程において下
地導体膜7が剥がれる不良が発生し易いという問題があ
った。
In the conventional method, as shown in FIG.
When the holes for connecting the interlayer wirings are formed in the insulating layer 6, the surface of the reaction preventive film 4 and the copper conductor 3 is etched to remove the oxide film and the like. At that time, as shown in this figure, the reaction preventive film is formed. 4 is likely to have a defect in the hole shape for interlayer connection such as overetching. To improve this, Fig. 4
As shown in (e), after the reaction-preventing film 4 was etched, the interlayer insulating film 6 made of polyimide was again wet or dry-etched to enlarge the opening diameter of the hole, and the reaction-preventing film 4 made of chromium was exposed. . However, this method has a problem that the base conductor film 7 is likely to be peeled off in the subsequent second wiring layer forming step due to contamination of the surface of the copper conductor 3 or alteration of the surface of the polyimide 6.

【0034】しかし、この実施例ではこれらの問題点を
解消するため図1(d)に示したように、反応防止膜4
上に酸化止膜8を置換めっきにより積層することで、従
来必須とされていた表面処理工程を無用とし、層間接続
穴形状不良を改善した。
However, in this embodiment, in order to solve these problems, as shown in FIG. 1D, the reaction preventive film 4 is formed.
By laminating the anti-oxidation film 8 on the upper side by displacement plating, the surface treatment step, which has been indispensable in the past, is made unnecessary and the defective shape of the interlayer connection hole is improved.

【0035】つまり、本実施例の酸化止膜8として形成
する金の置換めっきによれば、下地となる反応防止膜4
の表層部が溶解するにしたがい、その跡に金めっきが形
成されることから、反応防止膜4の表層部が酸化されて
いたとしても、金めっき時の自己清浄化作用によりに実
質的にそれらの酸化物は溶解除去される。
That is, according to the displacement plating of gold formed as the anti-oxidation film 8 of this embodiment, the reaction preventive film 4 serving as the base is formed.
Since the gold plating is formed on the surface of the reaction preventive layer 4 as it dissolves, even if the surface layer of the reaction-preventing film 4 is oxidized, the self-cleaning action at the time of gold plating substantially eliminates them. Oxides are dissolved and removed.

【0036】次に図1(e)の工程に示すように、層間
絶縁層6としてポリイミド層を、配線層上を覆い、全表
面に形成する。
Next, as shown in the step of FIG. 1E, a polyimide layer is formed as an interlayer insulating layer 6 on the entire surface of the wiring layer so as to cover the wiring layer.

【0037】次いで図1(f)の工程に示すように、回
路接続に必要な所定の個所のポリイミド層をエッチング
して層間接続穴を形成した後、図1(a)に示した下地
導体膜2の形成工程と同様の工程でクロム/銅の2層膜
からなる下地導体膜7を形成する。
Then, as shown in the step of FIG. 1F, after the polyimide layer at a predetermined portion necessary for circuit connection is etched to form an interlayer connection hole, the underlying conductor film shown in FIG. The base conductor film 7 made of a two-layer film of chromium / copper is formed by the same process as the forming process of 2.

【0038】最後に図1(g)の工程に示すように、図
1(b)から図1(f)までの工程を繰返し、3層配線
の多層配線基板を製造した。
Finally, as shown in the step of FIG. 1 (g), the steps of FIG. 1 (b) to FIG. 1 (f) were repeated to manufacture a multilayer wiring board having three-layer wiring.

【0039】〈実施例2〉この例は、実施例1における
図1(f)の工程、つまりポリイミド層間絶縁膜6の形
成後に、下地導体膜7を形成する工程の変形例を示すも
ので、その要部断面図を図5に示す。図1(f)のスパ
ッタ成膜法による下地導体膜7の形成を、無電解めっき
で形成する場合には、ポリイミド層間絶縁膜6上に十分
な密着力のある無電解めっきを工程増とならないプロセ
スで形成しなければならない。
Example 2 This example shows a modification of the step of FIG. 1 (f) in Example 1, that is, the step of forming the underlying conductor film 7 after forming the polyimide interlayer insulating film 6. A cross-sectional view of the main part is shown in FIG. When forming the underlying conductor film 7 by the sputter deposition method of FIG. 1F by electroless plating, electroless plating with sufficient adhesion on the polyimide interlayer insulating film 6 does not increase the number of steps. Must be formed in the process.

【0040】この実施例はこれを実現するもので、図5
に示すようにポリイミド層間絶縁膜6上に、絶縁微粒子
としてポリイミド粒子9を含有するポリイミド樹脂12
を塗布し、ポリイミド粒子9の粒子径以下の膜厚に形成
し、このポリイミド樹脂12により固定された微粒子の
表面形状にしたがいポリイミド層間絶縁膜6の表面を凹
凸化し、その上に下地導体膜7を形成したものである。
This embodiment realizes this, and FIG.
The polyimide resin 12 containing the polyimide particles 9 as insulating fine particles on the polyimide interlayer insulating film 6 as shown in FIG.
Is applied to form a film having a film thickness equal to or smaller than the particle size of the polyimide particles 9, and the surface of the polyimide interlayer insulating film 6 is made uneven according to the surface shape of the fine particles fixed by the polyimide resin 12, and the underlying conductor film 7 is formed thereon. Is formed.

【0041】下地導体膜7の形成は、実施例1のスパッ
タ法によるクロム/銅2層膜の代わりに無電解銅めっき
単層で形成した。銅めっき単層の代わりにクロム/銅2
層めっき膜としてもよいことは言うまでもない。この凹
凸形成により、ポリイミド層間絶縁膜6に対するめっき
下地導体膜7の密着力を格段に増加させることができ
た。
The underlying conductor film 7 was formed by a single layer of electroless copper plating instead of the chromium / copper two-layer film formed by the sputtering method of Example 1. Chromium / copper 2 instead of copper plating single layer
It goes without saying that a layer plating film may be used. By forming the unevenness, the adhesion of the plating base conductor film 7 to the polyimide interlayer insulating film 6 could be significantly increased.

【0042】[0042]

【発明の効果】以上詳述したように本発明により、所期
の目的を達成することができた。すなわち、銅−ポリイ
ミド多層基板を代表例として説明すると、配線層を構成
する銅導体を無電解めっきによる銅−ポリイミド反応防
止膜及び酸化防止膜で被覆するため、配線層(銅導体)
のパターン形状によらず銅−ポリイミド反応を防止でき
配線層間接続部形成時、銅−ポリイミド反応防止膜エッ
チングや銅導体表面処理工程が不要になる。これによ
り、配線層間接続部形状不良を解消し、配線層間接続部
形成工程が簡略化できる。
As described above in detail, according to the present invention, the intended purpose can be achieved. That is, when a copper-polyimide multilayer substrate is described as a typical example, since the copper conductor forming the wiring layer is covered with the copper-polyimide reaction preventing film and the oxidation preventing film by electroless plating, the wiring layer (copper conductor)
The copper-polyimide reaction can be prevented irrespective of the pattern shape and the step of etching the copper-polyimide reaction preventing film and the copper conductor surface treatment step are not required at the time of forming the wiring interlayer connection portion. As a result, it is possible to eliminate the defective shape of the wiring interlayer connecting portion and simplify the wiring interlayer connecting portion forming step.

【0043】また、セラミック基板上の配線層を電解め
っきで形成することによりセラミック基板表面の凹凸を
平坦化でき、反応防止膜の被覆性が向上し、結果として
銅−ポリイミド反応を完全に防止することができる。
By forming the wiring layer on the ceramic substrate by electrolytic plating, the irregularities on the surface of the ceramic substrate can be flattened, the coverage of the reaction preventive film is improved, and as a result, the copper-polyimide reaction is completely prevented. be able to.

【0044】さらに、無電解めっきにより下地導体膜を
ポリイミド層間絶縁膜上に形成する際に、予めポリイミ
ド層間絶縁膜上に絶縁微粒子を固定することによって表
面を凹凸化しておくことにより、無電解めっきの密着力
を増加させることができ、低抵抗、低誘電率の多層配線
基板を安価に提供することができる。
Further, when the underlying conductor film is formed on the polyimide interlayer insulating film by electroless plating, by fixing insulating fine particles on the polyimide interlayer insulating film in advance to make the surface uneven, electroless plating is performed. It is possible to increase the adhesion force of the above, and it is possible to provide a low-resistance, low-dielectric-constant multilayer wiring board at low cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例(実施例1)となる多層配線
基板の製造工程を示す断面図。
FIG. 1 is a cross-sectional view showing a manufacturing process of a multilayer wiring board according to an embodiment (Example 1) of the present invention.

【図2】従来の多層配線基板の製造工程例を示す断面
図。
FIG. 2 is a cross-sectional view showing an example of a manufacturing process of a conventional multilayer wiring board.

【図3】同じく従来の製造工程を示す断面図。FIG. 3 is a sectional view showing a conventional manufacturing process.

【図4】同じく従来の製造工程を示す断面図。FIG. 4 is a sectional view showing a conventional manufacturing process.

【図5】本発明の他の実施例(実施例2)となる多層配
線基板の要部断面製造工程図。
FIG. 5 is a cross-sectional manufacturing process diagram of a main part of a multilayer wiring board according to another embodiment (second embodiment) of the present invention.

【符号の説明】[Explanation of symbols]

1…セラミック基板、 2…下地導体、2a
…下地導体の配線形成領域、2b…下地導体の配線形成
外領域、3…配線層(銅導体)、 4…反応防
止膜、5…レジストパターン、 6…配線層間
絶縁膜(ポリイミド)、7…下地導体、
8…酸化防止膜、9…絶縁微粒子、
10…下層クロム膜、11…ポリイミド−銅接触部、
12…微粒子含有ポリイミド樹脂。
1 ... Ceramic substrate, 2 ... Base conductor, 2a
... Wiring formation region of base conductor, 2b ... Non-wiring formation region of base conductor, 3 ... Wiring layer (copper conductor), 4 ... Reaction preventive film, 5 ... Resist pattern, 6 ... Wiring interlayer insulating film (polyimide), 7 ... Base conductor,
8 ... Antioxidation film, 9 ... Insulating fine particles,
10 ... Lower chrome film, 11 ... Polyimide-copper contact part,
12 ... Polyimide resin containing fine particles.

フロントページの続き (72)発明者 橋本 悟 神奈川県横浜市戸塚区戸塚町216番地 株 式会社日立製作所情報通信事業部内 (72)発明者 森田 守 神奈川県横浜市戸塚区戸塚町216番地 株 式会社日立製作所情報通信事業部内Front page continuation (72) Inventor Satoru Hashimoto 216 Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Prefectural Information & Communication Division, Hitachi, Ltd. (72) Mori Morita 216 Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Information & Communication Division, Hitachi, Ltd.

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】セラミック基板上の下地導体膜を介して形
成された配線層の表面及び側面に、反応防止膜と酸化防
止膜との2層膜を積層被覆し、層間絶縁膜として有機高
分子絶縁層を形成して成る多層配線基板。
1. A surface layer and a side surface of a wiring layer formed on a ceramic substrate with a base conductor film interposed therebetween are laminated and coated with a two-layer film including a reaction-preventing film and an anti-oxidizing film to form an organic polymer as an interlayer insulating film. A multilayer wiring board formed by forming an insulating layer.
【請求項2】上記有機高分子絶縁層を、ポリイミドで構
成して成る請求項1記載の多層配線基板。
2. The multilayer wiring board according to claim 1, wherein the organic polymer insulating layer is composed of polyimide.
【請求項3】上記反応防止膜を、ニッケルで構成して成
る請求項1記載の多層配線基板。
3. The multilayer wiring board according to claim 1, wherein the reaction preventing film is made of nickel.
【請求項4】上記酸化防止膜を、金で構成して成る請求
項1記載の多層配線基板。
4. The multilayer wiring board according to claim 1, wherein the antioxidant film is made of gold.
【請求項5】上記層間絶縁膜上に下地導体膜を介して新
たな配線層が積層された多層配線基板において、前記層
間絶縁膜上に、絶縁微粒子を含有した有機高分子絶縁膜
を微粒子径より薄く形成して、微粒子を表面に固定する
ことにより凹凸化した表面層に、めっき下地導体膜を介
して新たな配線層が積層されて成る請求項1記載の多層
配線基板。
5. A multilayer wiring board in which a new wiring layer is laminated on the interlayer insulating film via a base conductor film, and an organic polymer insulating film containing insulating particles is provided on the interlayer insulating film with a fine particle diameter. 2. The multilayer wiring board according to claim 1, wherein a new wiring layer is laminated on a surface layer which is formed to be thinner and is made uneven by fixing fine particles on the surface, with a plating base conductor film interposed therebetween.
【請求項6】上記絶縁微粒子を、層間絶縁膜を形成する
樹脂の微粒子で構成して成る請求項5記載の多層配線基
板。
6. The multilayer wiring board according to claim 5, wherein the insulating fine particles are made of resin fine particles forming an interlayer insulating film.
【請求項7】セラミック基板上に下地導体膜を介して
電解めっきにより第1の配線導体層を形成する工程と、
前記導体層上に反応防止膜と酸化防止膜とを、めっき
法により順次積層し、前記第1の配線導体層の表面全体
をこれらの2層膜で被覆する工程と、全面に層間絶縁
膜として有機高分子絶縁層を形成する工程と、前記第
1の配線導体層上の層間絶縁膜に回路形成用の開口部を
形成する工程と、前記回路形成用の開口部を含む層間
絶縁膜上に下地導体膜を介して第2の配線導体層を形成
する工程とを有すると共に、引き続き前記乃至の
工程を多層配線の積層数に見合った回数分だけ繰返す工
程とを有して成る多層配線基板の製造方法。
7. A step of forming a first wiring conductor layer on a ceramic substrate by electrolytic plating through a base conductor film,
A step of sequentially laminating a reaction prevention film and an oxidation prevention film on the conductor layer by a plating method and covering the entire surface of the first wiring conductor layer with these two-layer films, and forming an interlayer insulating film on the entire surface. A step of forming an organic polymer insulating layer, a step of forming an opening for circuit formation in the interlayer insulating film on the first wiring conductor layer, and a step of forming an opening for circuit formation on the interlayer insulating film. And a step of forming a second wiring conductor layer via an underlying conductor film, and a step of successively repeating the above-mentioned steps by the number of times corresponding to the number of laminated layers of the multilayer wiring. Production method.
【請求項8】上記の層間絶縁膜として有機高分子絶縁
層を形成する工程の後に引き続いて、絶縁微粒子を含
有した有機高分子絶縁膜を微粒子径より薄く形成して、
微粒子を表面に固定することにより絶縁層表面を凹凸化
する工程を付加して成る請求項7記載の多層配線基板の
製造方法。
8. An organic polymer insulating film containing insulating fine particles is formed to be thinner than the fine particle diameter, following the step of forming an organic polymer insulating layer as the interlayer insulating film.
The method for manufacturing a multilayer wiring board according to claim 7, which further comprises a step of making the surface of the insulating layer uneven by fixing fine particles on the surface.
【請求項9】上記の反応防止膜を無電解ニッケルめっ
きで、酸化防止膜を無電解による金の置換めっきで、そ
れぞれ形成する工程として成る請求項7記載の多層配線
基板の製造方法。
9. The method for manufacturing a multilayer wiring board according to claim 7, wherein the reaction preventing film is formed by electroless nickel plating, and the oxidation preventing film is formed by electroless gold displacement plating.
【請求項10】上記の回路形成用の開口部を含む層間
絶縁膜上に下地導体膜を形成する工程において、下地導
体膜を無電解めっきで形成する工程として成る請求項7
もしくは8記載の多層配線基板の製造方法。
10. The step of forming a base conductor film on an interlayer insulating film including an opening for circuit formation as described above, which is a step of forming the base conductor film by electroless plating.
Alternatively, the method for manufacturing a multilayer wiring board according to item 8.
JP9731293A 1993-04-23 1993-04-23 Multilayer wiring board and method of manufacturing the same Expired - Fee Related JP3080508B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9731293A JP3080508B2 (en) 1993-04-23 1993-04-23 Multilayer wiring board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9731293A JP3080508B2 (en) 1993-04-23 1993-04-23 Multilayer wiring board and method of manufacturing the same

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Publication Number Publication Date
JPH06310866A true JPH06310866A (en) 1994-11-04
JP3080508B2 JP3080508B2 (en) 2000-08-28

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010205856A (en) * 2009-03-02 2010-09-16 Murata Mfg Co Ltd Method of forming pattern and electronic component
JP2012192629A (en) * 2011-03-16 2012-10-11 Toshiba Tec Corp Inkjet head and method of manufacturing the same
JP2014053608A (en) * 2012-09-10 2014-03-20 Samsung Electro-Mechanics Co Ltd Circuit board and production method of the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010205856A (en) * 2009-03-02 2010-09-16 Murata Mfg Co Ltd Method of forming pattern and electronic component
JP2012192629A (en) * 2011-03-16 2012-10-11 Toshiba Tec Corp Inkjet head and method of manufacturing the same
US8662645B2 (en) 2011-03-16 2014-03-04 Toshiba Tec Kabushiki Kaisha Inkjet head and method of manufacturing the same
US8777381B2 (en) 2011-03-16 2014-07-15 Toshiba Tec Kabushiki Kaisha Inkjet head and method of manufacturing the same
JP2014053608A (en) * 2012-09-10 2014-03-20 Samsung Electro-Mechanics Co Ltd Circuit board and production method of the same

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