JPH1154930A - Manufacture of multilayered wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method wherein lowering of insulation resistance between wirings and shortcircuiting are prevented, by reducing height difference of sticking surfaces when forming a lower wiring layer and a via hole are formed by a semi-additive method. SOLUTION: An electroless plating layer 103 is formed on a lower insulation layer 101, a first photosensitive dry film DF1 is stuck, and an opening pattern for a lower wiring layer is shaped by exposure and development. A current is made to flow through the electroess plating layer 103, and an electrolytic plating lower wiring layer 105 is formed inside the opening. A second photosensitive dry film DF2 is stuck on the first photosensitive dry film DF1 and an electrolytic plating lower wiring layer 105, and an opening pattern OP2 for a via hole is shaped in a part of an upper surface of the electrolytic plating lower wiring layer 105 by exposure and development. A current is made to flow through the electroless plating layer 103, and a via hole 107 is formed inside the opening OP2 by electrolytic plating.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board for connecting an upper wiring layer and a lower wiring layer via a via, and more particularly, to a multilayer method for forming a via by photolithography and plating. The present invention relates to a method for manufacturing a wiring board.

[0002]

2. Description of the Related Art Conventionally, when forming a multilayer wiring board,
The semi-additive method is known. In this method, first, electroless plating is performed on the entire surface of the lower insulating layer, and then openings are formed by using a photoresist. Then, a current is passed through the electroless plating layer to form an electrolytic plating lower wiring layer in the opening by electrolytic plating. Thereafter, the photoresist is removed, and the exposed electroless plating layer is removed by etching to form a lower wiring layer composed of two layers, an electroless plating lower wiring layer and an electrolytic plating lower wiring layer.

Further, this technique is also applied to a case where a via is formed on a lower wiring layer. That is, an electroless plating layer is formed on the entire surface of the lower wiring layer and the lower insulating layer exposed between the lower wiring layers by electroless plating. Thereafter, a photoresist layer is formed on this, which is the same as or thicker than the height of a via to be formed later, and is exposed and developed to form a via opening, and a current is passed through this electroless plating layer to open the via opening. An electrolytic plating via is formed therein. Then
The photoresist is removed, and the exposed electroless plating layer between the lower wiring layers (and on the lower wiring layers) is removed by etching, thereby securing insulation between the lower wiring layers and providing necessary portions on the lower wiring layers. Via (via post)
To form

Thereafter, in order to form an upper wiring layer, an insulating resin paste is further applied and dried, and the upper surface of the via is exposed by polishing, and then the upper wiring layer is formed in the same manner as the lower wiring layer. The method of stacking the wiring layer and the insulating layer one by one in this manner is called a build-up wiring forming method.

[0005]

In the case where the lower wiring layer and the via are formed by the above-described semi-additive method, the photoresist to be used is of a type (liquid resist) in which a liquid is coated and dried. There is a type (dry film resist) in which a film-like resist in a semi-dry state is pasted. Among them, the liquid resist has an advantage that it can be formed so as to reliably follow some unevenness, but it is difficult to apply the liquid resist to a uniform thickness. Also, it is difficult to apply a thick coating at a time.
Only a thickness of about 0 μm can be formed. If the resist is thinner than the required thickness, the top of the via, etc., crosses over the opening edge of the resist and spreads laterally, causing variations in shape and height such as mushrooms. Need to be secured. Therefore, when it is desired to form a thick layer, several times (for example, 4 to 5
Times) application and drying must be repeated.

On the other hand, since a dry film resist (hereinafter, also simply referred to as a dry film) is formed to have a certain thickness from the beginning, a resist layer having a uniform thickness can be formed, and it is sufficient to simply attach it. Handling is easy. There is also an advantage that a thick one (for example, one having a thickness of 40 μm) can be easily obtained. However, when the unevenness of the attachment surface is large, it is impossible to follow the shape, and the resist is locally lifted. If the resist floats, the plating solution may penetrate into the raised portion during plating, and plating dripping may occur on the unnecessary portion where the plating adheres. As described above, after the electrolytic plating, an etching process is performed to remove the exposed electroless plating layer.However, when this plating sag occurs between the wirings, it is difficult to sufficiently remove the plating between the wirings. Become. Therefore, the insulation resistance between the wirings may be reduced, or in a severe case, the wirings may be short-circuited (short-circuited).

Further, in order to ensure a predetermined insulation resistance between the lower wiring layer and the upper wiring layer, the insulating layer needs to have a predetermined thickness, and the height of the via needs to be also predetermined. Generally, it was necessary to make the thickness higher than the thickness of the lower and upper wiring layers.

Therefore, when forming a via on the lower wiring layer as described above, when applying a liquid resist, the resist is formed higher than the height of the via to be formed. It was necessary to repeat the application and drying of the resin, which required a man-hour. On the other hand, as shown in FIG. 5, in the case where the via 7 is formed using the dry film DF, the lower wiring layer 2 already formed on the lower insulating layer 1 and the lower insulating layer 1 exposed therebetween are formed. The steps, and hence the steps of the irregularities after the formation of the electroless plating layer 3 thereon, are large, and the dry film DF has a large thickness. Therefore, the followability is poor, and the resist floating F occurs ( FIG. 5 (a)). Therefore, at the time of electrolytic plating, the plating solution penetrates into the portion of the resist floating F, and plating is deposited, and a plating sag D is generated. In particular, at the time of forming a via, electrolytic plating is performed under the condition that the via portion is formed to be high (thick), so that the portion of the plating sag D is also likely to be deposited. For this reason, the subsequent etching for the purpose of removing the electroless plating layer 3 cannot be sufficiently removed, so that the insulation resistance between the wirings may be reduced or the wiring may be short-circuited.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing a highly reliable wiring board which uses a dry film resist which is easy to handle and which does not cause plating sagging due to floating of the resist. Aim.

[0010]

According to a first aspect of the present invention, there is provided a method of manufacturing a multilayer wiring board having a via for connecting an upper wiring layer and a lower wiring layer. After attaching the first photosensitive dry film resist on the electroless plating layer formed on the lower insulating layer,
Exposing and developing to open a lower wiring layer opening pattern, and passing a current through the electroless plating layer to form an electrolytic plating lower wiring layer by electrolytic plating in the lower wiring layer opening pattern, After attaching the second photosensitive dry film resist on the first photosensitive dry film resist and the electrolytic plating lower wiring layer,
Exposing and developing to form a via opening pattern on a part of the upper surface of the electrolytic plating lower wiring layer, and passing a current through the electroless plating layer to form a via in the via opening pattern by electrolytic plating A step of removing the first and second photosensitive dry film resists, and a step of etching and removing exposed portions of the electroless plating layer. It is a manufacturing method of.

According to the above means, since the second photosensitive dry film resist is pasted on the first photosensitive dry film resist, unlike the case where only the second photosensitive dry film resist is pasted, the step of the pasting surface is different. Become smaller. Therefore, the second photosensitive dry film resist can be attached easily and without lifting. Therefore, it is possible to prevent the plating sagging phenomenon caused by the resist floating,
A highly reliable wiring having high insulation resistance between the wirings can be formed. Further, since the (second photosensitive) dry film resist is used for forming the via pattern, a thick and uniform resist film can be easily formed as compared with applying a liquid resist. An inexpensive multilayer wiring board can be obtained.

The lower insulating layer may be made of an insulating resin such as an epoxy resin, a BT (bismale-mite-triazine) resin, a polyimide resin, a ceramic such as alumina, aluminum nitride, glass ceramic, or a glass. -Composite materials such as epoxy resin and glass-BT resin can be appropriately selected. In addition, the material of the electroless plating layer may be appropriately selected in consideration of the adhesion to the material of the lower insulating layer, conductivity, ease of plating, and the like. For example, Cu, Ni, Au, or the like may be selected. Can be.

The material of the lower wiring layer and the via of the electrolytic plating is appropriately determined in consideration of the adhesion to the material of the insulating layer formed after the formation of the electroless plating layer and the via, the conductivity, the ease of plating, and the like. What is necessary is just to select, for example, Cu, Ni, Au,
Cr or the like can be selected. Further, in order to prevent the top of the via from being etched when the electroless plating layer is removed by etching, the upper surface of the via may be formed thin by plating with a material different from that of the electroless plating layer. That is, for example, a current may be passed through a Cu electroless plating layer to form a via by Cu electrolytic plating, and the upper surface of the via may be formed by thin electrolytic Ni plating. In this case, the upper portion can be protected during Cu etching by Ni plating on the upper surface of the via. The material of the insulating layer to be formed after the formation of the via may be selected in consideration of the material of the lower insulating layer and the via, characteristics such as insulation and water absorption. For example, epoxy resin, BT resin, polyimide Resins.

Further, the solution according to claim 2 further comprises a roughening step of roughening the upper surface of the electrolytic plating lower wiring layer before attaching the second photosensitive dry film resist. Item 4. A method for manufacturing a multilayer wiring board according to item 1.

According to the above means, the roughening step
The surface of the electrolytic plating lower wiring layer becomes rough. Therefore, when the second photosensitive dry film is adhered, the contact area between the two becomes large, and the adhesion between the lower wiring layer of the electrolytic plating and the second photosensitive dry film resist is further improved. Therefore, the second photosensitive dry film resist does not peel off from the lower wiring layer of the electrolytic plating, and the resist floating and the plating sag can be prevented. Therefore, a more reliable multilayer wiring board can be manufactured.

Here, the roughening step refers to a process for increasing the roughness of the upper surface of the lower plating layer of the electrolytic plating, and specifically, the upper surface of the lower wiring layer of the electrolytic plating is treated with a persulfate-based etching solution or sulfuric acid. A method of roughening the surface by etching (soft etching) using a hydrogen peroxide-based etchant or the like; According to these soft etchings, since the etching rate is low, the etching does not proceed rapidly, and the variation in the degree of surface roughening due to the processing time is small, which is preferable. Needle-like or granular plating may be applied to the upper surface of the lower wiring layer of electrolytic plating by alloy plating of Cu, Cu, Zn, Co, or the like. In this roughening process, since the process is performed with the first photosensitive dry film adhered, it is preferable to select a process that can withstand the dry film.

A portion of the upper surface of the electrolytic plating lower wiring layer formed by the roughening process, which is exposed in the via opening pattern which is opened after the second photosensitive dry film resist is attached (opening bottom surface). For (2), in order to improve the connectivity between the lower wiring layer of the electrolytic plating and the via, even before the via is formed by the electrolytic plating, the resist residue is removed by acidic degreasing or activated by etching (soft etching). good.

Further, in the step of forming the electrolytic plating lower wiring layer, it is preferable to form the electrolytic plating lower wiring layer by semi-gloss or matte electrolytic plating. Since the deposition surface itself of the electrolytic plating lower wiring layer becomes rough,
Roughening treatment is not required. Alternatively, a sufficiently roughened surface can be obtained by a weak or short-time roughening treatment.

Further, according to a third aspect of the present invention, in the step of forming the electrolytic plating lower wiring layer, a step between an upper surface of the electrolytic plating lower wiring layer and an upper surface of the first photosensitive dry film resist is 0 to 0. 3. The method according to claim 1, wherein the lower wiring layer is formed so as to have a thickness of 5 μm.

According to the above means, the step between the upper surface of the electrolytic plating lower wiring layer and the upper surface of the first photosensitive dry film resist is reduced to 0 to 5 μm. For this reason, when the step is in this range, when the second photosensitive dry film resist is applied, the dry film resist reliably follows the step, so that the resist can be securely applied without causing resist floating, No plating sag. Therefore, a more reliable multilayer wiring board can be manufactured.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below.
This will be described with reference to the drawings. 1 to 3 are partially enlarged cross-sectional views for explaining a manufacturing process of a multilayer wiring board according to the present invention. The lower insulating layer 1 made of the epoxy resin shown in FIG.
Numeral 01 is formed on a core substrate (BT resin-glass composite material) (not shown), and a lower via 102 formed by electrolytic Cu plating penetrates the inside vertically in the drawing. The insulating layer 101 and the lower via 102
In the drawing, upper surfaces 101a and 102a are smoothed by buffing.

First, the upper surface 101 of the insulating layer 101
a is roughened with a permanganate solution (45 g / l). Further, Cu on the upper surface 102a of the lower via 102 is converted into a sulfuric acid-hydrogen peroxide-based etching solution (OPC-400; OPC-400).
And soft immersion in a Sn-Pd colloid solution (Okuno Pharmaceutical; OPC-80) to adsorb the Pd catalyst nuclei. Then, electroless Cu plating (Okuno Pharmaceutical;
Build copper) to form an electroless C having a thickness of 0.5 to 1.0 μm on the entire upper surface 101a of the insulating layer and the upper surface 102a of the via.
The u plating layer 103 was applied (FIG. 1B). As a result, the lower via 102 and the electroless plating layer 103 were connected.

Thereafter, a first photosensitive dry film resist DF having a thickness of 25 μm is formed using a hot roll laminator.
1 (manufactured by Nippon Gohsei; NIT-225) is laminated on the electroless plating layer 103. Next, the lower wiring layer pattern is exposed and developed using a 1% aqueous solution of sodium carbonate to open the lower wiring layer opening pattern OP1 (FIG. 1 (c)). In addition, in order to improve the adhesion between the electroless plating layer and the electrolytic Cu plating described below, the bottom of the opening pattern OP1 was subjected to acidic degreasing to remove the resist residue.
The surface of the electroless Cu plating layer is activated by soft etching. Further, as shown in FIG.
An electric current is passed through the plating layer 103 and the copper sulfate-based electrolytic C
u plating, and a thickness of about 22
A μm electrolytic plating lower wiring layer 105 was formed. At this time, the upper surface D of the first photosensitive dry film resist DF1
Cu plating was performed so that the step d between F1a and the upper surface 105a of the electrolytic plating lower wiring layer 105 was 0 to 5 μm. The lower wiring layer 105 has a dry film DF.
If the upper surface DF1a is higher than the upper surface DF1a (that is, the step d <0), the electrolytic plating lower wiring layer 105 spreads beyond the opening end of the opening OP1 and becomes mushroom-like, which is not preferable. On the other hand, when the step d exceeds 5 μm, the second photosensitive dry film DF2 to be attached later becomes difficult to follow the step d. In this case, plating sag tends to occur.

Then, the upper surface 105a of the electrolytic plating lower wiring layer 105 is soft-etched with a persulfate-based etchant (PB-228, manufactured by Ebara Uzilite) to roughen the surface 1a.
05b is formed. The upper surface 105a of the lower wiring layer 105 is roughened by the roughening process by the soft etching to become a roughened surface 105b. When the second dry film resist DF2 described below is attached, the roughened surface 105b and the second The film DF2 is firmly adhered. Since the roughening treatment uses soft etching with a persulfate-based etchant, the etching rate is low, and even if the treatment time varies slightly, the influence on the roughening treatment state is small. For this reason, the process management is facilitated and the yield is improved.

Next, a second dry film resist DF2 having a thickness of 40 μm (NIT-240 manufactured by Nippon Synthetic Chemical Co., Ltd.) is attached on the upper surface DF1a and the roughened surface 105b of the first dry film resist DF1 using a hot roll laminator. At this time, as described above, the step d between the upper surface DF1a of the first dry film DF1 and the upper surface 105a of the lower wiring layer 105, and thus the roughened surface 105b is 5 μm.
m, and the second dry film DF2 could be stuck and adhered without causing resist floating. Thereafter, the via pattern is exposed and developed using a 1% aqueous solution of sodium carbonate to open a via opening pattern OP2 having a diameter of 60 μm (FIG. 2A). The bottom surface of the opening pattern OP2 is also acid degreased. The resist residue is removed by soft etching and the lower wiring layer surface is activated by soft etching.
Adhesion with plating (via) is improved.

Next, as in the case of forming the electroplating lower wiring layer 105 (FIG. 1D), the electroless plating layer 10 is formed.
3, a via 107 having a diameter of 60 μm and a height of 40 μm was formed by copper sulfate-based electrolytic Cu plating (FIG. 2B). As described above, since the resist is not lifted on the second dry film DF2, there is no plating sagging in which the plating solution enters under the second dry film DF2 and the plating is deposited during the electrolytic plating. In this example, the via 107 having a height (40 μm) almost the same as that of the second dry film DF2 having a thickness of 40 μm was formed. This is because the upper portion of the via 107 is removed by polishing about 5 μm in a step to be described later, so that the shape of the upper portion of the via 107 does not matter much.
Needless to say, the via 107 having a height of 40 μm may be formed using a thicker dry film (for example, one having a thickness of 50 μm).

Thereafter, the dry film resists DF2 and DF1 were peeled off and removed by showering with a 3% aqueous NaOH solution. As a result, as shown in FIG.
Via (via post) 1 on electrolytic plating lower wiring layer 105
07 could be formed.

Then, soft etching is performed with a persulfate-based etchant (PB-228, manufactured by Ebara Uzilite), and Cu is etched and removed by about 1 μm over the entire surface, so that the electroless Cu between the electroplating lower wiring layers 105 is removed. The plating layer is removed, and the upper surface 1 of the lower insulating layer 101 is removed.
01a is exposed to make each wiring pattern independent. As a result, the exposed portion of the electroless Cu plating layer 103 is removed, and only the portion below the electrolytic plating lower wiring layer 105 remains as the electroless plating lower wiring layer 103a, thereby forming the lower wiring layer 106 ( FIG. 3 (a)).

Thereafter, the lower wiring layer 106 and the via 10
The surface of No. 7 was subjected to a known blackening treatment to roughen the surface. This roughening can improve the adhesion to the insulating layer described below. Next, as shown in FIG. 3B, an epoxy resin-based insulating paste is applied by screen printing and cured at 150 ° C. for 2 hours to form an insulating layer 111 having a thickness of about 35 μm from the upper surface of the lower wiring layer 106. did. At this time, an insulating layer is also formed above the via 107, but the height of the insulating paste is about 10 μm above the via 107 because the insulating paste flows and spreads.

Further, the upper surface of the insulating layer 111 is flattened by buffing. By this polishing, the insulating layer above the via 107 is removed, and as shown in FIG.
07 is also polished by about 5 μm to expose the via 107. The margin for polishing the via 107 (5 μm in this example)
In order to ensure that the upper surface of the via 107 is exposed from the insulating layer 111, an appropriate value is selected in consideration of the thickness of the insulating layer 111, the variation in the height of the via 107, and the like.

Thereafter, as in the case of FIG. 1B, the surface of the insulating layer 111 is roughened using permanganic acid, and the upper surface (polished surface) of the via 107 is etched with a sulfuric acid-hydrogen peroxide-based etchant. And soft-etch. Furthermore, Sn-
After being immersed in the Pd colloid solution, electroless Cu plating is performed to form an upper electroless plating layer. Further, as shown in FIG. 4, the electroplating upper wiring layer 115 and the electroless plating upper wiring are formed by a well-known semi-additive method. An upper wiring layer 116 composed of the layer 113a is formed. Specifically, a dry film resist (not shown) is pasted on the upper electroless plating layer (not shown), exposed and developed to open the pattern of the upper wiring layer, and a current is passed through the upper electroless plating layer, so that The electrolytic plating upper wiring layer 115 is formed by electrolytic Cu plating. Thereafter, the dry film is peeled off, and the exposed upper electroless plating layer is removed by soft etching to form each pattern independently. In addition,
The upper wiring layer 116 has a panel C on the upper electroless plating layer.
It may be formed by a subtractive method in which etching is performed after u plating is performed.

Further, an upper via, an insulating layer, and a wiring layer were sequentially formed to form a multilayer wiring board 100 as shown in FIG. In the multilayer wiring board 100 of FIG.
An upper wiring layer 116 including an electroless plating upper wiring layer 113a and an electrolytic plating upper wiring layer 115 is formed on the upper wiring layer 11, and the lower wiring layer 106 and the upper wiring layer 116 are connected by vias 107. Further, an insulating layer 121 is formed between the upper wiring layer 116 and the via 117 formed thereon. A wiring layer 126 composed of an electroless plating wiring layer 123a and an electrolytic plating wiring layer 125 is similarly formed on the insulating layer 121, and an insulating layer (epoxy resin solder resist layer) 131 of the upper part of the wiring layer 126 is formed. Ni-A
A u-plate layer 128 is formed, and a solder bump 139 made of eutectic solder is formed. In this multilayer wiring board 100, each insulating layer (101, 111, 1)
21) penetrating through (102, 107, 117)
It constitutes a so-called stacked via that is formed by being stacked vertically.

As described above, in this embodiment, since the second photosensitive dry film DF2 is adhered on the first photosensitive dry film DF1, the step d is small (0 to 5).
μm), no resist floating occurs on the second photosensitive dry film DF2. Therefore, a reduction in insulation resistance and a short circuit due to the plating sagging phenomenon do not occur, and a highly reliable multilayer wiring board can be obtained. In addition, the electroless plating layer 1
03 is used not only as a conductor at the time of forming the electrolytic plating lower wiring layer 105 but also as a conductor at the time of electrolytic plating at the time of forming the via 107, and there is no need to form electroless plating on the lower wiring layer. Therefore, the process can be simplified.

In the above embodiment, three insulating layers (111, 121, 131) are formed on the lower insulating layer 101. However, the number of laminated insulating layers is not particularly limited. . Further, the present invention may be applied to a via connecting the lower wiring layer and the upper wiring layer, and it is not necessary to stack vias vertically so as to form a so-called stacked via as shown in FIG. On the other hand, the stacked via has an advantage that the area is smaller than that of the staggered via to connect the wirings over a plurality of layers, and the present invention is also useful in forming such a stacked via.

Further, in the above embodiment, the roughened surface 105
b was formed by soft etching (see FIG. 2A). However, instead of soft etching, the roughened surface 105b may be formed by performing acidic electrolytic Cu plating having a needle-like or granular surface following electrolytic Cu plating for forming the electrolytic plating lower wiring layer 105. good. In this case, the roughened surface 105b can be formed by continuous plating, and the etching operation and the cleaning operation associated therewith become unnecessary.

Another method is to adjust the brightening agent or the like added to the electrolytic Cu plating solution for forming the electrolytic plating lower wiring layer 105 so that the deposition surface becomes dull or semi-gloss. Good. By doing so, the upper surface of the electrolytic plating lower wiring layer 105 can be made a roughened surface 105b without performing a roughening process such as soft etching.

In the above, the present invention has been described with reference to the embodiment. However, the present invention is not limited to this, and can be appropriately modified and applied within the scope of the invention.

[Brief description of the drawings]

FIG. 1 is a partially enlarged cross-sectional view illustrating a former part of a manufacturing process of a multilayer wiring board according to an embodiment of the present invention.

FIG. 2 is a partially enlarged cross-sectional view illustrating a middle part of a manufacturing process of the multilayer wiring board according to the embodiment of the present invention.

FIG. 3 is a partially enlarged cross-sectional view illustrating a latter part of a manufacturing process of the multilayer wiring board according to the example of the present invention.

FIG. 4 is a partially enlarged sectional view of a multilayer wiring board according to an example of the present invention.

FIG. 5 is an explanatory diagram of a via forming step of a conventional multilayer wiring board.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 multilayer wiring board 101 lower insulating layer 102, 107, 117 via 103 electroless Cu plating layer 103 a electroless plating lower wiring layer 105 electrolytic plating lower wiring layer 106 lower wiring layer 111, 121, 131 insulating layer 113 a electroless plating upper wiring Layer 115 Electroplating upper wiring layer 116 Upper wiring layer 139 Solder bump

Claims (3)

[Claims] 1. A method of manufacturing a multilayer wiring board having a via for connecting an upper wiring layer and a lower wiring layer, the method comprising: forming a first photosensitive dry layer on an electroless plating layer formed on a lower insulating layer; After applying a film resist, exposing and developing to open an opening pattern for the lower wiring layer, and passing an electric current through the electroless plating layer, and electrolytically plating the lower part of the opening pattern for the lower wiring layer by electrolytic plating. Forming a wiring layer; attaching a second photosensitive dry film resist on the first photosensitive dry film resist and the electrolytic plating lower wiring layer; exposing and developing the same; A step of opening a via opening pattern on a part of the upper surface of the substrate, and passing a current through the electroless plating layer to form a via in the via opening pattern by electrolytic plating. A step of removing the first and second photosensitive dry film resists; and a step of etching and removing an exposed portion of the electroless plating layer. Manufacturing method. 2. The multilayer wiring board according to claim 1, further comprising a roughening step of roughening the upper surface of the lower wiring layer of the electrolytic plating before attaching the second photosensitive dry film resist. Method. 3. The step of forming an electrolytic plating lower wiring layer, wherein a step between an upper surface of the electrolytic plating lower wiring layer and an upper surface of the first photosensitive dry film resist is 0 to 5 μm.
3. The method according to claim 1, wherein the lower wiring layer is formed so as to fall within the range of: