JPH0629356A - 半導体素子用容器 - Google Patents

半導体素子用容器

Info

Publication number
JPH0629356A
JPH0629356A JP3140512A JP14051291A JPH0629356A JP H0629356 A JPH0629356 A JP H0629356A JP 3140512 A JP3140512 A JP 3140512A JP 14051291 A JP14051291 A JP 14051291A JP H0629356 A JPH0629356 A JP H0629356A
Authority
JP
Japan
Prior art keywords
semiconductor chip
sidewall
side wall
bonding
bonding wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3140512A
Other languages
English (en)
Other versions
JP2604506B2 (ja
Inventor
Yoshimi Kurita
善美 栗田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP3140512A priority Critical patent/JP2604506B2/ja
Publication of JPH0629356A publication Critical patent/JPH0629356A/ja
Application granted granted Critical
Publication of JP2604506B2 publication Critical patent/JP2604506B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 （修正有） 【構成】金属性の容器本体１の素子搭載部の周囲に設け
て容器本体１と接続し、且つ素子搭載部に搭載した半導
体チップ４と同程度の高さを有する側壁２の上面に接地
用ボンディング部３を設け、半導体チップ４と内部リー
ド６との間を接続するボンディング線７の通路に対応す
る側壁２に切込部８を設ける。 【効果】内部リードに接続するボンディング線の短絡事
故を防止する。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体素子用容器に関
し、特に高周波帯高信頼性半導体素子用の容器に関す
る。
【０００２】
【従来の技術】従来の高周波帯高信頼性半導体素子用の
容器は図２（ａ）〜（ｃ）に示すように、金属製の容器
本体１の内側中央部に設けた素子搭載部の周囲に半導体
素子の上面と同程度の高さを有し容器本体１と接続して
設けた枠状の側壁２の上面に接地用ボンディング部３を
設けており、素子搭載部に搭載した半導体チップ４と接
地用ボンディング部３との間を接続するボンディング線
５と、半導体チップ４と内部リード６との間を接続する
ボンディング線７とを設けている。
【０００３】ここで、ボンディング線５の長さを短くす
ることにより、接地インダクタンスを低減させることが
できるが、ボンディング線７は側壁２の上方を越えて内
部リード６と接続している。
【０００４】
【発明が解決しようとする課題】この従来の半導体素子
用容器は、素子搭載部に搭載する半導体チップと内部リ
ードとの間を接続するボンディング線が接地ボンディン
グ部を有する枠状の側壁に接触して短絡し易いという問
題点があった。
【０００５】
【課題を解決するための手段】本発明の半導体素子用容
器は、導電性容器本体の内側中央部に設けた素子搭載部
と、前記素子搭載部の周囲に設けて前記容器と接続し且
つ前記素子搭載部に搭載する半導体チップの上面と同程
度の高さを有する枠状の側壁の上面に設けた接地用ボン
ディング部と、前記側壁の外側に設けた内部リードと前
記半導体チップとの間を接続するボンディング線の通路
に対応する前記側壁に設けた切込部とを備えている。
【０００６】
【実施例】次に、本発明について図面を参照して説明す
る。
【０００７】図１（ａ）〜（ｃ）は本発明の一実施例を
示す平面図及びＡ−Ａ′線断面図並びにＢ−Ｂ′線断面
図である。
【０００８】図１（ａ）〜（ｃ）に示すように、金属製
の容器本体１の内側中央部に設けた素子搭載部の周囲に
素子搭載部に搭載する半導体素子の上面と同程度の高さ
を有し且つ容器本体１と接続又は一体化して設けた枠状
の側壁２を設け、側壁２の外側に設けた内部リード６と
素子搭載部に搭載する半導体チップ４との中間に存在す
る側壁２に切込部８を設け、切込部８を挟む側壁２の上
面に接地用ボンディング部３を設けて半導体素子用容器
を構成する。
【０００９】素子搭載部に搭載した半導体チップ４の接
地電極と接地用ボンディング部３との間を短いボンディ
ング線５で接続し、半導体チップ４の信号電極又は電源
電極と内部リード６との間を切込部８を通してボンディ
ング線７で接続する。
【００１０】ここで、ボンディング線７は切込部８を通
しているため側壁２に接触することを防ぐことができ
る。
【００１１】
【発明の効果】以上説明した様に本発明は、半導体チッ
プと内部リードとの間を接続するボンディング線を素子
搭載部の周囲の側壁に設けた切込部を通すことにより、
ボンディング線が接地電位の側壁に接触して短絡するこ
とを防止し、半導体装置の信頼性を向上できるという効
果を有する。
【図面の簡単な説明】
【図１】本発明の一実施例を示す平面図及びＡ−Ａ′線
断面図並びにＢ−Ｂ′線断面図である。
【図２】従来の半導体素子用容器の一例を示す平面図及
びＣ−Ｃ′線断面図並びにＤ−Ｄ′線断面図である。
【符号の説明】
１ 容器本体 ２ 側壁 ３ 接地用ボンディング部 ４ 半導体チップ ５，７ ボンディング線 ６ 内部リード ８ 切込部

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 導電性容器本体の内側中央部に設けた素
    子搭載部と、前記素子搭載部の周囲に設けて前記容器と
    接続し且つ前記素子搭載部に搭載する半導体チップの上
    面と同程度の高さを有する枠状の側壁の上面に設けた接
    地用ボンディング部と、前記側壁の外側に設けた内部リ
    ードと前記半導体チップとの間を接続するボンディング
    線の通路に対応する前記側壁に設けた切込部とを備えた
    ことを特徴とする半導体素子用容器。
JP3140512A 1991-06-13 1991-06-13 半導体素子用容器 Expired - Fee Related JP2604506B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3140512A JP2604506B2 (ja) 1991-06-13 1991-06-13 半導体素子用容器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3140512A JP2604506B2 (ja) 1991-06-13 1991-06-13 半導体素子用容器

Publications (2)

Publication Number Publication Date
JPH0629356A true JPH0629356A (ja) 1994-02-04
JP2604506B2 JP2604506B2 (ja) 1997-04-30

Family

ID=15270374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3140512A Expired - Fee Related JP2604506B2 (ja) 1991-06-13 1991-06-13 半導体素子用容器

Country Status (1)

Country Link
JP (1) JP2604506B2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018225296A1 (ja) 2017-06-05 2018-12-13 株式会社Ｔｏｐ ロータ及び回転機

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6222461A (ja) * 1985-07-22 1987-01-30 Nec Corp 積層型セラミツクパツケ−ジ
JPH02138431U (ja) * 1989-04-20 1990-11-19

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6222461A (ja) * 1985-07-22 1987-01-30 Nec Corp 積層型セラミツクパツケ−ジ
JPH02138431U (ja) * 1989-04-20 1990-11-19

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018225296A1 (ja) 2017-06-05 2018-12-13 株式会社Ｔｏｐ ロータ及び回転機

Also Published As

Publication number Publication date
JP2604506B2 (ja) 1997-04-30

Similar Documents

Publication Publication Date Title
US5656857A (en) Semiconductor device with insulating resin layer and substrate having low sheet resistance
US5869886A (en) Flip chip semiconductor mounting structure with electrically conductive resin
JPH046222Y2 (ja)
US4266239A (en) Semiconductor device having improved high frequency characteristics
KR100475477B1 (ko) 인덕턴스 소자 및 반도체 장치
US5512781A (en) Semiconductor package device for super high-frequency band
US6166429A (en) Lead-frame package with shield means between signal terminal electrodes
US5523621A (en) Semiconductor device having a multilayer ceramic wiring substrate
JPH07321140A (ja) 半導体装置
JPH10224175A (ja) 弾性表面波装置
JPH0629356A (ja) 半導体素子用容器
JP2003017941A (ja) 圧電発振器
JP2536431B2 (ja) 半導体装置
JPH05121458A (ja) 半導体集積回路
JPS6112680Y2 (ja)
JPH09213868A (ja) マイクロ波半導体集積回路用リ−ドフレ−ム
JPS62119949A (ja) 半導体装置用パツケ−ジ
US5894171A (en) Semiconductor integrated circuit having a grounding terminal
JPH06268012A (ja) 半導体集積回路装置
JPH08298307A (ja) 半導体装置
JP3670863B2 (ja) 半導体装置
JPH06169047A (ja) 半導体装置
JPH0351132B2 (ja)
JPH0272654A (ja) Ｉｃパッケージ及びその接続構造
JPH06260563A (ja) トランジスタ用パッケージ

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19961203

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees