JPH06292126A - Serial data processing circuit - Google Patents

Abstract

PURPOSE:To relieve the load of software control on a master set side attended with the increase in serial data by synchronizing a signal requiring synchronization with plural synchronization pulses at a slave set side. CONSTITUTION:The serial data processing circuit receiving plural synchronization pulses P1, P2 whose phases differ from each other and provided to a slave set to which serial data including data to be synchronized with any of the plural synchronization pulses P1, P2 is provided with 1st and 2nd latch circuit sections 2, 3 provided to the synchronization pulses P1, P2 from the master set and latching input data by the synchronization pulses P1, P2 to send the data to be synchronized with the other synchronization pulse P2 among the data latched by the 1st latch circuit 2 with the synchronization pulse P1 to the 2nd latch circuit 3 latched by the synchronization pulse P2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a slave device such as a video signal processing device, and serial data sent from a master device is appropriately synchronized with a plurality of sync pulses sent separately. It relates to a processing circuit.

[0002]

As is well known, in a video tape recorder (hereinafter referred to as a VTR), on / off control of a rotary erasing head, on / off control of a recording current of a rotary video / HiFi head, and switching of a double azimuth head are performed. Embedded (Select the one with the larger double azimuth head playback output,
The function to eliminate the noise bar during special playback) control, playback screen switching control, etc. are performed.

These controls are controlled in synchronization with a video head switching signal (video head switching pulse, hereinafter referred to as V-SWP) or a HiFi head switching signal (HiFi head switching pulse, hereinafter referred to as H-SWP). Better performance. This synchronous control is
The following three methods are common.

(1) A signal requiring synchronization is asynchronously output from a master IC such as a microprocessor and latched by V-SWP or H-SWP using a D latch flip-flop shown in FIG. This also includes the case of inputting SWP to the interrupt terminal and outputting from the master IC in synchronization with this SWP. However, in this case, the signal output response performance is determined by the processing time). An example is shown in FIG.

(2) Timing pulse generating circuit (hereinafter TPG) incorporated by making the servo circuit a microprocessor
Circuit)) and use V-SWP
Alternatively, it is synchronized with H-SWP. An example is shown in FIG.

In FIG. 7, the comparator 11 compares the count value of the synchronization pulse obtained by a counter (not shown) with the reference value from the reference value FIFO 21 of the memory circuit 12, and outputs the coincidence timing pulse to the memory circuit 12 and the TPG output buffer. Send to 13.

The TPG output buffer 13 is a memory circuit 12
The TPG data from the TPG data FIFO 22 is read and synchronously output. The memory circuit 12 updates the values of the output data of the reference value FIFO 21 and the TPG data FIFO 22 each time the timing pulse is input. As a result, the servo timing is synchronized with the sync pulse.

(3) The signal is output from a serial shift type expansion IC as shown in FIG. in this case,
Set the STROBE (latch) signal to V-SWP or HS
Control to synchronize with WP. An example is shown in FIG.

By the way, recently a development of the conventional example (3), as shown in FIG. 10, a bus (I ² C bus), using a master IC 100 such as a microprocessor
Demands to change the system to control a plurality of slave ICs 201 to 20n such as video, HiFi, P / R (playback / recording) amplifiers.

In this case, it is necessary to serially transmit control data including the address / subaddress of each IC through the serial bus 300. However, since the amount of data on the bus increases, signals that need to be synchronized can be software-controlled to control V-SWP / H-SWP.
Will be difficult to sync to.

There is also a problem that a plurality of ICs cannot generally latch at the same time. Even if the slave side has a latch function other than the end of reception, it is necessary to send the same serial data to a plurality of ICs within a fixed time. Especially I ² If you try to use the C bus,
According to the standard, it can be sent only within 100 [kbit / sec], which causes a problem in temporal responsiveness.

The timing which is most problematic in terms of time is 5.5 [ms] (the shortest section of the edges of both SWPs when, for example, six heads are arranged on a rotary cylinder at equal intervals. That is, serial data must be sent to a plurality of ICs during the NTSC signaling VTR).

Especially when this is realized by a microprocessor having a servo function, even if the bus (I ² C bus)
Even if part of the I / O control is replaced with hardware (for example, serial I / O circuit hardware, serial I / O buffer FIFO), the microprocessor's servo processing involves too much real-time processing. It may not be possible depending on the timing of the factors.

[0014]

As described above, in the serial data processing circuit used in the conventional VTR or the like, when synchronizing the serial data transferred from the master device with a plurality of synchronization pulses, the serial data processing circuit on the serial bus is used. Due to the increase in the amount of data, it becomes difficult to synchronize a signal requiring synchronization with each synchronization pulse by software control.

The present invention has been made to solve the above problems, and even if the serial data increases, the slave device side can synchronize a signal required for synchronization with a plurality of synchronization pulses. An object of the present invention is to provide a serial data processing circuit capable of reducing the load of software control on the side.

[0016]

In order to achieve the above object, according to the present invention, a plurality of sync pulses having different phases are transmitted from a master device and should be synchronized with any of the plurality of sync pulses. In a serial data processing circuit provided in a slave device to which serial data including data is transferred, the serial data processing circuit includes a plurality of latch means provided for each sync pulse from the master device and latching input data with each sync pulse. The plurality of latch means latches the input data with a predetermined synchronization pulse of the plurality of synchronization pulses, and another synchronization of the data latched by the first latch circuit. And a second latch circuit for latching data to be synchronized with the pulse by the synchronization pulse.

[0017]

In the serial data processing circuit having the above structure,
When sending a large amount of data from the master device to multiple slave devices, when sending a signal to be synchronized with each of the multiple sync pulses through the serial bus, the data is sent from the master device to the slave device during a specific sync pulse. In this way, the slave side is provided with a plurality of latch means that use the edge of each sync pulse as the latch timing, and after latching the necessary signal with the specified sync pulse, only the signal that should be synchronized with another sync pulse Is sent to the latch means of the next stage and latched by the corresponding sync pulse. As a result, the master device side can manage the data transfer only with the first synchronization pulse, and the load of the responsiveness of the software processing time is reduced.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described in detail below with reference to FIGS.

FIG. 1 shows an embodiment of a serial data processing circuit according to the present invention, and shows a configuration when mounted on a slave IC. I ^{2 for} this slave IC Serial data SDA and its synchronizing clock SCL are supplied from a master device (not shown) through a two-wire serial data bus (4 is a clock transmission line, 5 is a data transmission line) such as a C bus, and other transmission is performed. A first synchronizing pulse P1 and a second synchronizing pulse P2 are supplied via the lines 10 and 20. The serial data processing circuit includes a data decoding circuit unit 1, a first latch circuit unit 2 and a second latch circuit unit 3.

First, the data decoding circuit unit 1 receives the serial data SDA from the serial data buses 4 and 5,
After the reception end is detected, the received data is decoded into a signal S11 that requires synchronization with the first synchronization pulse P1, a signal S21 that requires synchronization with the second synchronization pulse 20, and a signal S6 that does not require synchronization. To do. Since the decode signal S6 obtained here is not necessary for synchronization, it is directly led to the subsequent circuit, and the decode signals S11 and S21 are both sent to the first latch circuit section 2.

The first latch circuit section 2 latches the input decode signals S11 and S21 at the timing of the first synchronizing pulse P1. These latch signals S13,
S22 is a synchronization signal of the first synchronization pulse P1 that requires synchronization of the first synchronization pulse P1 and a synchronization signal of the first synchronization pulse P1 that requires synchronization of the second synchronization pulse P2. Since the latch signal S13 is already synchronized with the first synchronizing pulse, it is derived as it is, and the latch signal S22 is sent to the second latch circuit unit 3.

The second latch circuit section 3 latches the latch signal S22 from the first latch circuit section 2 at the timing of the second synchronizing pulse P2. Signal S2 latched here
Reference numeral 3 is a synchronization signal of the second synchronization pulse P2 that requires synchronization of the second synchronization pulse P2. In the above configuration,
The operation will be described with reference to FIGS.

When the clock SCL and the serial data SDA from the master IC are input to the slave IC and received by the data decoding circuit unit 1, the data decoding circuit unit 1 outputs the received data as the first synchronization pulse 1.
A signal S11 requiring synchronization to 0, a signal S21 requiring synchronization to the second synchronization pulse 20, and a signal S6 not requiring synchronization.
Is decoded into.

The decode signal S6 is used as it is inside or outside the slave. Decode signals S11, S2
1 is sent to the first latch circuit unit 2 and latched at the timing of the synchronization pulse P1. The latch signal S13 of the decode signal S11 is a synchronization signal that requires synchronization of the first synchronization pulse and is used as it is inside or outside the slave. The latch signal S22 of the decode signal S12 is sent to the second latch circuit unit 2 and latched at the timing of the sync pulse S20. The latch signal S23 is a synchronization signal that requires synchronization of the second synchronization pulse P2, and is used as it is inside or outside the slave.

The configuration of the above slave IC is applied to video signal processing I such as VTR video, HiFi, and reproducing / recording amplifier.
When one of C is used, there are V-SWP and H-SWP as the first and second synchronization pulses, and signals requiring synchronization are an ON / OFF signal of the rotation erasing head and a rotation video / H.
Recording current on / off signal of the iFi head (hereinafter referred to as video / HiFi recording mute signal), switching signal / embedding of the double azimuth head (function to eliminate the noise bar during special playback by selecting the one with the larger double azimuth head playback output) Signals, playback screen switching signals, etc. Here, for simplification of explanation, the slave IC is a reproducing / recording amplifier, and the serial bus is I ² The case of the C bus will be described.

2 and 3 are timing charts in the case of generating the video / HiFi recording mute signal of the reproducing / recording amplifier from the serial bus data SDA in the slave IC, respectively, at the start of recording.

2 and 3, a is video recording mute on / HiFi recording mute on, b is video recording mute on / HiFi recording mute off, c is video recording mute off / HiFi recording mute off, and d is H.
If the i-fi recording mute is on, e is control data for instructing the hi-fi recording mute off.

FIG. 2 shows a pattern when there is a margin between the timings of video recording mute and HiFi recording mute due to the phase relationship between H-SWP and V-SWP, and FIG.
The pattern in the case where there is a margin in the timing of video recording mute and HiFi recording mute is shown from the phase relationship between -SWP and V-SWP.

In the initial state, the video / HiFi recording mute is both on, and it is necessary to turn off the HiFi mute and the video recording mute in this order at the start of recording. In order to realize this timing, the master IC sequentially serially transmits the control data a, b, c to the reproducing / recording amplifier during both edges of V-SWP which is the first synchronizing pulse.

That is, the master IC is initially V-SW.
Control data a is sent to the reproducing / recording amplifier between both edges of P. The data decoding circuit unit 1 of the reproducing / recording amplifier is
After receiving the control data a, for V (video) synchronization,
Separate for H (HiFi) synchronization. The first latch circuit unit 2 latches both data separated at the edge timing of V-SWP. Further, the second latch circuit section 3 has the first
The control data d for H synchronization latched in the latch circuit unit 2 of 1 is latched at the next edge timing of H-SWP.
As a result, both the video / HiFi recording mute are turned on.

The master IC sends the control data b to the reproducing / recording amplifier in the next cycle. The data decoding circuit unit 1 of the reproducing / recording amplifier, after receiving the control data b, outputs V
Separate for synchronization and H synchronization. The first latch circuit unit 2 latches both data separated at the edge timing of V-SWP. Further, the second latch circuit section 3 latches the control data e for H synchronization latched by the first latch circuit section 2 at the next edge timing of H-SWP. As a result, only the HiFi recording mute is turned on.

The master IC further sends the control data c to the reproducing / recording amplifier in the next cycle. After the reception of the control data c, the data decoding circuit unit 1 of the reproducing / recording amplifier separates it for V synchronization and H synchronization. The first latch circuit unit 2 latches both data separated at the next V-SWP edge timing. As a result, the video storage mute is turned on after a delay of HiFi. At this time, the second
The latch circuit unit 3 of 1 latches the control data e for H synchronization latched by the first latch circuit unit 2 at the next edge timing of H-SWP. As a result, the HiFi recording mute is continuously turned on.

By the way, in the case of a VTR designed so that six heads can be placed at equal intervals on a rotary cylinder, both SWs
It is necessary to send data to a plurality of ICs during the shortest interval 5.5 ms (VTR of NTSC signaling system) at the edge of P.

On the other hand, I ² C bus is 100kbi by standard
Data can be sent only within t / sec. Therefore, it is necessary to send the address / sub-address data of each slave IC with 10 bits of data per word. The average data amount at this time is 6 words (about 60b) per IC.
it).

For this reason, in the past, video and HiF have been used.
i, the data sent to the three ICs of the reproducing / recording amplifier is 1.8 mS at the earliest, and it is 3.6 mS by halving the clock speed. In a servo microprocessor using a VTR system computer which is performing other real-time processing, control data is simply sent to three slave ICs so as to be synchronized with each head switching pulse. In this case, although it is necessary to send the data even if there is another interrupt input within 5.5 mS, it is conceivable that a problem of processing response may occur.

On the other hand, if the serial data processing circuit having the above-mentioned configuration is mounted on the slave IC, the data is sent between both edges of V-SWP, that is, within 16.6 mS (NTTR system VTR), so that the slave side You can get the timing. Therefore, the problem of processing response does not occur.

Therefore, in the serial data processing circuit having the above structure, when the master IC is a one-chip microprocessor and a large amount of data is sent to a plurality of slave ICs, the control data input by each slave IC is 1 sync pulse (eg video head switching signal)
Alternatively, even when synchronizing with a second sync pulse (for example, a HiFi head switching signal), data can be sent from the master IC to the slave IC during the first sync pulse.
After latching the necessary signal on the slave side with the first sync pulse, only the signal that is synchronized with the second sync pulse is second
Can be latched with the sync pulse.

As a result, the master IC can manage the data transfer only by the first synchronization pulse, and the burden of the responsiveness of the software processing time can be reduced even in the system having many real-time processing.

In the above embodiment, I ² Although the C bus is used for the description, other serial data transfer may be used. If a plurality of latches as in the present invention are required even in the case where serial is latched by STROBE, the load on the master can be reduced by making the circuit configuration of the slave IC the same as that of the present invention.

In the above description, the serial data is always sent to the plurality of slave ICs during the first synchronizing pulse P1, but when timing is not required, for example, in the case of refreshing, the serial data to the plurality of slave ICs is sent. Need not be sent during the first sync pulse P1.

In the description of the above embodiment, for the sake of convenience, the data decoding circuit section 1 separates the data for V synchronization and H synchronization after receiving the control data, but this is not always necessary. Of the data latched by the latch circuit unit 2, the V synchronization data may be derived as the signal S13, and the H synchronization data may be latched by the second latch circuit unit 3 and derived as the signal S23.

Further, a plurality of second latch circuit sections 3 may be arranged in parallel, and the signal S22 may be commonly latched at the same timing by the second synchronizing pulse. In addition, the signal S latched by the second latch circuit unit 3
A part or all of 22 is latched in a latch circuit unit (not shown) driven by another synchronization pulse (not shown) so that the latch circuit units are connected in series,
It is also possible to latch with synchronization pulses of different phases and send the data to be synchronized with other synchronization pulses of the latched data to the subsequent stage.

FIG. 4 shows another embodiment according to the present invention. The first and second synchronizing pulses V-SWP, H- of FIG.
The structure when multiplexing SWP and sending is shown. Reference numeral 7 is a multiplexed pulse transmission line, and 8 is a synchronous pulse separation circuit unit. The basic operation is the same as in FIG. 1, and the first and second synchronizing pulses P1 and P2 that are multiplexed and transmitted are separated by the separation circuit unit 8 and are input to the corresponding latch circuit units 2 and 3. It was done like this. Needless to say, various modifications can be made in the same manner without departing from the scope of the present invention.

[0044]

As described above, according to the present invention, even if the serial data increases, the signal required for synchronization can be synchronized with a plurality of synchronization pulses on the slave device side, and software control on the master device side is possible. It is possible to provide a serial data processing circuit capable of reducing the load on the serial data processing circuit.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing the configuration of an embodiment of a serial data processing circuit according to the present invention.

FIG. 2 is a timing chart showing a pattern when there is a margin in timing of video recording mute and HiFi recording mute from the phase relationship between H-SWP and V-SWP in the embodiment.

FIG. 3 is a timing chart showing a pattern when there is a margin in timing of video recording mute and HiFi recording mute from the phase relationship between H-SWP and V-SWP in the embodiment.

FIG. 4 is a block circuit diagram showing another embodiment according to the present invention.

FIG. 5 is a block circuit diagram showing a configuration of a conventional VTR when a D latch flip-flop is used for various synchronization controls.

6 is a timing chart showing an example of the synchronization control timing of FIG.

FIG. 7 is a block circuit diagram showing a configuration of a conventional VTR in which a timing pulse generation circuit incorporated in a servo circuit as a microprocessor is used for various synchronization controls.

FIG. 8 is a block circuit diagram showing a configuration in the case where an expansion IC such as a serial shift type is used for various synchronization controls in a conventional VTR.

9 is a timing chart showing an example of the synchronization control timing of FIG.

FIG. 10 is a block circuit diagram showing a configuration of a serial bus control system which has been recently demanded.

[Explanation of symbols]

11 ... Comparator, 12 ... Memory circuit, 21 ... Reference value FIFO, 22 ... TPG data FIFO, 13 ... TPG
Output buffer, 100 ... Master IC, 201 to 20n
... Slave IC, 300 ... Serial bus, 1 ... Data decoding circuit section, 2 ... First latch circuit section, 3 ... Second latch circuit section, 4 ... Clock transmission line, 5 ... Data transmission line,
7 ... Multiplexed pulse transmission line, 8 ... Synchronous pulse separation circuit section,
SDA: serial data, SCL: synchronization clock, P
1 ... 1st synchronizing pulse, P2 ... 2nd synchronizing pulse, V-
SWP ... video head switching signal, H-SWP ... HiHi
Head switching signal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H04N 5/93 D 4227-5C H04Q 9/00 7170-5K

Claims (7)

[Claims] 1. A serial device provided in a slave device, wherein a plurality of sync pulses having different phases are transmitted from a master device and serial data including data to be synchronized with any of the plurality of sync pulses is transferred. The data processing circuit comprises a plurality of latch means provided for each sync pulse from the master device and latching the input data with each sync pulse, wherein the plurality of latch means are among the plurality of sync pulses. A first latch circuit for latching the input data by a predetermined sync pulse, and a second latch circuit for latching data to be synchronized with another sync pulse of the data latched by the first latch circuit by the sync pulse. And a latch circuit for the serial data processing circuit. 2. The serial device according to claim 1, wherein the slave device is a video signal processing device, and each of the plurality of synchronization pulses is synchronized with a vertical synchronization signal of a video signal handled by the video signal processing device. Data processing circuit. 3. The slave device is a video signal processing device used in a magnetic recording and reproducing device using a rotary head equipped with a pair of video heads and a pair of audio heads, and the plurality of synchronization pulses are switching signals of the video heads. And a voice head switching signal.
The described serial data processing circuit. 4. The slave device inputs, together with the serial data, a clock synchronized with the data through a bus in which data and a clock synchronized with the data are transmitted through different lines, and based on the clock, the plurality of latches are input. 2. The serial data processing circuit according to claim 1, wherein each serial data is input to the means. 5. The slave device according to claim 1, further comprising a sync pulse separating means for separating the plural sync pulses when the plural sync pulses are multiplexed and transmitted. Serial data processing circuit. 6. The slave device comprises, in a serial data input stage, asynchronous data separation means for separating data that does not need to be synchronized with the plurality of synchronization pulses from the input serial data. The described serial data processing circuit. 7. The serial data processing circuit according to claim 1, wherein the serial data is transferred in a state where individual data is inserted between both edges of the specified synchronization pulse.