JPH1168879A - Communication circuit and communication circuit control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To communicate with an external circuit without reducing a communication rate by changing an internal data latch timing against plural modes which have different synchronization of a synchronizing signal by a timing generator. SOLUTION: In the case of exchanging data between a microcomputer 101 and a module 2 through a communication circuit MCI 1, an input register 4 detects a bit that designates whether a standard operation SD mode from the microcomputer 101 or a high compression SDL mode and inputs it to a timing generator 7 that is installed on the MCI 1. Thereby, a latch timing of the register 4 in the SDL mode becomes a timing which makes both edges of a switching position SWP signal reference and synchronizes with a synchronizing signal in the microcomputer 101 whose frequency is equal to the SWP signal in the SD mode. The timing of serial communication for the MCI 1 is controlled by a chip select signal CS from the microcomputer 101 and a serial clock signal SCK signal and makes communication timing constant without depending on operation modes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a communication circuit for transmitting and receiving information signals to and from an external electronic circuit, and a communication circuit control program.

[0002]

2. Description of the Related Art A so-called digital video camcorder (DVC) for recording and reproducing digital signals on a magnetic tape by using a rotary head device has been proposed. The rotary head device of this digital video camcorder is configured such that a pair of magnetic heads are arranged on a rotary drum so as to face 180 degrees.

In this digital video camcorder, when the operation mode is an SD (Standard Definition) mode, a 150 Hz SWP (Sw) signal is used as a signal for switching between the two magnetic heads of the rotary head device.
itching Position) signal. In the communication circuit formed as a communication circuit for the digital video camcorder, in communication with the microcomputer serving as the control circuit of the digital video camcorder, latching of internal data and communication with the microcomputer are performed using the SWP signal as a synchronization signal. Is going. The microcomputer is
Communication with the communication circuit is performed based on an internal synchronization signal of the microcomputer having the same phase difference and frequency as the SWP signal.

[0004]

In the above-described digital video camcorder, when the operation mode is set to the SDL (high compression SD) mode, the frequency of the SWP signal becomes lower than the frequency of the SWP signal in the SD mode. It is 75 Hz, which is 1/2. At this time, the communication circuit is SD
When communication is performed based on one edge of the SWP signal on the communication circuit side in the same manner as in the mode, the communication timing viewed from the microcomputer side is once for two cycles of the internal synchronization signal of the microcomputer. The speed will be reduced. Thereby, the responsiveness between the communication circuit and the microcomputer decreases.

Accordingly, the present invention has been proposed in view of the above situation, and has been proposed in a plurality of modes having different synchronizing signals, without lowering the communication speed, between external modes such as a microcomputer. An object of the present invention is to provide a communication circuit capable of communicating information signals and a communication circuit control program for realizing such a communication circuit.

[0006]

In order to solve the above-mentioned problems, a communication circuit according to the present invention provides a constant circuit by changing internal data latch timings for a plurality of modes having different periods of a synchronization signal. The communication is performed while maintaining the communication timing.

Further, a communication circuit control program according to the present invention causes a data latch timing inside a communication circuit to be changed in accordance with a cycle of a synchronization signal, and the communication circuit controls the data latch in a plurality of modes having different synchronization signal cycles. The communication is performed while maintaining the communication timing.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

In this embodiment, a communication circuit according to the present invention is mounted on a so-called digital video camcorder. This communication circuit, as shown in FIG.
The first module (MCI) 1 is built in the (integrated circuit) and performs communication between the external microcomputer 101 and the second module 2. The function of the first module 1 is to transfer data from the microcomputer 101 to a communication register (input) 3 as shown in FIG.
And the data is passed to the second module 2 via the input register 4, and at the same time, the data from the second module 2 is sent to the microcomputer 101 via the output register 5 and the communication register (output) 6. Also,
The first module 1 includes a microcomputer 10
A latch timing generator 7 for instructing the input register 4 and the output register 5 to latch based on the signal 1 and the control of the input register 4 is provided.

The communication in the first module 1 of the communication circuit is performed by a microcomputer 101 as shown in FIG.
Is controlled by a chip select signal (CS) and a serial lock signal (SCK) asynchronously transmitted from the CPU.

The sequence until data from the microcomputer 101 is sent to the second module 2 will be described. Data from the microcomputer 101 is serially taken into the communication register (input) 3 in synchronization with the serial clock signal when the chip select signal is at “L” level. This data is taken into the input register 4 from the communication register (input) 3 in synchronization with the rise of the 150 Hz SWP signal which is a signal for switching between the two magnetic heads of the rotary head device in the digital video camcorder, and is read in parallel to the second register. Module 2
Distributed to

Next, the flow of data until the data from the second module 2 is taken into the microcomputer 101 will be described. In this communication circuit, different processing is performed at the “H” level and the “L” level of the SWP signal. That is, data during which the SWP signal is at “H” level
The data is taken into the output register 5 in synchronization with the fall of the signal, and the data during the "L" level is taken into the output register 5 in synchronization with the fall of the SWP signal. Also, SWP
It is assumed that data not related to the signal is taken in synchronization with the rise of the SWP signal. The second module 2 outputs parallel data. From the output register 5 to the communication register (output) 6, for example, latch is performed in synchronization with the fall of the chip select signal.
The data in the communication register (output) 6 is serially transferred to the microcomputer 101 in synchronization with the serial clock signal when the chip select signal is at the “L” level.

Even if the operation mode of the digital video coder is switched between the SD mode and the SDL mode under the control of the microcomputer 101, the communication circuit operates in the digital video coder operation mode by the data from the microcomputer 101. Regardless, communication at a constant communication timing is realized.

That is, a part of the serial data sent from the microcomputer 101 includes the SD mode and the S mode.
Assign a bit to specify one of the DL modes.
Then, the output of the mode designation bit of the input register 4 is input to the timing generator 7 inside the first module 1. Thereby, the latch timing of the input register 4 in the SDL mode is a timing based on both edges of the SWP signal as shown in FIG. Similarly,
The latch timing of the output register 5 follows the following theory. That is, data during which the SWP signal is at the “H” level is taken into the output register 5 on the basis of the falling edge of the SWP signal. Data during which the SWP signal is at the “L” level is taken into the output register 5 on the basis of the rising edge of the SWP. SWP
Data that does not depend on whether the signal is at the “H” level or the “L” level is taken in based on both edges of the SWP signal.

In the SDL mode as opposed to the SD mode, S
The frequency of the WP signal becomes 1/2. However, even in the SDL mode, the microcomputer 101 does not
It is synchronized with the internal synchronization signal of the microcomputer 101 having the same frequency as the SWP signal in the mode. The timing of serial communication of the communication circuit is the microcomputer 1
01 is controlled by a chip select signal, which is an asynchronous signal, and a serial clock signal. By switching the latch timing of the communication circuit between the SDL mode and the SD mode, the communication timing with the microcomputer 101 can be constant regardless of these operation modes.

[0016]

As described above, in the communication circuit according to the present invention, there is no need to determine the operation mode on the external circuit side such as a microcomputer to switch the communication timing. The storage memory can be reduced and cost can be reduced.

For example, in a digital video camcorder, the response of the IC to the instruction of the microcomputer in the SDL mode can be made faster by setting the communication timing based on both edges of the SWP signal. Further, by setting the communication timing based on both edges of the SWP signal, the internal state of the IC in the SDL mode can be quickly reflected on the operation of the microcomputer.

That is, according to the present invention, in a plurality of modes having different synchronization signals, the communication speed is not reduced.
It is possible to provide a communication circuit capable of communicating information signals with an external circuit such as a microcomputer and a communication circuit control program for realizing such a communication circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a communication circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a first module of the communication circuit.

FIG. 3 is a time chart showing an operation in an SD mode of the communication circuit.

FIG. 4 is a time chart showing an operation of the communication circuit in an SDL mode.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 1st module, 2nd module, 7 timing generator, 101 microcomputer

Claims (3)

[Claims] 1. A communication circuit for performing communication while maintaining a constant communication timing by changing internal data latch timing for a plurality of modes having different synchronization signal periods. 2. A data latch timing corresponding to one edge of a synchronizing signal is adopted for a first mode.
2. The communication circuit according to claim 1, wherein the data latch timing corresponding to both edges of the synchronization signal is adopted for the mode. 3. A data latch timing inside a communication circuit is changed according to a cycle of a synchronization signal, and communication is performed while maintaining a constant communication timing by the communication circuit in a plurality of modes having different synchronization signal cycles. A communication circuit control program characterized by the above-mentioned.