JPH036139A - Time base compressing operation circuit - Google Patents

Abstract

PURPOSE:To execute a time base compressing operation being suitable for a digital transmission by providing each counter of a write address and a read- out address, an address switching means of a buffer memory, a write/read-out control means, and a write address initializing means. CONSTITUTION:An input data train A is made parallel and latched by putting a synchronizing pattern at every prescribed bit, and written in a buffer memory 7 through a 3-state buffer 4. Subsequently, it is read out and latched, and converted to series, by which an output data train A' is obtained. In this case, a write address counter 9 and a read-out address counter change address information periodically, and like a burst, respectively. Also, an address switching means 13 switches counters 9, 11 and designates an address of a buffer memory 7. When the information is read out like a burst the memory, a control circuit 10 switches the address switching means 13, and also, avoids a collision by controlling read-out and write, and allows it to execute write. Also, an initializing means 16 allows a write address to precede by preceding a read-out address. According to this constitution, even in the case a phase relation of a write time and a read-out time is not constant, a time axis compression can be executed by avoiding a competition of R/W.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is a method for time-axis multiplexing information signals such as PCM audio signals onto blank portions of PCM video signals such as high-definition and digitally transmitting the information signals. The present invention relates to a time base compression operation circuit suitable for.

(Prior Art and Problems to be Solved by the Invention) Circuits that perform time axis compression using a buffer memory have conventionally existed. However, there has not been a time-base compression operation circuit in which the cycle of reading output data in bursts is not an integral multiple of the cycle of writing input data.

As mentioned above, when the phase relationship between writing and reading is not constant, there is a problem that writing and reading conflict at certain times.

SUMMARY OF THE INVENTION An object of the present invention is to provide a time base compression operation circuit that can avoid the above-mentioned conflict with an hour wheel configuration when the phase relationship between writing and reading is not constant.

(Means for Solving the Problems) The time base compression operation circuit of the present invention has a first
The data string is converted into a second data string with a transmission rate Pa (Fo > Fi) arranged in bursts at a period that is not an integer multiple of the transmission rate Fi, and the data in the first data string is compared to the data in the second data string. In the time axis compression operation circuit that compresses the time axis by inserting dummy data and data when there is insufficient data, a write address counter that periodically changes address data, a read address counter that changes address data in a burst pattern, address switching means for specifying an address for a buffer memory that stores data of a first data string by switching output address data from a write address counter and output address data from a read address counter; In addition to switching the address switching means to write the data of the first data string so as not to conflict with reading, the control means for controlling read/write of the buffer memory and the write address so as to make the write address precede the read address. The invention is characterized by comprising an initializing means for initializing the.

(Function) In the present invention having the above configuration, the buffer memory has output address data from a write address counter that periodically changes address data, and output data from a read address counter that changes address data in a burst manner. The address is switched by the address switching means to designate the address of the buffer memory. However, the switching means can switch between reading and writing data in bursts without causing a collision, and a collision occurs when writing the first data string to the buffer memory and when reading data from the buffer memory. Never.

Furthermore, when initialization is performed by the initialization means, the write address will precede the read address.
The written data is read.

(Example) The present invention will be explained below with reference to Examples.

First, the background leading to the present invention will be specifically explained. The present invention has a sampling frequency of 4 for audio signals with a band of 20 kHz.
A/D conversion is performed at 8 kHz, quantization bit number 16 bits (linear), and the resulting 768 kb/s bit string is converted into a burst-like bit string of 37.125 Mb/s at the period of the high-definition horizontal synchronization signal for transmission. a transmitter,
From a series of 37.125 Mb/s bit streams, audio signal bit streams that exist in bursts at the period of the high-definition horizontal synchronization signal are extracted, and the original series of 768 kb/s is extracted.
This circuit was invented as a time-base compression operation circuit suitable for an audio signal transmission device of a high-definition digital in-office optical transmission device, which includes a receiving section that converts the signal back into a bit string and performs DA conversion. In this embodiment, in the above case, the audio signal is A with a sampling frequency of 48 Hz and a quantization bit number of 16 bits.
The 768 kbps data string obtained by /D conversion is compressed on the time axis to create a high-definition horizontal synchronizing signal (33,
37.125Mbp in bursts at a frequency of 75kHz)
s data string is generated and this data string is multiplexed into a video signal.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a schematic diagram showing time axis compression multiplexing.

The 768 kbps NRZ signal after A/D conversion is converted into a 1,536 Mbps RZ double signal data string A with an internal frame synchronization signal added [Figure 2 (a) However, in Figure 2 (a), a periodic pattern is added. The condition is indicated. ]. Since this is multiplexed into a video signal, one frame consists of 45
line [Figure 2 (C)], approximately 1.3msMb
ps) can be multiplexed, so 204
8 bits as shown in Figure 2 (b) < 48 bits x 42 + 32
We will divide it into 10 bits and 10 bits.

This data string is denoted as A''.

The buffer memory 7 has a capacity for two frames, and the timing control section 20 on the write control side and the timing control section 30 on the read control side of the buffer memory 7 operate independently.

The timing control unit 20 is the writing side system control circuit 8
The writing side system control circuit 8 outputs a frame synchronization signal WSYN every 2048 bits to the frame synchronization pattern addition circuit 2, and outputs a signal -LCH (192k
A latch strobe signal of Hz) is output to the latch circuit 3, and a clock signal of a constant period is output to the write address counter 9,
The address data of 00000000 (511) is output. Here, the buffer memory 7 has one address of 8 bits.

The timing control section 30 is the read-side system control circuit 1
0, a read address counter 11, and a line power counter 12 that counts the number of lines (horizontal synchronization signal number).The read side system control circuit 10 outputs a clock signal to the read address counter 11, and the read address counter 11 outputs a clock signal to the read address counter 11, and the read address counter 11 outputs a clock signal to the read address counter 11. (0) ~100000
Address designation of 000 (511) is performed in six addresses per line, and a shift register load signal RLD for parallel-to-serial conversion is output to the parallel-to-serial conversion circuit 6.

The input data string A is sent to the serial-parallel converter circuit 1.
The data is supplied to the frame synchronization pattern adding circuit 2, where it is converted into 8-bit parallel data, and a frame synchronization pattern is added every 2048 bits. The data string A parallel-converted via the frame synchronization pattern addition circuit 2 is latched in the latch circuit 3, and the latch data of the latch circuit 3 is transferred via the 3-state buffer 4 to the buffer memory 7.
supply to.

The data read from the buffer memory 7 is sent to the latch circuit 5.
The latch data of latch circuit 5 is latched in parallel.
The serial conversion circuit 6 converts it into a serial data string and outputs it.

On the other hand, the read-side system control circuit 10 supplies an initialization signal to the initialization circuit 14 during initialization, and the write-side system control circuit 8 sets the write address to an address that precedes the read address by one frame. is controlled so that the write-side address precedes the read-side address by one frame. Further, in order to avoid conflicts between writing and reading, an address selection circuit 13 that receives signals from the reading side system control circuit 10 and a write command signal generation circuit (indicated as a ridge generation circuit in FIG. 1) 15 is the provision.

The read-side system control circuit 10 sends the write mode/read mode selection signal R/W to the address selection circuit 1.
3, the address data from the write address counter 9 and the address data from the read address counter 11 are selected and supplied to the buffer memory 7. At the same time, the signal R/W is supplied to the 3-state buffer 4 as an enable instruction signal, and when the signal R/W is at a high potential, the 3-state buffer 4 is enabled, and the signal R/W is a strobe for latching read data. It is supplied as a signal to the latch circuit 5, and when the signal R/- is at a low potential, the data read from the buffer memory 7 is latched by the latch circuit 5. Further, the signal W and the write period signal WEW from the write system circuit 8 are supplied to the write command signal generating circuit 15 to generate a write command signal basket and supply it to the buffer memory 7.

For example, as shown in FIG. 3, the write command signal generation circuit 15 uses the write period signal i as a data input, and receives the signal p-
D flip-flop 15. which uses as a clock signal. ,
Q output of D flip-flop 151 and buffer amplifier 1
It is composed of an OR gate 15 which receives a signal "C" via a signal 5□, and generates a write command signal snore at the timing shown in FIG. 5 in response to a write period signal - OPEN and a signal R/W.

1, 5361'1bp converted to the above RZ code
The data string of s is converted into a parallel 8-bit data string by a serial-parallel conversion circuit 1, and the first 6 bits become a synchronization pattern in accordance with a frame synchronization signal WSYN every 2048 bits. The parallel 8-bit data string passed through the frame synchronization pattern adding circuit 2 is latched by the input transmission rate divided by 8 signal WLCH (192 kHz).

The write-side transmission lock is as shown in FIG. 4(a), and in FIG. 4(a), "0"・-" 204
7 "is in the first frame" 2048 "..."
4095'' is for the second frame, and the frame synchronization signal WSYN is as shown in FIG. 4(b).The signal WLCH is as shown in FIG. 4(c).

On the other hand, the latch output of the latch circuit 3 is the state buffer 4
The address “000000000” by the write address counter 9 is supplied to the buffer memory 7 through
(0)”～” Written to 100000000 (511). This writing is performed when the write command signal -E is at a low potential. The write address output from the write address counter 9 is shown in FIG.
) as shown. In Fig. 4(d), IF O'
1~”255” is in the first frame, “256”~”
511'' is for the second frame.

Further, the writing period signal outputted from the writing side system control circuit 8 is as shown in FIG. 4(e),
Signal R output from the read-side system control circuit 10
/- as shown in FIG. 4(g).

As is clear from FIG. 5, the write command signal -E is as shown in FIG. 4(h).
Signal R/W and write command signal -B are enlarged in Fig. 4 (
k), FIG. 4(p), and FIG. 4(q).

The horizontal synchronizing signal is input at the timing shown in FIG. 4(f). The horizontal synchronizing signal is expanded as shown in FIG. 4(m).

On the read side, the buffer memory 7 has an address selection circuit 13
The address data "oooooooo" output from the read address counter 11 is supplied via the address counter 11.

The read 8-bit parallel data addressed by 0(0)" to "100000000(511)" is once latched by the latch circuit 5 at the timing of the signal R/-, and the latch output of the latch circuit 5 is Fourth
It is output as serial data A' by the shift register load signal RLD shown in FIG.

Here, the reading side transmission rate is as shown in FIG. 4<f). Changes in write address data and changes in read address data are not constant over time because data is output in bursts. First, for the 48 bits assigned to one line, 48 bits (8 bits x 6) are obtained with a sharp period. cycle 2
The 6 counts in 15 μs are synchronized with the horizontal synchronization signal,
45 lines are repeated at a period of 26.9 μs (1/33.75 MHz).

However, if the above steps are repeated over 45 lines, 2160 points per frame [=48 bits x 451
becomes. However, the reading side system control circuit 10
is when read address counter 1 outputs address data for 2048 bits, that is, 112 bits.
The clock transmission to the address counter is temporarily stopped for bits (2160-2048), and the shift register load signal RLD is held at a high potential. Therefore, the read address is as shown in FIG. 4(i). An enlarged view of the read address is as shown in FIG. The frame synchronization is maintained, and the parallel-to-serial conversion circuit 6 outputs 48 bits 42 times, 32 bits once, O bit twice, as shown in FIG. 4(j).
Output in synchronization with the horizontal synchronization signal. An enlarged view of the data string A° output from the parallel-serial conversion circuit 6 is shown in FIG. 4(s).

In order to avoid the above-mentioned conflict between the write timing and the read timing, this embodiment uses two signals, the signal R/W and the write command signal to the buffer memory 7, as the write/read mode selection signal.

The signal R/W is in the write mode when the read data transmission rate divided by 8 signal R/W is at a high potential, and is in the read mode when the signal R/W is at a low potential. Also, in the write command signal WE, the change point of the write address and write data is signal 1? The circuit is prevented from malfunctioning by overlapping with the /H write mode.

The write command signal WE is sent to the write side system control circuit 8.
No matter what phase the read timing appears with respect to the write timing, both operations are generated by the logic of the write period signal 10 and the signal R/W output from the signal 1/2 and the write command signal layer. Since these are performed alternately, there will be no data loss.

Furthermore, the buffer memory 7 has a capacity for two frames (addresses "01" to "511"), and writing precedes reading by one frame.

This is schematically shown in FIG. However, if the write address and read address operate chaotically, such as when the power is turned on, the initialization circuit 14 forces the write-side system control circuit 8 that includes the address to have an offset of one frame with respect to the read address. preset. The time required for signal processing of one frame is the same for both writing and reading. Therefore, once initialization is performed, the frame-by-frame offset is kept constant thereafter.

(Effects of the Invention) As explained above, according to the present invention, the address switching means is controlled to write the data of the first data string so as not to conflict with reading data in burst form from the buffer memory, and the buffer memory is Since reading and writing are controlled, even if the read address counter and the write address counter operate independently, there will be no collision between writing and reading.

In addition, since the write address is made to precede the read address by the initialization means, reading is not performed before writing, and input information is accurately time-axis compressed in a short processing time (1 frame). can do.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a schematic diagram showing time axis compression and multiplexing in one embodiment of the present invention. FIG. 3 is a circuit diagram of a write command signal generation circuit in one embodiment of the present invention. FIG. 4 is a timing diagram for explaining the operation of one embodiment of the present invention. FIG. 5 is a timing diagram for explaining the operation of the write command signal generation circuit in one embodiment of the present invention. FIG. 6 is a schematic diagram showing changes in the write address and read address of the buffer memory in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Serial-parallel conversion circuit, 2... Frame synchronization pattern addition circuit, 3 and 5... Latch circuit, 4... 3-state buffer, 6... Parallel-serial conversion circuit, 7. ...Buffer memory, 8...Writing side system control circuit, 9...Writing address counter, 10...Reading side system control circuit, 1
DESCRIPTION OF SYMBOLS 1... Read address counter, 12... Line counter, 13... Address selection circuit, 14... Initialization circuit, 15... Write command signal generation circuit.

Claims (1)

[Claims] A transmission rate Fo that arranges the first data string of the transmission rate Fi in a burst pattern at a period that is not an integral multiple of the transmission rate Fi.
A time axis compression operation circuit that converts into a second data string (Fo>Fi) and inserts dummy data to compress the time axis when the data of the first data string is insufficient for the data of the second data string. , there is a write address counter that periodically changes address data, a read address counter that changes address data in a burst pattern, and a switch between the output address data from the write address counter and the output address data from the read address counter. an address switching means for specifying an address for a buffer memory that stores data of one data string; and an address switching means for switching the address switching means to write the data of the first data string so as not to conflict with reading data in a burst form from the buffer memory; 1. A time axis compression operation circuit comprising: control means for controlling reading and writing of a buffer memory; and initialization means for initializing a write address so that the write address precedes the read address.