JPH06103867B2 - Time axis compression operation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention is for digital transmission of information signals such as audio signals converted into PCM in a blank portion of a video signal converted into PCM such as high-definition and time-division multiplexed. The present invention relates to a time axis compression operation circuit suitable for.

(Prior Art and Problems to be Solved by the Invention) A circuit for performing time base compression using a buffer memory has existed conventionally. However, there is no time axis compression operation circuit when the cycle of reading output data in bursts is not an integral multiple of the cycle of writing input data.

As described above, if the phase relationship between writing and reading is not constant, there is a problem that writing and reading compete at a certain time.

An object of the present invention is to provide a time base compression operation circuit capable of avoiding the above competition with a simple configuration when the phase relationship between writing and reading is not constant.

(Means for Solving the Problem) In the time-base compression operation circuit of the present invention, the transmission rate Fo (Fo> Fi) in which the first data string of the transmission rate Fi is arranged in a burst at a cycle that is not an integral multiple of the transmission rate Fi In the time axis compression operation circuit for converting into the second data string of (1) and inserting the dummy data by inserting dummy data when the data of the first data string is insufficient for the data of the second data string, Write address counter for changing address data, a read address counter for changing address data in burst form, and output address data from the write address counter and output address data from the read address counter to switch the first data string. Address switching means for specifying the address of the buffer memory that stores data, and burst data from the buffer memory. The address switching means is switched so as to write the data of the first data string so as not to conflict with the reading of the data, and the control means for controlling the read / write of the buffer memory and the write address so as to precede the read address It is characterized by comprising an initialization means for initializing an address.

(Operation) In the present invention having the above-described configuration, the buffer memory has the output address data from the write address counter that periodically changes the address data and the output data from the read address counter that changes the address data in burst form. The address is switched by the address switching means, and the buffer memory is addressed. However, when reading and writing data in bursts, both are switched by the switching means without collision, and collision occurs when writing the first data string in the buffer memory and when reading data from the buffer memory. There is no such thing.

Furthermore, when initialization is performed by the initialization means, the write address precedes the read address,
The written data is read.

(Examples) Hereinafter, the present invention will be described with reference to Examples.

First, the background leading to the present invention will be specifically described. The present invention, the sampling frequency 48kHz, the audio signal of the band 20kHz,
768 obtained by AD conversion with 16-bit quantization line (straight line)
A bit string of kb / s in the period of the HDTV horizontal sync signal
A transmission unit for converting and transmitting to a 37.125 Mb / s burst-shaped bit string, and extracting a bit string of a voice signal that exists in a burst form at the cycle of the HDTV horizontal sync signal from a series of 37.125 Mb / s bit strings, Original series of 768kb / s
The invention was invented as a time axis compression operation circuit suitable for an audio signal transmission device of an optical transmission device in a high-definition digital station, which is composed of a receiving unit for converting to a bit string of the above and performing DA conversion.
In the present embodiment, in the above case, that is, a sampling frequency of 48 Hz, a 768 kbps data string obtained by A / D conversion with a quantization bit number of 16 bits is compressed on the time axis,
An example is shown in which a 37.125 Mbps data string is generated in bursts at the cycle of a high-definition horizontal sync signal (33.75 kHz), and this data string is multiplexed with a video signal.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a schematic diagram showing time-axis compression multiplexing.

The 768kbps NRZ signal after A / D conversion is the data string A of the 1.536Mbps RZ signal with the internal frame synchronization signal added. [Fig. 2 (a) However, Fig. 2 (a) shows the state with the periodic pattern added. It is indicated by. ]]. Since this is multiplexed with the video signal, if one frame consists of 45 lines [Fig. 2 (c)], about 1.3ms Since 2048 bits (1.3 ms × 1.536 Mbps) data can be multiplexed with 2048 bits, as shown in Fig. 2 (b).
It will be divided into 48 bits x 42 + 32 bits + 0 bits + 0 bits. This data string is referred to as A '.

The buffer memory 7 has a capacity of 2 frames, and the timing control unit 20 on the write control side and the timing control unit 30 on the read control side of the buffer memory 7 operate independently.

The timing controller 20 comprises a write side system control circuit 8 and a write address counter 9, and the write side system control circuit 8 is a frame synchronization pattern addition circuit 2
A frame synchronization signal ▲ ▼ is output for every 2048 bits, a latch strobe signal of the input transmission rate divided by 8 signal WLCH (192 kHz) is output to the latch circuit 3, and a clock signal of a constant cycle is output to the write address counter 9. It outputs the address data of 000000000 (0) to 100000000 (511). Here, the buffer memory 7 has one address of 8 bits.

The timing control unit 30 is a read side system control circuit 10,
It consists of a read address counter 11 and a line counter 12 that counts the number of lines (the number of horizontal synchronization signals). The read side system control circuit 10 outputs a clock signal to the read address counter 11, and the read address counter 00
Addressing from 0000000 (0) to 100000000 (511)
6 addresses per line and shift register load signal RLD for parallel-serial conversion
To the parallel-serial conversion circuit 6.

The input data string A is a serial-parallel conversion circuit 1
To the 8-bit parallel data and supplied to the frame synchronization pattern adding circuit 2 to add a frame synchronization pattern every 2048 bits. The parallel-converted data string A via the frame synchronization pattern adding circuit 2 is latched in the latch circuit 3, and the latched data of the latch circuit 3 is supplied to the buffer memory 7 via the 3-state buffer 4.

The data read from the buffer memory 7 is the latch circuit 5
And latch data of the latch circuit 5 is parallel-
The serial conversion circuit 6 converts the serial data string and outputs the serial data string.

On the other hand, an initialization signal is supplied from the read side system control circuit 10 to the initialization circuit 14 at the time of initialization, and the write side system control circuit 8 is controlled so that the write address is an address preceding the read address by one frame. And the write side address is 1 more than the read side address.
Advance by a frame. Further, in order to avoid a collision between writing and reading, an address selection circuit 13 and a write command signal generation circuit (indicated by ▲ ▼ generation circuit in FIG. 1) for receiving a signal from the read side system control circuit 10 There are fifteen.

From the read side system control circuit 10, write mode
The read mode selection signal / W is supplied to the address selection circuit 13, and the address data from the write address counter 9 and the address data from the read address counter 11 are selected and supplied to the buffer memory 7. Signal at the same time
/ W is supplied to the 3-state buffer 4 as an enable instruction signal, and when the signal / W is at high potential, the 3-state buffer 4
And the signal / W is supplied to the latch circuit 5 as a strobe signal for latching the read data, and the data read from the buffer memory 7 is latched by the latch circuit 5 when the signal / W has a low potential. To do. further,
The signal / W and the write period signal ▲ ▼ are supplied from the write system circuit 8 to the write command signal generation circuit 15, and the write command signal ▲ ▼ is generated and supplied to the buffer memory 7.

Write command signal generating circuit 15, for example as shown in FIG. 3, and the write period signal ▲ ▼ data input, D flip-flops 15 ₁ to the signal / W as a clock signal,
It is composed of an OR gate 15 ₃ which receives the Q output of the D flip-flop 15 ₁ and the signal / W via the buffer amplifier 15 ₂ at the timing shown in FIG. 5 by the write period signal ▲ ▼ and the signal / W. Write command signal ▲ ▼
To occur.

The 1.536Mbps data string converted to the above RZ code is converted to a parallel 8-bit data string by the serial-parallel conversion circuit 1, and a frame synchronization signal for every 2048 bits
According to ▼, the first 6 bits become the synchronization pattern.
The parallel 8-bit data string via the frame synchronization pattern adding circuit 2 is the input transmission rate divided by 8 signal WLCH (192 kH
z) latched.

The write side transmission clock is as shown in FIG. 4 (a), and in FIG. 4 (a), "0" ... "2047" is for the first frame and "2048" ... "4095" is for the second frame. Therefore, the frame synchronization signal ▲ ▼ is as shown in FIG. 4 (b). The signal WLCH is as shown in FIG. 4 (c).

On the other hand, the latch output of the latch circuit 3 is the state buffer 4
Is supplied to the buffer memory 7 through the write address counter 9 from the address “000000000 (0)” to
“100000000 (511) is written. This writing is performed when the write command signal ▲ ▼ is at a low potential. The write address output from the write address counter 9 is as shown in FIG. 4 (d). In Fig. 4 (d), "0" to "255" are in the first frame,
"256" to "511" are for the second frame. The write period signal ▲ ▼ output from the write side system control circuit 8 is as shown in FIG. 4 (e), and the signal / W output from the read side system control circuit 10 is shown in FIG. 4 (g). As shown in. The write command signal WE is as shown in FIG. 4 (h), as is apparent from FIG. The enlargement of the write period signal ▲ ▼, the signal / W, and the write command signal ▲ ▼ are shown in FIGS. 4 (k), 4 (p) and 4 (q).

The horizontal synchronizing signal is input at the timing shown in FIG. The expansion of the horizontal synchronizing signal is as shown in FIG. 4 (m).

On the read side, the buffer memory 7 receives the address data “000000000 (0)” to “1000000” output from the read address counter 11 supplied through the address selection circuit 13.
The 8-bit parallel data read by being addressed by "00 (511)" is once latched by the latch circuit 5 at the timing of signal / W, and the latch output of the latch circuit 5 is shown in FIG. 4 (r). It is output as serial data A ′ by the shift register load signal ▲ ▼.

Here, the read side transmission rate is as shown in FIG. The change of write address data is a cycle of 5.2μ
s However, the change in the read address data is not constant in time because the data is output in bursts.
First, the period is 21 for 48 bits assigned to one line.
5ns Is output 6 times. Therefore, 48 bits [8 bits x
6] is obtained. Counting 6 times in a cycle of 215 μs is synchronized with the horizontal sync signal and 45 in a cycle of 26.9 μs (1 / 33.75 KHz).
The line is repeated.

However, if the above is repeated over 45 lines, 1
There are 2160 bits [= 48 bits x 45] between frames. However, when the read address counter 11 outputs the address data for 2048 bits, that is, the read side system control circuit 10, that is, 112 bits (2160−2048),
The clock transmission to the address counter is temporarily stopped and the shift register load signal ▲ ▼ is held at a high potential.
Therefore, the read address is as shown in FIG. An enlarged view of the read address is as shown in FIG. Further, unnecessary data is not output from the parallel-serial conversion circuit 6 and the frame synchronization is maintained. From the parallel-serial conversion circuit 6, as shown in FIG. Bit once,
The 0 bit is output twice in synchronization with the horizontal sync signal.
An enlarged view of the data string A'output from the parallel-serial conversion circuit 6 is as shown in FIG. 4 (s).

In order to avoid the above-mentioned conflict between the write timing and the read timing, this embodiment uses the signal / W as the write / read mode selection signal and the write command signal to the buffer memory 7.
Two signals of ▼ are used. Signal / W is a cycle of 215 ns, which is the read data transmission rate divided by 8. The signal is in the write mode when the signal / W has a high potential, and the read mode when the signal / W has a low potential. In addition, the change point of the write address and write data of the write command signal ▲ ▼ overlaps with the write mode of the signal / W, and malfunction of the circuit is prevented.

The write command signal ▲ ▼ is the write period signal ▲ ▼ and the signal output from the write side system control circuit 8.
It is generated by the logic of / W and no matter what phase the read timing appears with respect to the write timing due to the signal / W and the write command signal ▲ ▼, both operations are always performed alternately. It never happens.

Further, the buffer memory 7 has a capacity for two frames (addresses "0" to "511"), and writing is ahead of reading by one frame. This is as schematically shown in FIG. However, if the write address and read address are operating randomly, such as when the power is turned on,
The initialization circuit 14 forcibly presets the write side system control circuit 8 including the address so that the read address has an offset of one frame. 1
The time required for frame signal processing is the same for both writing and reading. Therefore, once the initialization is performed, the offset in frame units is kept constant thereafter.

(Effects of the Invention) As described above, according to the present invention, the address switching means is controlled so as to write the data of the first data string so as not to collide with the data read in burst form from the buffer memory, and the buffer memory Since the read / write is controlled, even if the read address counter and the write address counter operate independently, the write and read do not conflict with each other.

Further, since the write address is made to precede the read address by the initialization means, the read is not performed before the write, and the input information is accurately time-axis compressed in a short processing time (1 frame). can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a schematic diagram showing time axis compression / multiplexing in one embodiment of the present invention. FIG. 3 is a circuit diagram of a write command signal generation circuit in one embodiment of the present invention. FIG. 4 is a timing chart for explaining the operation of one embodiment of the present invention. FIG. 5 is a timing chart for explaining the operation of the write command signal generating circuit in the embodiment of the present invention. FIG. 6 is a schematic diagram showing changes in the write address and read address of the buffer memory in the embodiment of the present invention. 1 ... Serial-parallel conversion circuit, 2 ... Frame synchronization pattern adding circuit, 3 and 5 ... Latch circuit, 4 ...
... 3-state buffer, 6 ... parallel-serial conversion circuit, 7 ... buffer memory, 8 ... write side system control circuit, 9 ... write address counter, 10 ...
Read side system control circuit, 11 ... Read address counter, 12 ... Line counter, 13 ... Address selection circuit, 14 ... Initialization circuit, 15 ... Write command signal generation circuit.

Claims (1)

[Claims] 1. A first data string having a transmission rate Fi is transmitted at a transmission rate.
When converting to the second data string of transmission rate Fo (Fo> Fi) that is arranged in bursts at a cycle that is not an integral multiple of Fi, and the data of the first data string is insufficient for the data of the second data string Output from a write address counter that periodically changes address data, a read address counter that changes address data in bursts, and a write address counter in a time axis compression operation circuit that inserts dummy data and performs time axis compression Address switching means for switching the address data and the output address data from the read address counter to specify the address of the buffer memory for storing the data of the first data string, and to avoid collision with the burst data read from the buffer memory. When the address switching means is switched to write the data of the first data string to In addition, the time axis compression operation circuit is provided with control means for controlling read / write of the buffer memory, and initialization means for initializing the write address so that the write address precedes the read address. .