JPH0714155B2 - PCM terminal equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an improvement of a PCM terminal device used for data transmission between exchanges, for example.

(Prior Art) In recent years, various communication systems have been developed with the diversification of information and an increase in the amount of transmitted information. Among them, FIG. 3 shows one of them as a system for performing telephone communication or facsimile communication. The ones shown are known. This system
An exchange 2 to which a plurality of terminal devices 1 are connected, and a plurality of exchanges 31 to 3 m to which a plurality of terminal devices 1 are connected respectively
And PCM terminal equipment 4,5 installed between
Connected via 1-5m, and PCM terminal equipment 4 and other
For data transmission with the PCM terminal equipments 51 to 5m, as shown in FIGS. 4 (a) and 4 (b), a plurality of channels (for example, 24 channels) are time-division multiplexed and a frame synchronization signal is added to the head thereof. 1 frame, and a plurality of such frames (for example, 12 frames) are time-division multiplexed to form 1 multiframe.

In this type of system, when data transmission is performed by using one PCM terminal station device 4 as a master station and the other PCM terminal station devices 51-5m as slave stations, each PCM terminal station device 51-51 becomes a slave station. Since 5 m does not have its own reference clock source, it reproduces the frame synchronization signal and the clock signal from the received data coming from the PCM terminal device 4 of the master station to create the transmitted data, and It is necessary to match the phase with the received data. Therefore, conventionally, for example, a buffer for transmission data is provided, and phase matching between transmission and reception is performed by this buffer. FIG. 5 shows an example of the configuration. The transmission channel data TC is multiplexed with the transmission frame synchronization pulse generated from the frame synchronization pulse generation circuit 62 in the multiplexing circuit 61 and then RA as a buffer.
Supplied to the M63. The transmission frame synchronization pulse is created based on the transmission multi-frame pulse TMS generated from the clock signal of the reception data RD sent from the master station. Now, the transmission data TD supplied to the RAM 63 is
The transmission multi-frame pulse TMS and the clock signal CLK regenerated from the reception data TD by the reception clock regeneration circuit 68.
It is written in the RAM 63 by the write address generated from the write address counter 64 based on On the other hand, the transmission data written in the RAM 63 is received by the reception synchronization circuit 67.
The RAM 63 is read by the read address generated by the read address counter 65 based on the received multi-frame pulse RMS extracted from the above and the clock signal CLK reproduced by the received clock reproducing circuit 68. The write and read addresses are alternately selected by the multiplexer 66, for example, in the 1/2 bit cycle of the transmission data TD and R
Supplied to AM63. Then, from RAM 63, receive data R
The transmission data TD whose phase matches that of D is output, whereby the transmission / reception data between the master station and the slave station are phase-matched.

However, since such a conventional terminal device performs phase matching of the transmission data TD with the reception data RD using a buffer, the RAM 63 having a capacity capable of storing at least one multiframe transmission data as a buffer.
And a circuit for generating a write address and a read address for the RAM 63 and a circuit for designating the supply timing of the write address and the read address generated from these circuits are required, which complicates the circuit configuration of the device. There was a drawback that caused a large size. In addition, depending on the transmission speed of the transmission data, the writing and reading operations of the RAM 63 cannot follow the data speed, which may not be applicable.

(Problems to be Solved by the Invention) As described above, in the conventional PCM terminal station device, since the phase matching between the transmitted and received data is performed by the buffer, the configuration of the device becomes complicated and large, and The present invention has a problem that it is not suitable for high-speed data transmission, and the present invention pays attention to this point, simplifies and downsizes the circuit configuration, and can sufficiently adapt to high-speed data transmission. Is to provide.

[Structure of the Invention] (Means for Solving Problems) The present invention introduces frame synchronization signal extraction that introduces transmission data of another PCM terminal station device that operates as a master station and extracts a frame synchronization signal of this transmission data. A circuit, a clock reproduction circuit for reproducing a clock signal from the transmission data of the other PCM terminal device, and a transmission frame synchronization signal generation circuit,
This transmission frame synchronization signal generation circuit resets the count value every time the frame synchronization signal obtained by the frame synchronization signal extraction circuit is input, counts the clock signal from the clock regeneration circuit, and the count value is A transmission frame synchronization signal is generated at the time when the value reaches one transmission frame length, and this transmission frame synchronization signal is time-division multiplexed with transmission channel data by a multiplexing circuit and transmitted.

(Operation) As a result, since the transmission frame synchronization signal is created from the frame synchronization signal of the reception data, the transmission data obtained by multiplexing the transmission frame synchronization signal with the transmission channel data has the same phase as the reception data. Therefore, the transmission data buffer is not required. Therefore, a circuit for a buffer such as a large-capacity buffer memory, a writing / reading address generating circuit, a timing generating circuit, etc. is not required at all, and the circuit configuration of the device can be simplified and downsized accordingly. Further, since transmission data is neither written to nor read from the buffer memory, it is possible to sufficiently cope with high-speed data transmission.

(Embodiment) FIG. 1 shows a configuration of a phase matching circuit of a PCM terminal station device in an embodiment of the present invention. In the figure, the same parts as those in FIG.

The reception data RD sent from the master station is introduced to the reception synchronization circuit 67 and the reception clock recovery circuit 68, and these circuits 67, 6
At 8, the received multi-frame pulse RMS and the clock signal CLK are extracted and reproduced, respectively. Then, the reception multi-frame pulse RMS and the clock signal CLK are respectively supplied to the transmission multi-frame counter 69.
The transmission multi-frame counter 69 resets the count value and starts counting the clock signal CLK each time the reception multi-frame pulse RMS is supplied, and the count value becomes a value corresponding to one transmission multi-frame length. At that time, a pulse signal is generated, and this pulse signal is supplied to the frame synchronization pulse generation circuit 62 as a transmission multi-frame pulse TMS. The frame synchronization pulse generation circuit 62 creates a frame synchronization pulse TFS by dividing the transmission multi-frame pulse TMS or the like. The multiplexing circuit 61 to which the frame synchronization pulse TFS is supplied multiplexes the transmission channel data TC and the frame synchronization pulse, and outputs the multiplexed output as transmission data TD.

With such a configuration, when the reception data RD arrives from the master station. Reception synchronization circuit 67 and reception clock recovery circuit
At 68, the received multi-frame pulse RMS and the clock signal CLK are extracted and reproduced from the received data RD, for example, as shown in FIG. Then, the transmission multi-frame counter 69 resets the count value every time the reception multi-frame pulse RMS is supplied and counts the clock signal CLK, and the count value becomes a value corresponding to one transmission multi-frame length. At that time, a pulse signal is generated. As a result, as shown in FIG. 2, a transmission multi-frame pulse TMS having the same phase as the reception multi-frame pulse RMS is obtained. When this transmission multi-frame pulse TMS is obtained, the frame synchronization pulse generation circuit 62 creates a frame synchronization pulse TFS as shown in FIG. 2 in synchronization with the transmission multi-frame pulse TMS, and multiplexes this frame synchronization pulse TFS. Supply to circuit 61. As a result, the multiplexing circuit 61 multiplexes the transmission channel data TC and the frame synchronization pulse TFS to generate transmission data TD.
This transmission data TD is obtained by multiplexing the transmission channel data TC with the frame synchronization pulse TMS having the same phase as the transmission multi-frame pulse RMS as described above.
It will be in phase with the received data RD.

In this way, according to this embodiment, the transmission frame synchronization pulse TFS is generated from the reception multi-frame pulse RMS of the reception data RD, and this frame synchronization pulse TFS is multiplexed with the transmission channel data TC, so that the transmission data TD is received. Data RD
This means that the phase of the transmission data TD can be matched with the phase of the reception data RD. Also, the circuit used for phase matching is only the circuit that generates the transmission frame synchronization signal TFS from the received data, and the configuration is more than that of the conventional circuit that requires the RAM 63, its write / read circuit, timing circuit, etc. It can be greatly simplified and miniaturized. Furthermore, since writing or reading of transmission data is not required, even high-speed data can be handled sufficiently, and the applicable range can be expanded.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the phase adjustment is performed by the device of the slave station in the system for transmitting data between the master station and the slave station has been described, but a plurality of PCM terminal devices are installed in the master station. It may be applied when one of the devices serves as a substantial master station and another device performs transmission in a state where the phase matches the transmission data of the device of this master station. By doing so, each PCM terminal station device in the master station can transmit and receive data to and from the opposite slave station in a state of being synchronized with each other. Further, in the above embodiment, the case where the data transmission unit is a multi-frame has been described.
It may be applied to a system that transmits in frame units. In addition, the configuration of the transmission frame synchronization signal generation circuit and the like can be variously modified and implemented without departing from the scope of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, a frame synchronization signal extraction circuit for introducing transmission data of another PCM terminal device operating as a master station and extracting a frame synchronization signal of this transmission data is provided. , A clock reproduction circuit for reproducing a clock signal from the transmission data of the other PCM terminal device, and a transmission frame synchronization signal generation circuit, which is obtained by the transmission frame synchronization signal generation circuit in the frame synchronization signal extraction circuit. Each time a frame synchronization signal is input, the count value is reset and the clock signal from the clock recovery circuit is counted. When the count value reaches a value corresponding to one transmission frame length, the transmission frame synchronization signal is By generating this transmission frame synchronization signal and transmitting it by time division multiplexing with transmission channel data in a multiplexing circuit, the circuit configuration is simple. It is possible to provide a PCM terminal station device that can be miniaturized and miniaturized and can be sufficiently adapted to high-speed data transmission.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a phase matching circuit portion of a PCM terminal station apparatus according to an embodiment of the present invention, FIG. 2 is a timing diagram used for explaining the operation of the apparatus, and FIG. 3 is a PCM terminal station apparatus. Is a schematic configuration diagram showing an example of a communication system using
FIG. 4 is a schematic diagram showing a frame structure of data used in the system, and FIG. 5 is a block diagram showing a structure of a phase matching circuit portion of a conventional PCM terminal station device. 1 ... Terminal device, 2,31-3m ... Switch, 4 ... Main station side
PCM terminal equipment, 51 to 5m ...... PCM terminal equipment on the slave station side, 61 ......
Multiplexing circuit, 62 ... Frame sync pulse generating circuit, 67 ...
… Reception synchronization circuit, 68 …… Reception clock recovery circuit, 69 ……
Transmission multi-frame counter, RD ... Reception data, RMS
...... Reception multi-frame pulse, TC …… Transmission channel data, TD …… Transmission data, TMS …… Transmission multi-frame pulse, TFS …… Transmission frame synchronization pulse, CLK …… Clock signal.

Claims (1)

[Claims] 1. A PCM that transmits time division multiplexed data in synchronization with transmission data of another PCM terminal device that operates as a master station.
In the terminal device, a frame synchronization signal extraction circuit that introduces the transmission data of the other PCM terminal device and extracts the frame synchronization signal of this transmission data, and reproduces a clock signal from the transmission data of the other PCM terminal device. The clock regenerating circuit and the frame synchronizing signal obtained by the frame synchronizing signal extracting circuit are reset each time the count value is reset to count the clock signals from the clock regenerating circuit, and the counted value is one transmission frame length. And a transmission frame synchronization signal generation circuit that generates a transmission frame synchronization signal when the value of the transmission frame synchronization signal reaches a value corresponding to And a digitalization circuit.
PCM terminal equipment.