JPS61177834A - Multiplexed signal transmitting system - Google Patents

Abstract

PURPOSE:To prevent missing of data even in case of a low speed line with high traffic by reading signals from a storing circuit provided in each low speed line utilizing idle time of the low speed circuit, and multiplexing and transmitting to a high speed line. CONSTITUTION:Serial signals 11-1N of a small-scale low speed line are inputted respectively to signal processing blocks 61-6N. A serial signal 40 shaped in waveform 70 of the signal 11, is inputted to a timing extracting circuit 71, synchronism detecting circuit 72 and a storage device 76. The circuit 71 outputs synchronizing signal detecting timing conformable to the bit rate of the signal 40 and a clock signal 42 for address counter. The circuit 72 detects a synchronizing signal SYC 48 in the signal 40 and starts 40 and starts an address counter 73, and supplies an address signal 45 to the device 76. When the signal 40 is written in the device 76 totally, an FF opens a gate 74, and operates address counters 77, 78. When a time period in which SYC 48 comes reaches, data from the device 76 are read out, and signals 11-1N are time division multiplexed by a multiplexer 79, and transmitted from a high speed circuit 31 through a transmitting circuit 80.

Description

[Detailed Description of the Invention] [Utilization of the Invention] The present invention relates to a multiplex signal transmission method, and is particularly suitable for collecting small-scale lines that are cyclically transmitting and further performing multiplex transmission. This invention relates to a multiplexed signal transmission system.

[Background of the invention]

As shown in Figure 1 of Japanese Patent Application Laid-Open No. 59-133754, a transmission buffer for temporarily storing VC and low-speed line signals inputs low-speed line signals one by one. It had become.

This is because the low-speed line is assumed to have low traffic such as a conversation terminal, and in the case of serial signals that are sent cyclically, the low-speed line signal is stored in the transmission buffer. If a large number of low-speed line signals are input simultaneously, the processing may not be able to keep up and there is a possibility that some signals may not be stored in the transmission buffer.

[Purpose of the invention]

It is an object of the present invention to further multiplex a plurality of cyclic low-speed circuits without dropping data on the low-speed circuit even when the traffic of the low-speed circuit is high, and to simultaneously transmit data in frame units on the low-speed circuit. Like preserving your sexuality.
The object of the present invention is to provide a multiplexed signal transmission system.

[Summary of the invention]

The present invention provides a transmitting device (1. Equipped with a receiving circuit and a storage device for each cyclic low-speed line signal to be multiplexed, and reads data from the storage device using idle time of the signal on the low-speed line side. , sequentially selected by a multiplexer circuit, multiplexed and transmitted on a high-speed line by a transmitting circuit, and sent to a receiving device through the multiplexed signal from the high-speed line. Assigned by Kusa circuit,
Data is stored for each individual signal in a storage device, and then reproduced into a low-speed serial signal by a transmitting circuit.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram of a multiplex transmitter according to the present invention. 11.12, for serial signals of small-scale low-speed lines.
13. ...Input to this device as N lines of IN. The internal operation is the same for each line, so
The block 61 that processes signals on the line 11 will be explained. The serial signal on line 11 is input to waveform shaping circuit 70 and waveform shaped. Waveform shaped serial signal 40, timing extraction circuit 71, synchronization signal detection circuit 7
2, input to the storage device 76; Timing extraction circuit 7
1Lri, extract the t timing that matches the bit rate of the input serial signal 40, and extract the synchronous 0-period signal detection timing 4.
1. Output the address counter clock signal 42.

The timing extraction circuit referred to here is U P L O (P
This is a well-known method using the following methods. The synchronization signal detection circuit 72 detects the synchronization signal 8YC in FIG. A signal 42 is generated. The output signal 4i of the address color/receiver 73 is sent to the memory device 76 through the gate 74.
It is added as signal 45. This address signal inputs the data part of the serial signal 40 in order
Write in 6. In other words, @2 diagram, line 11
The data part 1) opens the gate 74 to the rough flip-flop 75 that inputs tz into the storage device.
The gate 81 is shut off and the address signal 44 is sent to the storage device 7.
6 has all the effects applied.

When all the data in the serial signal is written to the storage device, the write end signal 43 is output from the address counter 73, which inverts the flip-flop 75 and writes the data to the storage device 7.
6 address signal 45 is supplied through gate 81. After this, the next synchronization signal S is sent at #111.
When the time period for YC arrives, another address counter 77
．． 78 is activated, the stored serial data is read from the storage device 76, and the selection circuit 79 outputs the data on the line 11 as the signal 31. This signal is a line 3 that newly multiplexes the step speed of the address counter 77.
Since the transmission speed is set to match the transmission speed of No. 2, it is possible to transmit data faster than in the case of a low-speed, long-distance line like line 11. Here, 80i is a transmitting circuit.

Other lines 12, 13.・Old ・The same operation is performed for the IN, and the input line signal can be temporally compressed and a fixed signal can be multiplexed in a time-division manner and sent out at time @32.

FIG. 2 is a diagram summarizing the above operations in a time chart. To explain the operation of the line 11, after storing the data portion D1m in the storage device, at time t4,
During the time period when the next synchronization signal sYC is being received, the data of n, DH is temporally compressed and output to the multiplexed line. Since other lines operate in the same way, lines 11, 12, 13, . ...
...IN is time-division multiplexed and output.

Conditions to be noted here include multiplexed serial signals, lines 11, 12 . It is necessary that the length T occupied by one frame of IN signal is T>N-TM compared to the length Tv occupied by 7'c and s when multiplexed at high speed.

Next, FIG. 3 shows an embodiment of a multiplex receiver for demodulating multiplexed signals. The multiplexed serial signal 33 is waveform-shaped by a waveform shaping circuit 70 to generate a serial signal 34.

The timing extraction circuit 71 and the synchronization detection circuit 7
2, the address counter 73 is incremented, and a serial signal is written in the memory device 103 by the same operation as in the embodiment shown in FIG. At this time, due to the action of the demultiplexer 90, the multiplexed serial data of each line is transferred to the data of the line 11, to the block 111,
The data on line 12 is stored separately in block 112, and so on.

The data frame stored in the storage device is read out from the storage device according to the transmission speed of each line, and transmitted through the transmission circuit 104 to the lines 141, 142 . . . . is restored and output as 14N. Here, as in Figure 1, too, to
i is a gate, 102 is an address counter, and 37 is an address signal.

〔Effect of the invention〕

According to the present invention, since a receiving circuit and a storage device are separately provided for each of the low-speed lines input to the multiplex transmitter, even in cases such as cyclic transmission where the traffic on the low-speed line is high, high-speed transmission is possible. This has the effect of preventing data loss during multiplexing. Furthermore, since each frame of a serial signal on a low-speed line is stored in a storage device and multiplexed at high speed as a series of data, the same characteristics of data in units of frames can be ensured. Furthermore, even if the cyclic serial data on the low-speed line has different transmission speeds, since the storage devices are provided individually, there is also the advantage that it can be multiplexed onto the high-speed line.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a multiplex transmitter according to the present invention, FIG. 2 is a time chart of an embodiment of the present invention, and FIG. 3 is an embodiment of a multiplex receiver according to the present invention. The structure of
It's a success.

Claims (1)

[Claims] 1. A transmitting device that inputs low-speed serial signals that are transmitted cyclically, multiplexes them onto a high-speed line, and transmits them, and a transmitter that receives the multiplexed and transmitted signals from the high-speed lines and transmits the low-speed serial signals. In the multiplex signal transmission device, the transmitting device includes a plurality of receiving circuits for individually receiving the low-speed serial signals, and a plurality of storage devices for storing the serial signals from the receiving circuits. ,
The receiving device includes a multiplexer circuit that sequentially selects the signals read from the storage device, and a transmitting circuit that multiplexes and transmits the signals on a high-speed line, and the receiving device receives the signals that are multiplexed and transmitted from the high-speed line. , a demultiplexer circuit that allocates signals from the receiving circuit to individual serial signals, a plurality of storage devices that store data for each individual serial signal, and a plurality of transmission circuits that generate low-speed serial signals from the storage devices. A multiplexed signal transmission system characterized by comprising: