JPH06342343A - Control system for multiple input/output file device - Google Patents

Abstract

PURPOSE:To provide the control system for multiple input/output file devices which can record and reproduced data in and from a buffer memory without using any register file. CONSTITUTION:An actual address(Physical Address) which is generated by preceding a half slot than actual case from a temporary address signal(Count Value) is generated. A memory cycle (Music Cycle) is generated from both a direction signal(Pray/Record) indicating the transmission direction of data and a master clock signal(SdClk). Then when AV information is outputted from a buffer memory, the front half of the memory cycle(Music Cycle) is assigned to access from an input/output interface circuit side and when the AV information is inputted to the buffer memory, the latter half of the last memory cycle(Music Cycle) is assigned to access to the input/output interface circuit side, thus inputting and outputting the AV information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system of a multi-input / output file device for inputting / outputting a digital audio signal or a digital video signal to / from an audio device or a video device having a plurality of parallel input / output channels. It is a thing.

[0002]

2. Description of the Related Art
No. 4 discloses a multi-channel information recording / reproducing device as an example of the multi-input / output file device. This multi-channel information recording / reproducing apparatus stores a large amount of audio / video information in a high-speed and large-capacity storage device such as a hard disk drive (HDD) and inputs / outputs in a time-division multiplex manner, thereby making it possible to store a plurality of information. It is designed so that the user can deal with any information simultaneously accessed. The inventor of the present invention has applied for an efficient transmission method of time division multiplex output in this multi-channel information recording / reproducing apparatus, filed on the same date as the present patent application, serial number 40500.
No. 0477 "Digital Signal Transmission System".

An example of a multi-channel information recording / reproducing apparatus using this digital signal transmission system is shown in FIG. 4 and briefly described below. In the multi-channel information recording / reproducing apparatus shown in the figure, a mass storage device (HDD) 1 in which AV information (audio / video information) is stored is a SCSI interface 2 and a (audio / video) data bus 3
It is connected to the buffer memory 6 which is a random access memory (RAM) via a. The buffer memory 6 temporarily stores the AV information for inputting / outputting the AV information corresponding to a large number of channels, and the AV information is exchanged with the mass storage device 1 through the SCSI interface 2 and the data bus 3a. Information is transmitted and received. Further, the address generation means (counter) 5a generates a temporary address signal 10a and outputs it to the address conversion means (dual ported RAM) 8a, and the address conversion means 8a outputs the temporary address signal 10a to the real address signal 11a. To output the data, and directly access the buffer memory 6. The address conversion means 8a is connected to a control means (CPU) 9 for appropriately rewriting the contents (data of the address conversion table).

On the other hand, from the buffer memory 6 to the external device A
In order to read the V information, the address generating means 5b generates a temporary address signal 10b and outputs it to the address converting means 8b, and the address converting means 8b outputs the real address signal 11b.
b to output to the address bus 3b, and from the buffer memory 6 via the data bus 3a and the input / output interface circuit (transceiver) 7 to the AV for each channel.
When the information is multiplexed and output to the music bus 4, the address is matched with the read timing.

In such a multi-channel information recording / reproducing apparatus, the clock of the signal output from the address generating means 5b is synchronized with the clock of the music bus 4 (transfer clock of the input / output interface circuit 7),
The AV information output from the buffer memory 6 is output to the music bus 4 as it is. In addition, as to which time slot number the AV information is actually transmitted and received, the actual address signal 11b output from the address conversion means 8b is disclosed in Japanese Patent Laid-Open No. 2222024/1990.
At the same time, it can be realized by outputting control information.

Here, as a specific example of the signal transmitted by the music bus 4, FIG. 5 shows an example in which an AV information signal of 128 channels is placed on a transmission line for performing 8-bit parallel transmission. The music bus 4 includes an 8-bit data bus (Data) for transmitting the AV information signal itself,
A master clock signal (SdClk) that controls the transfer timing and a synchronization signal (FSync) are transmitted.

In this example, the master clock signal (SdCl
One data can be loaded in one cycle of k). When the unit of this cycle is called a time slot, there are 128 time slots with numbers 0 to 127, which correspond to a maximum of 128 input / output channels with numbers 0 to 127, respectively. You can The synchronization signal (FSync) is inserted during the time slot number 127, and the synchronization signal (FSyn)
It shows that the time slot number of the master clock signal (SdClk) following c) is 0.

Therefore, a specific time slot number is determined in advance for each terminal device connected to the music bus 4, and an AV information signal is placed at that time slot number, so that only the data itself can be obtained. It is possible to determine which terminal device has the AV information signal.

Next, FIG. 2 is a chart showing the access timing to the buffer memory 6 during reproduction of this multi-channel information recording / reproducing apparatus. The address conversion means 8b outputs the real address signal 11b and, as control information, an access signal (Music-bus Enable) indicating that the buffer memory 6 is being accessed from the input / output interface circuit 7 side and the buffer memory 6 A direction signal (Play / Record) indicating whether input or output is performed (data transmission direction) is output. And the access from the mass storage device 1 side is
The access signal output from the address conversion means 8b is detected and controlled so as to be performed when the input / output interface circuit 7 side is not accessing.

In the figure, the temporary address signal (Count Valu) 10 output from the address generating means 5b is shown.
b is output to the address conversion means 8b at the same timing as the transfer clock of the input / output interface circuit 7, and the real address signal (DP-RAM Out) 11b is output from here. The access signal (Music-bus Enable) indicates that the input / output interface circuit 7 is accessing when it is at H level, and the direction signal (Play / Record) is at H level.
It indicates that the data transmission direction is reversed when the level is reached. Therefore, when the access signal is at the H level and the direction signal indicates the output from the buffer memory 6, the data (Buffer RAM Data) in the buffer memory 6 is read and output to the music bus 4.

In the figure, the shaded area in each signal is
The access time for each data input / output is shown, and that time is the delay time. Further, in this example, for the sake of simplification of description, the case where the access cycle to the buffer memory 6 is equal to the transfer clock of the input / output interface circuit 7 is shown. However, the access cycle is twice the transfer clock. In some cases, a method generally called a hidden access may be adopted in which the first half and the second half are allocated to the access from the input / output interface circuit 7 side and the access from the mass storage device 1 side, respectively.

[0012]

In the above-mentioned multi-channel information recording / reproducing apparatus, the address generating means 5b is
Time-division multiplexed I / O from the music bus 4
In the case of a counter that operates in synchronization with the V information transmission clock, the count value is more than the timing at which the AV information should be input / output, in consideration of the delay due to the circuit element and the delay due to the access time of the buffer memory 6. Must be changed prior to. However, if the count value of the address generation means 5b is changed in advance, the access to the buffer memory 6 also comes before the timing at which the AV information should be input / output, so that when the AV information is recorded in the buffer memory 6. If the reproduction is performed at the same timing as the reproduction, the AV information to be recorded is decided after the buffer memory 6 is accessed, and recording is practically impossible.

As one of the methods for solving this, paying attention to the point that AV information input / output by time division multiplexing is input / output AV information of the same channel for each frame, for example, in the i-th slot. It is possible to adopt a means of latching the input data in the register file for one frame and inputting the latch output to the buffer memory 6.

This will be described with reference to FIG. 3. Of the AV information time-division multiplexed from the music bus 4, the data input in the i-th slot is transferred to the register file for one frame (Delayed). Recording Da
ta), the access signal is at the H level, and the direction signal indicates the input to the buffer memory 6,
The data of the register file is recorded in the buffer memory 6 as data (Buffer RAM Data).

In this case, in terms of timing, there is almost no difference in the way of accessing the buffer memory 6 for both recording and reproduction, and it can be easily realized. However, when it is intended to correspond to many input channels, many cases are required. However, there is a problem that the circuit file becomes large because the register file of is required. Therefore, an object of the present invention is to provide a control system for a multi-input / output file device capable of recording / reproducing to / from a buffer memory without using a register file.

[0016]

As means for achieving the above object, a mass storage device for storing a large number of information and a temporary storage of the information for inputting / outputting the information corresponding to a large number of channels. A control method for a multi-input / output file device, comprising: a buffer memory for storing the information; From the transfer clock and the input / output direction to the buffer memory, a memory cycle in which a plurality of cycles are synchronized with one time slot of the transfer clock is generated, and an output from the buffer memory is output from the time slot. The input to the buffer memory is allocated to the memory cycle corresponding to the front, and the input to the buffer memory is the previous time slot. Assigned to the memory cycle corresponding to the rear, it is intended to provide a control method of a multi-input and output files and wherein from said output interface to input and output to the buffer memory.

[0017]

The memory cycle when accessing the buffer memory 6 is set to the transfer clock (Sd of the input / output interface circuit 7
Clk) twice, and the access cycles to the two buffer memories 6 generated during one transfer clock are assigned to the access from the input / output interface circuit 7 side and the access from the mass storage device 1 side, respectively. .
At this time, which of the access from the input / output interface circuit 7 side and the access from the mass storage device 1 side is processed first depending on whether the access from the input / output interface circuit 7 is an input operation or an output operation. Or switch.

Specifically, the input / output interface circuit 7
When reproducing AV information when accessing from the side, the buffer memory 6 is used by utilizing the first half memory cycle.
When the output from is determined, the AV information is placed in the time slot of the input / output interface circuit 7. Further, when recording in the buffer memory 6, the AV information on the side of the input / output interface circuit 7 is fetched and then recorded in the buffer memory 6 using the latter half memory cycle of the immediately preceding time slot. Then, the access from the mass storage device 1 side is performed using a memory cycle other than the above.

This eliminates the need to temporarily store the AV information in the buffer memory 6 in the register file when recording the AV information, and the register file becomes unnecessary even when many input / output channels are supported. The circuit scale of the circuit 7 can be reduced.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The control system for a multi-input / output file apparatus according to the present invention is designed to transmit a digital signal obtained by sampling the amplitude of an analog signal, which is continuous in time, such as an audio signal and a video signal, at a constant cycle, in order to transmit each signal. To the buffer memory 6 in the multi-input / output file device for transmitting and receiving the data of each terminal device at a constant interval for each sampling period when the data of each device is time-division multiplexed and transmitted / received by the music bus 4. Access control method.

As an embodiment of the control system of the multi-input / output file apparatus of the present invention, an example of use in the multi-channel information recording / reproducing apparatus shown in FIG. 4 and described in the section of the prior art is shown in the timing chart of FIG. Will be explained. Since the configuration of the multi-channel information recording / reproducing apparatus is almost the same as the conventional one, its explanation is omitted.

In the timing chart shown in FIG. 1, two memory cycles for accessing the buffer memory 6 are provided in one time slot of the master clock signal (SdClk) supplied together with the AV information. , Only signals related to access from the input / output interface circuit 7 side are shown. However, to access from the mass storage device 1 side, as described in the section of action, it may be performed when the memory cycle is at the H level indicating that the I / O interface circuit 7 side is not accessing. Therefore, the description is omitted here.

In FIG. 1, a music bus 4 (Musi
From the c-bus), a master clock signal (SdClk) for controlling the transfer timing and a synchronizing signal (FSync) are transmitted together with the AV information signal. The master clock signal (SdClk) can carry one data in this one cycle, and the unit of this cycle is called a time slot. In addition, the synchronization signal (FSync
) Indicates that the time slot number of the master clock signal (SdClk) next to this synchronizing signal (FSync) is 0, which is inserted during the period of the specific time slot number.

Then, the temporary address signal (Count Valu) 10b output from the address generating means 5b is output to the address converting means 8b at the same timing as the master clock signal (SdClk), from which the real address signal (DP
-RAM Out) 11b is output. At this time, in the address conversion means 8b, an access time for address conversion (hatched portion in the figure) occurs, so that the temporary address signal 10
b indicates a value that sufficiently precedes the time slot number when inputting / outputting AV information, and the generated real address (Physical Address) indicates a value that precedes the actual time slot by half a slot. As shown.

The access to the buffer memory 6 is performed at a timing half slot ahead as in the generated real address. Then, the direction signal (Play / Record) indicating whether the buffer memory 6 is inputting or outputting (data transmission direction) and the input / output interface circuit 7 uses the slot for input / output. A memory cycle (Music Cycle) indicating that the buffer memory 6 is being accessed from the input / output interface circuit 7 side is generated on the basis of whether or not. In the memory cycle shown in the figure, when it is at the L level, it indicates that access is in progress.

Here, when the AV information is output (reproduced) from the buffer memory 6, it is preceded by two half time slots.
The first half of one memory cycle is assigned to the access from the input / output interface circuit 7 side, and
In the case of inputting (recording) V information, the latter half of the memory cycle immediately before, of the two memory cycles, is assigned to access to the input / output interface circuit 7 side.

In this way, when the AV information is output from the buffer memory 6, the generated real address (Ph
The buffer memory 6 is accessed by the (ysical Address) (Buffer RAM Read) and the memory cycle (Mu
sic Cycle) becomes L level, and buffer memory 6
(RAM Read Latch) to Music Bus 4 (Music-bu
The AV information is output to (s).

When the AV information is input to the buffer memory 6, the generated real address (Physical Address) is used.
s) when the memory cycle (Music Cycle) at the start of generation is at the L level, the AV is transferred from the music bus 4 (Music-bus) to the buffer memory 6 after a half time slot.
Information is entered.

As described above, according to the control method of the multi-input / output file device of the present invention, the memory cycle (Music Cycle) assigned to the access from the input / output interface circuit 7 side.
Is generated, and recording / reproducing is performed on the buffer memory 6 with this memory cycle as a reference.

Then, this memory cycle (Music Cycl
e) can be expressed by an exclusive OR of the direction signal (Play / Record) and the master clock signal SdClk, and can be easily generated.

[0031]

According to the control method of the multi-input / output file device of the present invention, the output from the buffer memory is allocated to the memory cycle corresponding to the front of the time slot, and the input to the buffer memory is allocated to the rear of the immediately preceding time slot. Since it is assigned to the memory cycle corresponding to, and I / O is performed from the I / O interface to the buffer memory,
When inputting information to the buffer memory, it is not necessary to hold the data with frame rounding delay, and the reference memory cycle at the time of input / output can also be derived from a simple logical expression, so that information with good timing can be obtained. The effect is that input / output is possible.

[Brief description of drawings]

FIG. 1 is a timing chart showing an embodiment of a control system of a multi-input / output file device of the present invention.

FIG. 2 is a timing chart showing a conventional example.

FIG. 3 is a timing chart showing a conventional example.

FIG. 4 is a configuration diagram showing an example of a multi-channel information recording / reproducing apparatus.

FIG. 5 is a timing chart showing an example of a digital signal transmission system.

[Explanation of symbols]

1 mass storage device (HDD) 2 SCSI interface 3a data bus 3b address bus 4 music bus 5a, 5b address generation means (counter) 6 buffer memory 7 input / output interface circuit (transceiver) 8a, 8b address conversion means (dual ported)・ Ram) 9 Control means (CPU)

Claims (1)

[Claims] 1. A mass storage device for storing a large number of information,
A buffer memory for temporarily storing the information for inputting / outputting the information corresponding to a large number of channels, and an input / output interface for time-division multiplexing the information of a large number of channels for input / output with an external device A method of controlling a multi-input / output file device having: a plurality of cycles for synchronizing one time slot of the transfer clock from a transfer clock in the input / output interface and an input / output direction to / from the buffer memory. Generated memory cycles, assigning the output from the buffer memory to the memory cycle corresponding to the front of the time slot, and inputting the buffer memory to the rear of the previous time slot. Allocate for recycling and input to the buffer memory from the I / O interface. Control method of the multi-input and output files and wherein the performing forces.