JPH10149625A - Data recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform high speed data recording and reproducing. SOLUTION: An input recording data at high speed is separated into plural low speed separated data by a data separating means 1. The separated data outputted from the data separating means 1 are recorded as recording data by data storage means 3a-3n respectively upon receipt of control of a control means 2. The recording data are outputted as reproducing separated data by the data storage means 3a-3n again upon receipt of control of the control means 2. The reproducing separated data outputted at low speed from the data storage means 3a-3n are temporarily held, and are synchronized and outputted by a synchronizing means 4. The reproducing separated data outputted from the synchronizing means 4 are multiplexed by a data multiplexing means 5 to produce and output a high speed reproducing data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data recording and reproducing apparatus, and more particularly to a data recording and reproducing apparatus for recording and reproducing data at a predetermined speed.

[0002]

2. Description of the Related Art Generally, when data is recorded or reproduced on a data recording / reproducing device such as a magnetic storage device,
The speed is constant depending on the design specifications of each data recording / reproducing device. Therefore, when it is necessary to record or reproduce data at a speed exceeding the design specification of the data recording / reproducing apparatus, it is necessary to increase the signal frequency of data or increase the number of channels.

[0003]

However, the performance of data transmission media and the like is rapidly improving at present, and it is difficult to incorporate a function for changing the signal frequency and the number of channels of data into a data recording / reproducing apparatus and its peripheral devices. There is a problem.

[0004] The present invention has been made in view of the above points, and a data recording and reproducing apparatus capable of recording and reproducing data at high speed without changing the signal frequency or the number of channels of data. The purpose is to provide.

[0005]

According to the present invention, in order to solve the above-mentioned problems, in a data recording / reproducing apparatus for recording and reproducing data at a predetermined speed, a recording data input at a high speed is separated and a low speed data is recorded. A data separating unit that creates separated data transmitted by a plurality of data storage units; a plurality of data storage units that record the separated data as recording data and output the recording data as reproduction separation data; A synchronization unit for temporarily holding the separation data for reproduction output at a high speed, and synchronizing and outputting the separation data for reproduction output from the synchronization unit; And a data multiplexing means for generating and outputting the data.

In the data recording / reproducing apparatus having such a configuration, the data separating means separates the recording data input at a high speed to create separated data transmitted at a low speed.
The plurality of data storage units record the separation data output from the data separation unit as recording data, and output the recording data as reproduction separation data. The synchronizing means temporarily holds the separation data for reproduction output at a low speed from the plurality of data storage means, and synchronizes and outputs the data. The data multiplexing unit multiplexes the separation data for reproduction output from the synchronization unit to create and output reproduction data output at a high speed.

Thus, high-speed recording data is separated,
High-speed data recording and reproduction by creating low-speed separation data and storing it in a plurality of storage means, and multiplexing the reproduction separation data output at a low speed from the plurality of storage means and outputting it as high-speed reproduction data. Becomes possible.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the principle configuration of the present invention.

The data recording / reproducing apparatus of the present invention comprises a data separating means 1, a control means 2, and n data storage means 3.
, 3n, a synchronizing unit 4, and a data multiplexing unit 5. Note that n is an arbitrary integer.

The data separating means 1 separates input data into n pieces and creates and outputs separated data 1, separated data 2,..., Separated data n. Here, the speed of all the separated data is 1 / n of the input data. The control means 2
The processing performed by the data recording / reproducing device is controlled. That is,
When performing “recording” upon input of data, a data recording instruction is input to the data recording instruction, and when performing “reproduction” of already recorded data, a data reproduction instruction is input to a plurality of data recording / reproducing devices simultaneously. .

[0011] The n data storage means 3a, 3b, ...
, 3n are all created with the same design specifications, and the data processing speed is the same. Here, it is assumed that these n data storage means 3a to 3n have a data processing capacity of x (bps). The output terminals of the data separation means 1 are connected to the input terminals of the data storage means 3a to 3n, and when a data recording command is output from the control means 2, the data storage means 3a stores the separated data 1 and the data storage means 3b stores .., The data storage means 3n stores the separated data n as recording data. When a data reproduction command is output from the control unit 2, the data storage units 3a to 3n use the recording data as reproduction separation data 1, reproduction separation data 2,..., Reproduction separation data n. Output to the output terminal.

The input terminal of the synchronization means 4 is the data storage means 3
a to 3n are connected to the output terminals. Synchronization means 4
The separation data for reproduction output from the data storage means 3a to 3n is temporarily held at an arbitrary timing, and the data is output in a synchronized manner. The output terminal is connected to the input terminal of the data multiplexing means 5. I have. Data multiplexing means 5
Is x (bps) separation data 1 for reproduction input in synchronization with
The reproduction separation data 2,..., And the reproduction separation data n are multiplexed to create and output nx (bps) reproduction data.

As described above, in the data recording / reproducing apparatus of the present invention, when data is recorded, input data is separated and stored in a plurality of data storage means, and when data is reproduced, data is read from a plurality of data storage means. The output separation data for reproduction is multiplexed and output.

Thus, when exchanging data with the outside,
It is possible to increase the transmission speed without increasing the signal frequency of data to the individual data storage means or increasing the number of channels.

Next, a first embodiment of the data recording / reproducing apparatus of the present invention will be described.
An embodiment will be described. FIG. 2 is a block diagram showing a configuration of the first embodiment of the data recording / reproducing apparatus of the present invention. The correspondence between the configuration shown in FIG. 1 and the configuration shown in FIG. 2 will be described after the description of FIG.

The data recording / reproducing apparatus 10 includes a demultiplexer 11, a controller 12,
The data storage devices 13a and 13b and a FIFO (First-In
First-Out) memory unit 14 and a multiplexer (Multip
lexer) 15.

Here, the data recording / reproducing apparatus 10 has 2x (b
ps), an input terminal for receiving an enable (ENABLE) signal, and an input terminal for receiving an external clock signal (external CLOCK signal). In addition, an output terminal for outputting 2x (bps) output data, an output terminal for outputting an output VALID signal, and an output CL
An output terminal for outputting an OCK signal is provided, and the data recording / reproducing apparatus 10 exchanges data with the outside via these input / output terminals. The data recording / reproducing apparatus 10 is also provided with a command input terminal for receiving an external command for instructing whether to record or reproduce data.

The demultiplexer 11 receives 2 × (bps) input data in synchronization with the external CLOCK signal only while the ENABLE signal is true. Then, the received input data is separated into the number of data storage devices provided in the data recording / reproducing device. Data recording / reproducing apparatus 10 shown in FIG.
Is provided with two data storage devices, the demultiplexer 11 converts the input data into the separated data 1 of x (bps).
The data is separated into two of x (bps) separated data 2 and output. In the demultiplexer 11, similarly to the input data, the external CL is used.
The OCK signal is also divided by the number of data storage devices to generate a divided clock signal. In the data recording / reproducing apparatus 10 shown in the figure, the frequency-divided CLOCK signal has a cycle twice that of the external CLOCK signal. The internal configuration of the demultiplexer 11 will be described later.

The controller 12 receives an external command and simultaneously inputs the external command to the data storage devices 13a and 13b as an internal command. That is, a data recording command is output as an internal command when the external command requests data recording, and a data reproduction command is output as the internal command when data reproduction is requested. However, the data recording command among these internal commands must be input to the data storage devices 13a and 13b before the recording data and the ENABLE signal are input to the data recording / reproducing device 10. Note that the external command received by the controller 12 may be the same as that conventionally output to request data recording and reproduction from the data storage device.

The data storage device 13a receives x (bps) separated data 1, a frequency-divided CLOCK signal, and an internal command. If the input internal command is a data recording command, the data storage device 13a records the separated data 1 as recording data 1 in synchronization with the frequency-divided CLOCK signal. Also,
If the internal command is a data reproduction command, in synchronization with the internal first CLOCK signal having the same cycle as the frequency-divided CLOCK signal,
The recording data 1 is output as separation data 1 for reproduction together with a first VALID signal. The structure of the data storage device 13a will be described later in more detail. The structure of the data storage device 13b is substantially the same as the structure of the data storage device 13a, but the input is not the separation data 1 but the separation data 2. In this case, the output is not the separated data for reproduction 1 synchronized with the internal first CLOCK signal, but the separated data for reproduction 2 synchronized with the internal second CLOCK signal. Also, not the first VALID signal, but the second VALID signal
A signal is attached.

The FIFO memory unit 14 receives all outputs from a data storage device provided in the data recording / reproducing device. Therefore, here, the reproduction separated data 1 output from the data storage device 13a, the first VALID signal, and the internal first CLOCK signal are stored in the data storage device 1a.
3b for reproduction and the second VALID
The signal and the internal second CLOCK signal are input. FIF
The O memory unit 14 holds the separated data for reproduction 1 based on the internal first CLOCK signal and the first VALID signal,
The separation data for reproduction 2 is held based on the CLOCK signal and the second VALID signal. Further, the FIFO memory unit 14 synthesizes a third VALID signal from the first VALID signal and the second VALID signal. The FIFO memory unit 14 further includes, in synchronization with the frequency-divided CLOCK signal output from the demultiplexer 11, the separated data for reproduction 1 and the separated data for reproduction 2,
And a third VALID signal.

The multiplexer 15 stores the reproduction separation data 1 and the reproduction separation data 2 from the FIFO memory unit 14.
Are input in synchronization with the third VALID signal. Then, the multiplexer 15 multiplexes the separated data for reproduction 1 and the separated data for reproduction 2 to create 2 × (bps) output data. Further, an output VALID signal is created from the third VALID signal and the frequency-divided CLOCK signal. And external CLOCK
The output data is output with the output VALID signal in synchronization with the signal. The output CLOCK signal output at the same time is the same as the external CLOCK signal.

As described above, in the data recording / reproducing apparatus of the present invention, the processing speed of data transfer with the outside can be made nx by providing n data storage devices having the processing speed x inside. FIG. 2 shows an example in which two data storage devices are provided, but this number can be increased to an arbitrary number.

The demultiplexer 11 shown in FIG.
Corresponds to the data separating means 1 shown in FIG. Similarly, the controller 12 shown in FIG. 2 is used by the control means 2 shown in FIG. 1 to control the data storage devices 13a and 13a shown in FIG.
b is the data storage means 3a, 3b shown in FIG. 1, and the FIFO memory unit 14 shown in FIG.
The multiplexer 15 shown in FIG. 2 corresponds to the data multiplexing means 5.

Next, the demultiplexer 11 shown in FIG.
Will be described. FIG. 3 is a block diagram showing the internal configuration of the demultiplexer 11. The demultiplexer 11 constituting the data recording / reproducing apparatus according to the present invention includes a shift register 11a, a counter 11b, and a D-flip-flop (D-FF) 11c.
The demultiplexer 11 is provided with three input terminals, and receives nx (bps) input data, an ENABLE signal, and an external CLOCK signal from outside the data recording / reproducing apparatus 10. Hereinafter, the number of data storage devices is not particularly limited to two, and is described as n.

The shift register 11a has a data input terminal for receiving input data and an EN for receiving an ENABLE terminal.
It has an ABLE terminal and a CLOCK terminal for receiving an external CLOCK signal. Here, continuity of the external CLOCK signal is not required. If the ENABLE signal is "H", the shift register 11a validates the data input to the data input terminal in synchronization with the input external CLOCK signal. Then, the shift register 11a separates valid input data by n, creates n separated data of x (bps), and inputs the separated data to the D-FF 11c separately.

FIG. 4 shows the demultiplexer 1 shown in FIG.
6 is a timing chart illustrating switching between valid / invalid of input data in a shift register 11a of FIG. When the signal input at each input terminal is in the state shown in the figure, that is, "x" is synchronized with the continuous external CLOCK signal.
.. "are input to the data input terminal, and when the ENABLE signal is input from a time when the input data is" a ", the valid input data is" abcdef... ". is there. At this time, if n is 2, the shift register 11a outputs "ac
e ... "and" bdf ... ", and if n is 3, [ad ...]," be ... "and" cf ... "
And create

Returning to FIG. 3, the description of the demultiplexer 11 will be continued. The counter 11b has an ENABLE terminal for receiving an ENABLE signal and a CLOCK terminal for receiving an external CLOCK signal. Then, while the ENABLE signal is being input to the ENABLE terminal, the external clock signal is frequency-divided by dividing the external clock signal by n.
Create and output an OCK signal.

D-flip-flop (D-FF) 11c
Are supplied with the separated data 1 to n from the shift register 11a and the frequency-divided CLOCK signal from the counter 11b. The D-FF 11c holds the input separated data, and outputs all the held separated data in synchronization with the frequency-divided CLOCK signal. Thereby, the separation data 1 to the separation data n become x (bps). The separated data 1 to separated data n are output via separate output terminals.

Next, the data storage device 13a shown in FIG.
Will be described. FIG. 5A is a timing chart illustrating data storage of the data storage device, and FIG.
5 is a timing chart for explaining data reproduction of the data storage device.

The data storage device 13a is provided with a data input terminal for receiving the separated data 1 input from the demultiplexer 11, and a CLOCK terminal for receiving the frequency-divided CLOCK signal, and receives an internal command from the controller 12. . If the internal command is “data recording command”, the data storage device 13a inputs the divided CLOC
Treat the K signal as an input CLOCK signal. As shown in FIG. 5A, the separated data 1 "xace ..." is input to the data input terminal, and the frequency-divided CLOCK signal is input from the time when the separated data 1 is "a". Then, the data stored as the storage data is “ace...”.

The data storage device 13a is also provided with a data output terminal for outputting separated data for reproduction, a VALID terminal for outputting a first VALID signal, and an internal CLOCK terminal for outputting an internal first CLOCK signal. Controller 1
When the internal command input from step 2 is a "data reproduction command", the data storage device 13a creates an internal first clock signal having the same cycle as the cycle of the frequency-divided clock signal input when the stored data is stored. I do. Then, in synchronization with the created internal first CLOCK signal, the stored data is output as separation data 1 for reproduction together with the VALID signal. As shown in FIG. 5B, storage data "yace ..." is input to the data output terminal as separation data 1 for reproduction in synchronization with the internal first CLOCK signal.
When the D signal is input from the time when the stored data is “a”, the data that is effective as the separation data for reproduction 1 is “ace...”.

The operation of the data storage device 13b differs only in the contents of the input / output data.
Since the operation is the same as the operation a, the description is omitted. Next, the internal configuration of the FIFO memory unit 14 shown in FIG. 2 will be described.

FIG. 6 is a block diagram showing the internal configuration of the FIFO memory unit 14. The FIFO memory unit 14 constituting the data recording / reproducing apparatus of the present invention includes n FIFO memories 1
4a to 14n, a VALID signal detection circuit 14p, and a shift register 14q.

In the FIFO memory 14a, the reproduction separation data 1 output from the data storage device 13a and the first VA
An input terminal is provided for receiving the LID signal and the internal first CLOCK signal. When the first VALID signal is inputted, the FIFO memory 14a stores the inputted internal first CLOC.
Treat the K signal as a write CLOCK signal. In this case, the first VALID signal is treated as a write enable signal, and the reproduction separated data 1 is treated as write data, and is held in the FIFO memory 14a. The other (n-1) FIs
The FO memory also holds the separation data for reproduction.

The VALID signal detection circuit 14p includes n VALID signal input terminals for receiving the first to nth VALID signals input from the data storage devices 13a to 13n,
It has one intermediate VALID signal output terminal that outputs an intermediate VALID signal.

FIG. 7A is a timing chart for explaining the operation of the VALID signal detection circuit. The VALID signal detection circuit 14p calculates a logical product and a logical sum of the first to nth VALID signals. And the first VALID signal ~
Becomes true when the logical product of the n-th VALID signal becomes true,
A signal which becomes false when the logical sum of the first to nth VALID signals becomes false is defined as an intermediate VALID signal. This intermediate VALID signal is transmitted to the FIFO memory 14a.
... To 14n are created so as to be used as a read enable signal when reading the separated data for reproduction 1 to n stored as write data.

The VALID signal detection circuit 14p further includes
It is also possible to provide n EF input terminals for receiving the first empty flag (Empty Flag: EF) to the n-th empty flag (n-th EF) output from the FIFO memories 14a to 14n.

FIG. 7B shows a VALID signal detection circuit 14p
3 shows a timing chart for explaining the operation when an empty flag input terminal is provided. By taking the logical sum of the first EF to the n-th EF, the FI generated due to a loss in any of the data outputs of the data storage devices 13a to 13n is generated.
The empty state of the FO memories 14a to 14n can be identified. In this case, the intermediate VALID signal is the first E
The exclusive OR with the logical sum of F to the n-th EF.

Returning to FIG. 6, description of the FIFO memory unit 14 will be continued. The frequency-divided CLOCK signal output from the demultiplexer 11 and the intermediate VALID signal output from the VALID signal detection circuit 14p are input to the shift register 14q. The FIFO memories 14a to 14n require a certain "delay" between writing and reading. Therefore, the intermediate VALI created by the VALID signal detection circuit 14p
The D signal is delayed by the shift register 14q to be the (n + 1) th VALID signal. (N + 1) th created
The VALID signal is output in synchronization with the input frequency-divided CLOCK signal. The “delay” required here is the FI
It is determined by the specifications of the product used for the FO memories 14a to 14n.

When the FIFO memory holding the separated data for reproduction as described above receives the (n + 1) th VALID signal input from the shift register 14q, the FIFO memory reads this and treats it as an ENABLE signal. That is, the (n + 1) th VA
While the LID signal is true, the reproduction separation data held as write data is output in synchronization with the frequency-divided CLOCK signal input from the demultiplexer 11. In addition, FIF
The operations of the O memories 14a to 14n are all the same.

Next, the internal configuration of the multiplexer 15 shown in FIG. 2 will be described. FIG. 8 is a block diagram showing the internal configuration of the multiplexer 15. The multiplexer 15 constituting the data recording / reproducing apparatus of the present invention includes a load pulse generator (Load Pulse Generator) 15a.
And shift registers 15b and 15c.

The RPG 15a creates and outputs a load pulse from the frequency-divided CLOCK signal output from the demultiplexer 11. Reproduction separation data 1 to reproduction separation data n are input from the FIFO memory unit 14 to the shift register 15b in synchronization with each other. Shift register 15b
Converts the n pieces of x (bps) separation data for reproduction into RPG1
Multiplexing based on the load pulse input from 5a,
Create nx (bps) playback data. The shift register 15b receives an external clock signal from the outside, and the created nx (bps) reproduced data is stored in the external clock.
Output in synchronization with the signal.

The shift register 15c has an FIF
The (n + 1) th VALID signal output from the O memory unit 14 and the load pulse output from the RPG 15a are input. The shift register 15c converts the (n + 1) th VALID signal based on the load pulse into the shift register 1c.
An output VALID signal which is a read enable ENABLE signal for the reproduction data created in step 5b is created. And the created output VA
The LID signal is output in synchronization with an external clock signal input from the outside. At this time, the external clock signal is output to the outside again as an output clock signal.

FIG. 9 shows the multiplexer 15 shown in FIG.
6 is a timing chart for explaining switching between valid / invalid of output data in FIG. When the signal output at each output terminal is in the state as shown in the figure, that is, in synchronization with the output CLOCK signal, the output data "apqrstu ..." is output to the data output terminal, and the output VALID signal is If the output data is output from a time such as "p", the valid output data is "pqrstu ...".
When n = 2, such output data is stored in the shift register 15b as “prt...” And “q
"su ..." is input.

As described above, in the present embodiment, a plurality of data storage devices are provided in the data recording / reproducing device, and the recording data input from the outside at high speed is separated and stored in the plurality of data storage devices in parallel. Can be. Also, by synchronizing and multiplexing the separated data stored in a plurality of data storage devices, reproduced data can be output to the outside at high speed, and the data recording / reproducing device can be output without changing the signal frequency or the number of channels. Can increase the data transfer speed with the outside.

In the above description, the valid / invalid switching of the recording data input from the outside is performed by the ENABLE signal as shown in the time chart of FIG. 4, but another method is used for this switching. It is also possible to apply. That is,
The ENABLE signal may always be set to “H”, and the external CLOCK signal may be input only when there is data to be recorded.

Next, the second embodiment of the data recording / reproducing apparatus of the present invention will be described.
An embodiment will be described. FIG. 10 is a block diagram showing the configuration of the second embodiment of the data recording / reproducing apparatus of the present invention. Note that the configuration of the second embodiment is the same as that of the first embodiment except that only the controller 12 is removed.
Detailed description is omitted.

The data recording / reproducing device 10a includes a demultiplexer 11, data storage devices 13a and 13b,
It comprises an FO memory 14 and a multiplexer 15.

Here, the operation commands input to the data storage devices 13a and 13b correspond to the data recording / reproducing device 10a.
It is configured to be directly input from outside. This operation command may be the same as that conventionally output for requesting the data storage device to record and reproduce data, but before the recording data and the ENABLE signal are input to the data recording / reproducing device 10a. Data storage device 13
a, 13b.

As described above, in the data recording / reproducing apparatus of the present invention, the operation command can be directly input to the data storage device from the outside of the apparatus, and the configuration of the apparatus can be further simplified. If the number n of data storage devices is not a large number, this can reduce the cost.

Next, the third embodiment of the data recording / reproducing apparatus of the present invention will be described.
An embodiment will be described. FIG. 11 is a block diagram showing the configuration of the third embodiment of the data recording / reproducing apparatus of the present invention. Since the configuration of the third embodiment has many parts that are the same as the configuration of the first embodiment, the same components are denoted by the same reference numerals, and detailed description is omitted.

The data recording / reproducing device 20 includes a demultiplexer 21, a controller 12, a data storage device 23
a, 23b, a FIFO memory 14, and a multiplexer 15.

Here, the data recording / reproducing apparatus 20 has 2x (b
ps), an input terminal that receives the ENABLE signal, and an input terminal that receives the external CLOCK signal. The data recording / reproducing apparatus 20 has an output terminal for outputting 2x (bps) output data, an output terminal for outputting an output VALID signal, and an output terminal for outputting an output CLOCK signal. Data is exchanged with the outside via the output terminal. Note that the data recording / reproducing device 20 is also provided with a command input terminal.

The demultiplexer 21 receives 2 × (bps) input data in synchronization with the external CLOCK signal only while the ENABLE signal is true. Then, the received input data is separated into the number of data storage devices provided in the data recording / reproducing device. Data recording / reproducing device 20 shown in FIG.
Is provided with two data storage devices, the demultiplexer 21 converts the input data into the separated data 1 of x (bps).
x (bps) is separated into two data. Further, the demultiplexer 21 creates an internal ENABLE signal required when the separated data separated here is input to the data storage devices 23a and 23b. Further, the demultiplexer 2
In step 1, similarly to the input data, the external clock signal is frequency-divided by the number of data storage devices to generate a frequency-divided clock signal. In the data recording / reproducing apparatus 20 shown in FIG.
It has twice the cycle of the CLOCK signal. The internal configuration of the demultiplexer 21 will be described later.

The controller 12 receives an external command and inputs it to the data storage devices 23a and 23b as an internal command. The separated data 1 of x (bps), an internal ENABLE signal, a frequency-divided CLOCK signal, and an internal command are input to the data storage device 23a. In the data storage device 23a, the input internal command is a data recording command, and the internal EN
If the ABLE signal is "H", the separated data 1 is recorded as the recording data 1 in synchronization with the frequency-divided CLOCK signal. If the internal command is a data reproduction command, the recording data 1 is output as reproduction separated data 1 together with a first VALID signal in synchronization with the internal first CLOCK signal having the same cycle as the frequency-divided CLOCK signal.

This data storage device 23a is different from the data storage device 13a of the first embodiment,
A CLOCK signal (here, a divided CLOCK signal is used) is always required. Therefore, when input data is stored, switching between valid / invalid is performed by an ENABLE signal (here, an internal ENABLE signal is used). Although the structure of the data storage device 23b is almost the same as the structure of the data storage device 23a, what is input is not the separated data 1 but the separated data 2. In this case, the output is not the separated data for reproduction 1 synchronized with the internal first clock signal, but the separated data for reproduction 2 synchronized with the internal second clock signal. Also, the first VA
The second VALID signal is added instead of the LID signal.

The FIFO memory unit 14 stores the reproduction separated data 1 output from the data storage device 23a and the first VA
The LID signal, the internal first CLOCK signal, the separation data for reproduction 2 output from the data storage device 23b, the second VALID signal, and the internal second CLOCK signal are input. Then, the FIFO memory unit 14 synthesizes a third VALID signal from the first VALID signal and the second VALID signal, and synchronizes with the divided data 1 for reproduction and the reproduced The separated data 2 and the third VALID signal are output.

The multiplexer 15 multiplexes the separation data for reproduction 1 and the separation data for reproduction 2 input from the FIFO memory unit 14 to create 2 × (bps) output data. Then, an output VALID signal is generated from the third VALID signal and the frequency-divided CLOCK signal, and the output data is output together with the output VALID signal in synchronization with the external CLOCK signal. The output clock signal output simultaneously here is the same as the external clock signal.

As described above, in the data recording / reproducing apparatus of the present invention, the processing speed of data transfer with the outside can be set to nx by providing n data storage devices having the processing speed x inside. FIG. 11 shows an example in which two data storage devices are provided, but this number can be increased to an arbitrary number.

Here, the internal configuration of the demultiplexer 21 shown in FIG. 11 will be described. FIG.
3 is a block diagram showing the internal configuration of the demultiplexer 21 shown in FIG.

The demultiplexer 21 constituting the data recording / reproducing apparatus of the present invention includes shift registers 21a and 21d.
, Counters 21b and 21e, and D-flip-flops (D-FF) 21c, 21f and 21g. The demultiplexer 21 is provided with three input terminals, and receives nx (bps) input data, an ENABLE signal, and an external CLOCK signal from outside the data recording / reproducing device 20. Hereinafter, the number of data storage devices is not particularly limited to two, and is described as n.

The shift register 21a has a data input terminal for receiving input data and an EN for receiving an ENABLE signal.
It has an ABLE terminal and a CLOCK terminal for receiving an external CLOCK signal. Here, unlike the first embodiment, the external CLOCK signal is always input. Then, the shift register 21a validates only the data input to the data input terminal while the ENABLE signal is input to the ENABLE terminal. The valid input data is separated by n, and n separated data of x (bps) are created, each of which is separately D-FF 21c
Is input to

The counter 21b has an ENABLE terminal for receiving an ENABLE signal and a CLOCK terminal for receiving an external CLOCK signal. Then, only while the ENABLE signal is being input to the ENABLE terminal, a frequency-divided CLOCK signal obtained by dividing the external clock signal by n is created and output.

The D-FF 21c has a shift register 21
Separate data 1 to separate data n are input from a. D-
After holding all the input separated data, the FF 21c outputs each of them separately in synchronization with the frequency-divided CLOCK signal input from the counter 21b.

Here, the output of the D-FF 21c is based on the frequency-divided CLOCK signal created under the influence of the ENABLE signal input from the outside. The output separated data 1 to separated data n may be irregular. Therefore, the demultiplexer 21 according to the present embodiment includes a shift register 21d, a counter 21e, and a D-FF 21.
f, 21g are provided.

The shift register 21d includes a counter 21b
Receives the same frequency-divided CLOCK signal as input to the D-FF 21c from the external clock signal nCL.
An “H” pattern corresponding to OCK is generated and input to the D-FF 21g. The counter 21e simply outputs the external CLOCK signal to n
Divide the frequency to create a stable frequency-divided CLOCK signal. DF
The F21f holds all the separated data input from the D-FF 21c, and outputs each separately to the outside in synchronization with the stable frequency-divided CLOCK signal generated by the counter 21e. Then, the D-FF 21g counts the “H” pattern input from the shift register 21d into the counter 2
It is output in synchronization with the stable frequency-divided CLOCK signal created in 1e, and this is used as an internal ENABLE signal. The stable frequency-divided CLOCK signal generated by the counter 21e is also output to the outside.

FIG. 13 is a timing chart of the demultiplexer 21 shown in FIG. With the demultiplexer 21 having such a configuration, a stable frequency division CL is applied to the data storage devices 23a and 23b.
The OCK signal, the internal ENABLE signal, and the separated data 1 and 2 are input. Therefore, the data recording / reproducing device of the present invention can use a data storage device which always requires a stable CLOCK signal.

Next, the fourth embodiment of the data recording / reproducing apparatus of the present invention will be described.
An embodiment will be described. FIG. 14 is a block diagram showing the configuration of the fourth embodiment of the data recording / reproducing apparatus of the present invention. Note that the configuration of the fourth embodiment is obtained by removing only the controller 12 from the configuration of the third embodiment.
Detailed description is omitted.

The data recording / reproducing device 20a includes a demultiplexer 21, data storage devices 23a and 23b,
It comprises an FO memory unit 14 and a multiplexer 15.

Here, the operation command input to the data storage devices 23a and 23b corresponds to the data recording / reproducing device 20a.
It is configured to be directly input from outside. This operation command may be the same as that conventionally output to request data recording and reproduction from the data storage device, but before the recording data and the ENABLE signal are input to the data recording and reproduction device 20a. Data storage device 23
a, 23b.

As described above, in the data recording / reproducing apparatus of the present invention, the operation command can be directly input to the data storage device from the outside of the apparatus, and the configuration of the apparatus can be further simplified. If the number n of data storage devices is not a large number, this can reduce the cost.

[0073]

As described above, according to the present invention, a plurality of data storage devices having a low processing speed are provided inside a data recording / reproducing apparatus, and high-speed input data from the outside is separated into low-speed separation data. The data is recorded, and the output data to the outside is multiplexed and reproduced as high-speed reproduction data. As a result, high-speed data exchange with the outside becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle configuration of the present invention.

FIG. 2 is a block diagram showing a configuration of a first embodiment of a data recording / reproducing device of the present invention.

FIG. 3 is a block diagram showing the internal configuration of a demultiplexer.

FIG. 4 is a timing chart illustrating switching of valid / invalid of input data in a shift register in the demultiplexer illustrated in FIG. 3;

5A is a timing chart illustrating data storage of a data storage device, and FIG. 5B is a timing chart illustrating data reproduction of the data storage device.

FIG. 6 is a block diagram showing the internal configuration of a FIFO memory unit.

7A is a timing chart for explaining the operation of the VALID signal detection circuit shown in FIG. 6, and FIG.
7 is a timing chart illustrating an operation when an empty flag input terminal is provided in the VALID signal detection circuit shown in FIG.

FIG. 8 is a block diagram showing an internal configuration of a multiplexer.

FIG. 9 is a timing chart illustrating switching between valid / invalid of output data in the multiplexer illustrated in FIG. 8;

FIG. 10 is a block diagram showing a configuration of a data recording / reproducing apparatus according to a second embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a third embodiment of the data recording / reproducing apparatus of the present invention.

FIG. 12 is a block diagram showing the internal configuration of the demultiplexer shown in FIG.

FIG. 13 is a timing chart in the demultiplexer shown in FIG.

FIG. 14 is a block diagram showing a configuration of a data recording / reproducing apparatus according to a fourth embodiment of the present invention.

[Explanation of symbols]

1 ... data separation means, 2 ... control means, 3a to 3n ...
... data storage means, 4 ... synchronization means, 5 ... data multiplexing means.

Claims (4)

[Claims] 1. A data recording / reproducing apparatus for recording / reproducing data at a predetermined speed, comprising: data separating means for separating recording data input at a high speed to generate separated data transmitted at a low speed; A plurality of data storage means for recording the separation data as recording data and outputting the recording data as reproduction separation data; and temporarily holding the reproduction separation data output at a low speed from the plurality of data storage means. And a data multiplexing unit that multiplexes the separation data for reproduction output from the synchronization unit to create reproduction data that is output at a high speed, and outputs the reproduction data. Characteristic data recording / reproducing device. 2. An apparatus according to claim 1, further comprising: an input / output control unit for outputting a data recording instruction for instructing data recording or a data reproduction instruction for instructing data reproduction, wherein said data storage unit receives said data recording instruction. 2. The data recording / reproducing apparatus according to claim 1, wherein in the case, the separated data is recorded as recording data, and when the data reproduction command is received, the recording data is output as separated data for reproduction. 3. The recording data is input together with an external clock signal, and the data separating means divides the external clock signal to generate a divided clock signal, and synchronizes with the divided clock signal. 2. The data recording / reproducing apparatus according to claim 1, wherein the separated data is output, and the synchronization means outputs the reproduced separated data in synchronization with the frequency-divided clock signal. 4. The recording data is input together with an external clock signal and an enable signal, and the data separation means divides the external clock signal to create a divided clock signal, and outputs the divided clock signal to the divided clock signal. The separated data and the enable signal are output in synchronization with each other, and the data storage unit records the separated data as the recording data when the separated data is input together with the divided clock signal and the enable signal. 2. The data recording / reproducing apparatus according to claim 1, wherein