KR100218109B1 - Device for processing time code for simultaneous recording and reproducing in a video recording and reproducing device - Google Patents

Abstract

The present invention relates to a time code processing apparatus for an image recording / reproducing apparatus, and more particularly, A time code generator for periodically generating a time code with reference to a previously generated time code; A time code reader for reading an external serial time code and converting it into a parallel time code; A first time code memory for storing a time code generated in the time code generator; A second time code memory for storing a time code read from the time code reader; A first buffer coupled between the time code generator and a first time code memory to buffer a first bus; A second buffer connected between the time code reader and the second time code memory for buffering the second bus; A third buffer connected between the central processing unit and the first time code memory for buffering a third bus; A fourth buffer connected between the central processing unit and the second time code memory to buffer a fourth bus; A bus arbiter for arbitrating whether or not to use the bus in response to a bus request signal of the central processing unit, the time code generator, and the time code reader; And a bus controller (56) for controlling the first to fourth buffers and the first and second time code memories.

Description

A time code processing device for simultaneous recording / reproduction of an image recording / reproducing apparatus

The present invention relates to a time code processing apparatus for a video recording / reproducing apparatus, and more particularly, to a video codec for video recording / reproducing apparatuses for video recording / playback which can process a time code so that recording / And a time code processing apparatus for simultaneous recording / reproduction of the apparatus.

1, a conventional time code processing apparatus of a digital video disk recording / reproducing apparatus for a broadcasting station includes a central processing unit 10, a time code generator 12, a time code reader 14, a time code memory 16, A first buffer 18 connected between the code generator 12 and the time code memory 16 to buffer the first bus 19 and a second buffer 18 connected between the time code reader 14 and the time code memory 16, A second buffer 20 for buffering the second bus 21, a third buffer 22 for buffering the first bus 19, a central processing unit 10 and the second bus 19 A fourth buffer 26 for buffering the time code memory 16, a first buffer 26 for buffering the time code data, a time code memory 16, a first buffer 17, and a second buffer 16 in response to each bus use request signal of the central processing unit 10, the time code generator 12, And a bus arbiter 24 for controlling the third buffer to the third buffer. The first and second buffers 18 and 20 are connected to the time code memory 16 through a first common bus 17 and the third and fourth buffers 22 and 26 are connected to the central processing unit 10 and 2 common bus 11, respectively. The black for each bus is the data bus and the white for the address bus. The bus arbiter 24 generates enable signals of the first to fourth buffers such as * cpu_en, * tcg_en, and * tcr_en in response to each bus request signal such as * cpu_req, * tcg_req, * tcr_req, And generates a bus use authorization signal of the central processing unit.

The central processing unit 10 can refer to the contents of the time code memory 16 by obtaining the bus access authority while the time code generator 12 and the reader 14 are not performing bus operations The time code reader 14 can refer to the time code memory 16 because the time code reader 14 does not operate when the time code generator 12 desires to use the bus and the time code reader 14 operates similarly do. Also, the time code generator 12 and the time code reader 14 share the same time code memory 16 although they do not use the same memory address.

Thus, the prior art is that only one controller (central processing unit, time code generator, time code reader) can access the time code memory 16 at any one time. That is, in the case of a broadcast image editing system capable of recording and playback such as a DVD (Digital Video Disc) recorder, the conventional technology consumes too much time to control the bus when recording and playback are simultaneously performed, It may have an overhead in processing of the processing unit. That is, when both the time code generator 12 and the time code reader 14 do not access the bus in the case where simultaneous recording and playback are required, both time code values must be read. This can result in significant performance degradation in the system.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and apparatus for simultaneously recording and / or reproducing data in a video recording / reproducing apparatus capable of improving the performance of a system, And to provide a code processing device.

In order to achieve the above objects, A time code generator for periodically generating a time code with reference to a previously generated time code; A time code reader for reading an external serial time code and converting it into a parallel time code; A first time code memory for storing a time code generated in the time code generator; A second time code memory for storing a time code read from the time code reader; A first buffer coupled between the time code generator and a first time code memory to buffer a first bus; A second buffer connected between the time code reader and the second time code memory for buffering the second bus; A third buffer connected between the central processing unit and the first time code memory for buffering a third bus; A fourth buffer connected between the central processing unit and the second time code memory to buffer a fourth bus; A bus arbiter for arbitrating whether or not to use the bus in response to a bus request signal of the central processing unit, the time code generator, and the time code reader; And a bus controller (56) for controlling the first to fourth buffers and the first and second time code memories.

1 is a block diagram showing a configuration of a time processing apparatus of a conventional video recording / reproducing apparatus.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a time code processing apparatus for simultaneous recording / reproduction of a video recording / reproducing apparatus.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention.

2 shows a configuration of a time code processing apparatus for simultaneous recording / reproduction of an image recording / reproducing apparatus according to the present invention. The apparatus of FIG. 2 includes a central processing unit 30, a time code generator 32 for periodically generating a time code with reference to a previously generated time code, a time code reader 32 for reading an external serial time code, A first time code memory 36 for storing a time code generated by the time code generator 32, a second time code memory 38 for storing a time code read by the time code reader 34, A first buffer 42 connected between the time code generator 32 and the first time code memory 36 to buffer the first bus 40, a time code reader 34 and a second time code memory 34, A second buffer 46 connected between the central processing unit 30 and the first time code memory 36 to buffer the third bus 48, A third buffer 50 which is connected between the central processing unit 10 and the second time code memory 38, The fourth buffer 54 is buffering the fourth bus (52); A bus arbiter 56 for arbitrating whether or not to use the bus in response to the bus request signals of the central processing unit 30, the time code generator 32 and the time code reader 34; And a bus control unit 58 for controlling the first and second time code memories 36 and 38.

In order to generate a time code, a time code value of 4 bits per each digit (hour, minute, second, and whole frame of 4 bytes) is stored in a predetermined address of the memory 36 by the time code generator 32 When the data is stored, the central processing unit 30 can take the time code value by reading the value of the corresponding address in the memory 36. In addition, the time code generator 32 always reads the value in the memory 36 before outputting the time code value, since the previous time value must be referred to in order to output the next time code value. And then the time code value is written into the memory 36 again.

In addition, in the time code reader 34, when a serial time code value from the outside is input independently of the time code generator 32, the signal is analyzed and converted into an appropriate time code value. The converted time code value It is required to be recorded in a separate memory 38 since the 4 bits must be referred to by the central processing unit 30. [ Each time the read request signal from the central processing unit 30 is received, the stored value is read out from the memory 38 at the address.

The data buffer 50a of the third buffer 50 is connected to the third bus 48 and the third bus 48 for simultaneous memory access of the first time code memory 36 and the second time code memory 38. [ The data buffer 56a of the fourth buffer 54 is connected to the lower 4 bits of the common data bus 60 of the central processing unit 30 and the data buffer 56a of the fourth buffer 54 is connected to the common data of the central processing unit 30 And is connected to the upper four bits of the bus 60. The address buffer 50b of the third buffer 50 is connected to the third bus 48 and the common address bus 62 of the central processing unit 30 and the address buffer 56b Is connected to the fourth bus 52 and the common address bus 62 of the central processing unit 30.

Since the time code reading due to the generation of the time code and the occurrence of the interruption periodically generates or reads the code by the predetermined frequency of the time code generator 32 and the time code reader 34, The data signal line and the bus must be separated and separated by the buffer and the address and data buses of the two controllers and the address and data buses of the central processing unit.

The first to fourth buffers 42, 46, 50 and 54 are connected to data buses 42a, 42b and 42c, respectively, which interconnect the data buses 40a, 44a, 48a and 52a of the buses 40, And address buffers 42b, 46b, 50b, and 54b interconnecting the address buses 40a, 40a, 50a, and 54a and the address buses 40b, 44b, 48b, and 52b.

The bus arbiter 56 generates a bus use authorization signal according to the following logical expression.

* cpu_gnt = (! * tcg_req #! * tcr_req) * cpu_req

* tcr_gnt = * tcr_req

* tcg_gnt = * tcg_req

Here, * tcg_req, * tcr_req, and * cpu_req are bus request signals generated respectively by the time code generator, the time code reader, and the central processing unit, and * cpu_gnt, * tcr_gnt, and * tcg_gnt are bus use granting signals.

The control signals tcg_controll, tcr_controll, and cpu_controll applied to the bus controller 58 include a bus use grant signal, a memory read control signal, and a memory write control signal, respectively.

The bus control unit 58 generates a buffer enable signal according to the following logical expression.

* tcg_en = * tcg_req

* tcr_en = * tcr_req

* cpu_en1 =! * tcg_req

* cpu_en2 =! * tcr_req

Further, the bus control unit 58 generates a memory control signal according to the following logical expression.

* tcg_cs = * tcg_en * cpu_en1

* tcg_rd = * tcg_rd * cpu_rd

* tcg_wr = * tcg_wr * cpu_wr

* tcr_cs = * tcr_en * cpu_en2

* tcr_rd = * tcr_rd * cpu_rd

* tcr_wr = * tcr_wr * cpu_wr

Here, cs is a chip selection signal, rd is a read control signal, and wr is a write control signal.

With this configuration, the following eleven operations can be performed.

1) When only the time code generator 32 accesses the memory

Only the first buffer 42 is enabled and the other buffers 46, 50 and 54 are disabled (* tcg_en = * tcg_req).

2) When only the time code reader 34 accesses the memory

Only the second buffer 46 is enabled and the other buffers 42, 50 and 54 are disabled (* tcr_en = * tcr_req).

3) When only the central processing unit 30 accesses the memory

Only the third buffer 50 or the fourth buffer 54 is enabled and the other buffers 42 and 46 are disabled (* cpu_en1 =! * Tcg_req or * cpu_en2 =! * Tcr_req).

4) When the time code generator 32 owns the bus and the time code reader 34 makes a request for ownership of the bus, it is independent of each other.

5) When the time code reader 34 owns the bus and the time code generator 32 makes a request for ownership of the bus, it is independent of each other.

6) When the time code generator 32 owns the bus, the central processing unit 30 makes a request for ownership of the bus

After holding the bus request signal of the central processing unit 30, after the bus operation of the time code generator 32 is completed, the ownership of the bus is passed to the central processing unit 30. [

* tcg_en = * tcg_req

* cpu_gnt =! * tcg_req * cpu_req

7) When the time code reader 34 owns the bus, the central processing unit 30) requests the ownership of the bus

After the bus request signal of the central processing unit 30 is held and the bus operation of the time code reader 34 is completed, the ownership of the bus is passed to the central processing unit 30. [

* tcr_en = * tcr_req

* cpu_gnt =! * tcr_req * cpu_req

8) When there is a bus request by the time code generator 32 when the central processing unit 30 owns the bus

And passes ownership of the bus to the time code generator 32 after finishing the bus cycle by the current central processing unit 30. [

* cpu_gnt =! * tcg_req * cpu_req

* cpu_en = * cpu_gnt

9) When there is a bus request by the time code reader 34 when the central processing unit 30 owns the bus

And passes the ownership of the bus to the time code reader 34 after finishing the bus cycle by the current central processing unit 30. [

* cpu_gnt =! * tcr_req * cpu_req

* cpu_en = * cpu_gnt

10) When there is a simultaneous memory access request of the central processing unit 30 when the time code generator 32 and the time code reader 34 simultaneously access the memory

* tcg_en = * tcg_req

* tcr_en = * tcr_req

* cpu_gnt = (! * tcg_req #! * tcr_req) * cpu_req

11) When the central processing unit 30 owns the bus and there is a bus request signal of the time code generator 32 and the time code reader 34

And passes ownership of the bus to the time code generator 32 and the time code reader 34 after finishing the bus cycle by the current central processing unit 30. [

* cpu_gnt = (! * tcg_req #! * tcr_req) * cpu_req

* cpu_en1 = * cpu_gnt

* cpu_en2 = * cpu_gnt

As described above, according to the present invention, since the memory use of the time code generator and the time code reader can be used independently of each other, simultaneous recording / playback can be performed, thereby improving the performance of the system.

Claims (6)

A central processing unit; A time code generator for periodically generating a time code with reference to a previously generated time code; A time code reader for reading an external serial time code and converting it into a parallel time code; A first time code memory for storing a time code generated in the time code generator; A second time code memory for storing a time code read from the time code reader; A first buffer coupled between the time code generator and a first time code memory to buffer a first bus; A second buffer connected between the time code reader and the second time code memory for buffering the second bus; A third buffer connected between the central processing unit and the first time code memory for buffering a third bus; A fourth buffer connected between the central processing unit and the second time code memory to buffer a fourth bus; A bus arbiter for arbitrating whether or not to use the bus in response to a bus request signal of the central processing unit, the time code generator, and the time code reader; And a bus control unit (56) for controlling the first to fourth buffers and the first and second time code memories, wherein the time code processing unit for simultaneous recording / reproduction of the video recording / . The apparatus of claim 1, wherein the third buffer connects the third bus with the lower four bits of the data bus of the central processing unit, the fourth buffer connects the fourth bus and the upper four bits of the data bus of the central processing unit, Wherein the time code is recorded in the recording medium. 2. The video recording / reproducing apparatus according to claim 1, wherein the first to fourth buffers each comprise a data buffer for interconnecting the data buses of the buses and an address buffer for interconnecting the address buses. A time code processing device for playback. The apparatus of claim 1, wherein the bus arbiter generates a bus use authorization signal according to the following logical expression. * cpu_gnt = (! * tcg_req #! * tcr_req) * cpu_req * tcr_gnt = * tcr_req * tcg_gnt = * tcg_req 5. The apparatus of claim 4, wherein the bus controller generates an enable signal according to the following logical expression. * tcg_en = * tcg_req * tcr_en = * tcr_req * cpu_en1 =! * tcg_req * cpu_en2 =! * tcr_req The apparatus of claim 5, wherein the bus arbiter generates a memory control signal according to the following logical expression. * tcg_cs = * tcg_en * cpu_en1 * tcg_rd = * tcg_rd * cpu_rd * tcg_wr = * tcg_wr * cpu_wr * tcr_cs = * tcr_en * cpu_en2 * tcr_rd = * tcr_rd * cpu_rd * tcr_wr = * tcr_wr * cpu_wr