JP3482893B2 - Interface device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device for data communication used in a system for transmitting and receiving data, such as digital audio data, which changes in a time series at a predetermined cycle in packet units to a communication network. Regarding

[0002]

2. Description of the Related Art A data transmission system via a network is roughly classified into a synchronous system and an asynchronous system. Generally, in the synchronization method, a dedicated synchronization signal line or the like is provided between the transmission side and the reception side, and data is transmitted in synchronization with the synchronization signal line, so that the reception side uses the original data based on the transmitted data. The data can be reproduced accurately. Therefore,
The synchronous data transmission method is a method suitable for transmission of digital audio data or the like which requires accurate reproduction of the temporal position of information on the receiving side. However, it is necessary to provide a separate sync signal line or to have a structure for synchronizing transmission and reception. Further, during communication by the synchronous system, the line is dedicated only for that purpose, and there is a drawback that the versatility of the communication system is lacking.

On the other hand, the asynchronous method is suitable for transmitting character data or still image data such as personal computer communication because it is not necessary to secure a dedicated synchronous signal line. However, the packet transmission adopted in the asynchronous method is not suitable for transmission of digital audio data, etc., because the information on the original time position of data is lost.

[0004]

Therefore, recently, each node has a clock oscillation circuit and a clock counter for counting the clock, and the node on the transmission side indicates the time position of the data at the beginning of the packet data. Time data (time stamp) is added and the data is transmitted on the network. The receiving node compares the time data with the count value of the internal clock counter, and if both do not match, the count value is used as the time data. Then, a pseudo synchronization method has been adopted in which the data is sequentially reproduced based on the corrected count value of the clock counter. Such a pseudo-synchronous communication system is called an isochronous transfer system.
For example, there is IEEE 1394.

That is, in this pseudo-synchronization method, the clock oscillation circuit of each node does not always oscillate at the same frequency. Each time, that is, every time the time data is received, a method of correcting the count value of the clock counter according to the time data is adopted. In such a pseudo synchronization system, a FIFO memory capable of storing one packet or more of data is basically provided in a chip constituting an interface device, and data is transmitted / received in packet units.
Access of packet data to this FIFO memory is performed by the CPU or a peripheral I / O circuit. Therefore, the FIF
The size of the O memory has to be appropriately selected according to the application.

However, conventionally, there is a problem that a FIFO memory having a size larger than necessary is allocated because the versatility of the chip is prioritized, and the FIFO memory is wasted. On the contrary, when it is desired to increase the number of channels connected to the digital audio device, the size of the FIFO memory is small, which becomes a bottleneck, and the number of channels cannot be increased. The present invention has been made in view of the above points, and provides an interface device capable of efficiently changing the size of a buffer according to an application and efficiently transferring data.

[0007]

An interface device according to the present invention has an isochronous transfer cycle.
Via a communication network capable of isochronous transfer
In order to perform the transmission of de Tapaketto, the transmitting node
In an interface device used, transmitted all
An interface chip having a memory means for buffering can de Tapaketto to control the interface chip, and control means for controlling the transmit data packet to said communication network, any number to said control means mosquitoes the interface chip
1-eye in the communication network with a caded connection
In the sochronous transfer cycle, the control means
Control means or a circuit circulating through the interface chip
It outputs a start signal and the interface chip
The buffered data according to the input of the start signal
To the control means and the start signal
Output downstream, and the control means outputs the interface command.
The data output by the
It is sent to the work and the start signal is returned.
Depending on the return, the 1 isochronous transfer at the node
It is characterized in that the data transmission within the transmission cycle is ended . In addition, the interface according to the present invention
The face device has an isochronous transfer cycle.
Data is transferred via a communication network capable of isochronous transfer.
Used by the receiving node to receive data packets.
Interface device used for receiving received data
Interface having storage means for buffering data
Controls the chair chip and the interface chip,
Controls the reception of data packets from the communication network
Control means for controlling,
Connect a number of the interface chips and connect the communication
Within one isochronous transfer cycle in network
The control means responds to the reception of the data packet.
And receivable signals parallel to the interface chip
Output and the interface chip can receive the
The data packet included in the data packet according to the input of the active signal.
Data that the data should be received by the interface chip
It is determined that it should be received and
If the data contained in the data packet is
It is characterized by being buffered in storage means.

As a result, the user can configure a lean interface device by appropriately increasing or decreasing the number of interface chips according to the application purpose. For example, when transmitting and receiving high-speed and large-capacity data such as digital audio on a plurality of channels, a required number of interface chips each having a relatively large storage capacity are connected, which allows the interface device to operate. The total capacity of the buffer can be apparently increased, and a large capacity of data such as audio data can be transmitted and received on a plurality of channels. On the other hand, in the case of transmitting / receiving a relatively small amount of data such as MIDI data at a relatively low speed for a plurality of channels, it can be dealt with by connecting a required number of interface chips having a storage unit of a relatively small storage capacity. it can. Further, when transmitting and receiving both large data such as digital audio and small data such as MIDI data for a plurality of channels, an interface chip having a storage unit having a relatively large storage capacity and a storage unit having a relatively small storage capacity are used. Can be dealt with by connecting the required number of interface chips each having.

The number of interface chips to be connected may be appropriately determined according to the capacity of the buffer storage means in the interface chip. Further, by assigning for each data which of a plurality of interface chips is used for transmission or reception, it is possible to transmit and receive a plurality of different types of data. Further, a plurality of interface chips including buffers having different sizes (that is, storage means having different storage capacities) may be connected to form an interface chip group having an optimum configuration for transmitting / receiving each type of data. .

In this interface device, one node of the plurality of nodes sends a reference signal to the communication network on a communication network to which a plurality of nodes that operate asynchronously are connected, as in the isochronous transfer system. Transmitting a plurality of data packets corresponding to a plurality of applications having a time-sequential arrangement together with time data indicating the elapsed time with respect to the reference signal, the other one of the plurality of nodes transmitting above. According to this, it can be preferably used in a data transmission system configured to perform the synchronous communication of the data packet between the plurality of nodes. When one of the plurality of nodes connected to the communication network serves as a transmitting node and the other one operates as a receiving node, the transmitting node transmits a plurality of data packets on the communication network and receives the data packets. The data is transmitted / received on the communication network by being received. On such a communication network, an interface is required for transmitting high-speed and large-capacity data such as digital audio on a plurality of channels, and for relatively low-speed and small-capacity data transmission on a plurality of channels, such as MIDI data. Connect multiple chips in cascade. As a result, the apparent capacity of the transmission / reception buffer can be increased, and a large capacity of data such as audio data can be transmitted on a plurality of channels. Further, in the case of transmitting data of a relatively small speed and a small capacity, such as MIDI data, for a plurality of channels, it can be dealt with by reducing the number of interface chips connected to the cascade.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an example of a transmission / reception node incorporating an interface device according to the present invention. FIG. 2 is a diagram showing a configuration example of data transmitted between the transmission / reception nodes of FIG. In addition,
In this specification, a case where data transmission is performed according to the above-mentioned IEEE 1394 communication method will be described.
FIG. 1 shows one transmission / reception node connected to the IEEE 1394 serial bus 20, but in addition to this, all kinds of transmission nodes that only perform transmission, reception nodes that only perform reception, etc. Serial bus 2
A plurality may be connected via 0. In this embodiment, when another node on the serial bus 20 sequentially outputs a cycle start packet signal corresponding to a synchronization signal (cycle sync) of a normal cycle period 125 μsec as shown in FIG. A case where the transmission / reception node transmits / receives a data string as shown in FIG. 2 to / from the serial bus 20 will be described.

The transmitting / receiving node of FIG. 1 has a predetermined frequency (for example, a frequency of 24.576 MHz (a period of about 40 nse) generated by a built-in crystal oscillator (not shown).
c)) having a CPU 11 that operates according to the clock,
A microcomputer system including the CPU 11, the ROM 12, and the RAM 13 sequentially generates a plurality of data having a time-series arrangement of a predetermined sampling period T, and the data is serialized by the chip control means 15 and the interface chips 16-18. The data is output to the bus 20 or taken in from the serial bus 20. Data transfer to the chip controller 15 and the interface chips 16 to 18 is performed by the DMAC (Dir).
ect Memory Access Contro
ller) 14. The chip controller 15 and the interface chips 16 to 18 are connected to each other by the internal bus 10. CPU11,
The ROM 12, RAM 13, DMAC 14, chip control means 15, and interface chips 16 to 18 are connected to each other via a CPU bus 19. In addition, each interface chip 16-18 has a start input terminal ST
It is connected in a cascade through ART_IN1 to START_IN3 and start output terminals START_OUT1 to START_OUT3. For example, when the transmitting / receiving node of FIG. 1 is included in an audio reproducing device such as a CD (Compact Disc) player, sample data of reproduced digital audio signal is output to the serial bus. If the transmitting / receiving node is included in a musical tone synthesizer that synthesizes musical tone sample data in real time, the synthesized musical tone waveform sampled data is output. The sampling cycle T of the data output from the transmission / reception node is appropriately variable according to the data source.

The CPU 11 has a function of operating as a 32-bit running counter that counts a clock of a predetermined frequency generated by a crystal oscillator (not shown), and outputs time stamp data, that is, time data according to the count value. Output. Chip control means 15
Controls interface chips 16-18 to send and receive data to and from serial bus 20. The interface chips 16 to 18 have a built-in buffer register that performs input / output asynchronously, and send / receive data to / from the serial bus 20 via the chip control means 15. A FIFO memory is used for this buffer register. The chip control means 15 has a predetermined transmission interrupt cycle (the synchronization signal (cyc) output from the other transmission / reception node described above.
2) based on the data temporarily stored in the interface chips 16 to 18 in synchronization with one isochronous cycle (isochron).
A data string 9 (hereinafter referred to as a “cycle packet string”) corresponding to a “noose cycle” is configured, and data is transmitted / received to / from the serial bus 20.

As shown in FIG. 2, the cycle packet string 9 is composed of a cycle start packet 91, a synchronous data packet group 92 and an asynchronous data packet group 93. The cycle start packet 91 is composed of 32 bits, the upper 20 bits of which are data indicating the cycle timing of the cycle packet string 9, and the lower 12 bits.
The bit is data indicating cycle start data X indicating how much time delay the cycle packet string 9 has been transmitted from a synchronization signal (cycle sync) on the communication network. By using the time data included in this cycle start packet, as is known in the isochronous transfer method, the count value of the running counter (CPU 11) of the node is set so that the time reference is shared by all the nodes. It has become.

The synchronous data packet group 92 is composed of a plurality of P packet data which are the targets of pseudo synchronous signal processing. In the figure, as an example, eight synchronous data packets for transmission from channel 1 to channel 8 and three kinds of synchronous data packets for reception transmitted from other nodes are shown. The number P of the synchronization data packets can be set arbitrarily. Each synchronization data packet has a predetermined number Q
There is a plurality of groups each of which is made up of one piece of data and time stamp data indicating any one of the pieces of data (the first data in this embodiment). In this embodiment, four data and one time stamp make one
One group is composed. That is, in the figure, one piece of time stamp data T1 and T2 is provided for four pieces of data D1 to D4 and D5 to D8, respectively. The time stamp data T1 indicates the time position of the first data D1, and the time stamp data T2 indicates the time position of the data D5. Therefore, each synchronous data packet is (Q
It is composed of an integral multiple of +1) data groups. Due to the communication of digital audio data, there are cases where data is transmitted even if the number of data is less than Q, but the description thereof will be omitted. Asynchronous data packet group 93
Is composed of a plurality of R packet data to be subjected to asynchronous signal processing. In the figure, two packet data of packet B and packet C are shown as an example. In addition,
Asynchronous data packets need not be present.

The chip control means 15 has a terminal END for inputting a signal output from the output terminal START_OUT3 of the last interface chip 18, and output terminals TxREQ1 to Tx of the interface chips 16 to 18.
It has a terminal TxREQ0 for inputting an active-low transmission enable signal Tx output from REQ3. Further, the chip control means 15 uses the active-low receivable signal Rx.
Input terminal Rx of each interface chip 16-18
Terminal RxSTB0 that outputs to STB1 to RxSTB3
, A terminal RxSTB0 for outputting a start signal to the terminal RxSTB1 of the interface chip 16, and an operation clock signal ECLK for each of the interface chips 16-1.
8 ECL1 to ECLK1 to ECLK3
With K0.

Each interface chip 16-18 has
Clock terminal EC for inputting the operation clock signal ECLK
LK1 to ECLK3 and start input terminals START_IN1 to START that input the start signal START
_IN3, receivable signal input terminals RxSTB1 to RxSTB3 for receiving the receivable signal Rx, and transmissible signal output terminals TxREQ1 to Tx for outputting the transmissible signal Tx.
xREQ3 and start output terminals START_OUT1 to START_OU for outputting the start signal START
And T3. Interface chip 16-
18 is daisy-chained with respect to the start signal START, and the start signal START is sequentially transmitted to the interface chips 16 to 18. Note that, for example, each of the interface chips 16 to 18 is assumed to be capable of transmitting and / or receiving a synchronous data packet for one channel.

FIG. 3 is a diagram showing an example of an interface chip suitable for transmitting / receiving a digital audio signal (typically PCM waveform sample data). This interface chip comprises a capture control circuit 31, an output control circuit 32, an isochronous reception buffer 33, an isochronous transmission buffer 34, and a DSP 35.
When the capture control circuit 31 receives the low level receivable signal RxSTB from the chip control means 15, it captures packet data from the internal bus 10, separates the packet data into a header portion and a data portion, and determines from the information in the header portion. If it is data to be received, the data portion is transferred to the isochronous reception buffer 33, and if it is not data to be received, it is ignored. On the other hand, the output control circuit 3
2 is a start input terminal STAR when data to be transmitted is stored in the isochronous transmission buffer 34.
When the start signal START is input to T_IN,
The header section information is added to the data stored in the transmission buffer 34, and the data is transmitted to the internal bus 10. This data is transmitted from the chip control means 15 to the outside via the internal bus 10. The output control circuit 32 outputs the start signal START from the start output terminal START_OUT to the next interface chip at the last transmission timing of the data in the transmission buffer 34. DSP
Reference numeral 35 exchanges data of a digital audio signal to be transmitted / received between the isochronous reception buffer 32 and the isochronous transmission buffer 33 and the CPU bus 19 (FIG. 1). As described above, each of the buffers 33 and 34 is a FIFO memory. The capacity of the FIFO memory may be one that corresponds to the synchronous data packet for one channel. The buffers 33 and 34 may be connected to the CPU bus 19 without providing the DSP 35.

FIG. 4 is a diagram showing an example of an interface chip suitable for transmitting and receiving MIDI signals. This interface chip includes an acquisition control circuit 41, an output control circuit 42, an isochronous reception buffer 43, an isochronous transmission buffer 44, and a parallel-serial converter 45.
And a serial-parallel converter 46. The capture control circuit 41 and the output control circuit 42 are the same as those in FIG. The MIDI signal is IEEE1394.
Since the communication speed is relatively slower than the communication speed, the special isochronous reception buffer 43 and the isochronous transmission buffer 44 do not have to exist, but it is desirable to use a buffer having a certain capacity for timing adjustment and data expansion. . It should be noted that the isochronous reception buffer 43 and the isochronous transmission buffer 44 are indicated by dotted lines in the figure because they do not have to exist. Parallel-
The serial converter 45 has an isochronous reception buffer 43.
The parallel MIDI data stored in is converted to serial and sent to the CPU bus 19. The serial-parallel converter 46 converts serial MIDI data fetched from the CPU bus 19 (FIG. 1) into parallel data and outputs it to the isochronous transmission buffer 44. Even if the special isochronous reception buffer 43 and the isochronous transmission buffer 44 are not provided,
The register means included in the parallel-serial converter 45 and the serial-parallel converter 46 functions as a buffer.

By properly combining an interface chip suitable for transmitting / receiving digital audio signals and an interface chip suitable for transmitting / receiving MIDI signals as shown in FIGS. 3 and 4, data of a cycle packet string as shown in FIG. 2 is transmitted / received. You will be able to.

Next, using the timing chart of FIG.
The operation of the interface device of FIG. 1 will be described. First,
In FIG. 5, each interface chip 16 and 17
In order to transmit the data Tx10 and Tx20 on the serial bus 20 of the communication network, the isochronous transmission buffer of the data Tx10 and the data Tx2 in advance.
0 is written. Then, these data Tx10 and Tx20 are input according to the input of the cycle start data.
To work. Here, TxREQ in FIG.
As shown in the column 0-3, the output terminals TxREQ of the interface chips 16 to 18 having the function of the transmission node.
From 1 to TxREQ3, an active low transmission enable signal Tx is given to the input terminal TxREQ0 of the chip control means 15. In this state, the cycle start data Cycle st
When the art 10 is transmitted, the chip control means 15 causes the cycle start data Cycle on the serial bus 20.
The start 10 is fetched, and as shown in the ED column of FIG. 5, it is converted into parallel data Cycle start 11
Is output to the CPU 11 and the active-low receivable signal Rx is input from the terminal RxSTB0 to the input terminals RxSTB1 to RxS of the interface chips 16 to 18.
Output to TB3. The state of this signal Rx is RxS in FIG.
It is shown in columns TB0-3. When this signal Rx is low, it is in the reception mode, and therefore when it is high, transmission is possible.

As described above, the CPU 11 receives the cycle start signal CYCLE START 11 and adjusts the value of the internal running counter to the time data. In addition, the cycle start signal Cycle s
When the parallel cycle start signal CYCLE START 11 is generated in response to the reception of the start 10, the chip control means 15 causes the start signal STA as shown in FIG.
RT is output and input to the start signal input terminal START_IN1 of the first interface chip 16. In response to the input of the start signal START to the start signal input terminal START_IN1, the output control circuit 32 (or 42) of the interface chip 16 (FIG. 3 or FIG. 4) receives the isochronous transmission buffer 34 (or 44).
A header portion is added to the data Tx10 in (FIG. 3 or FIG. 4) and the data is transmitted to the internal bus 10. The chip control means 15 receives the data Tx10 on the internal bus 10, converts it into serial data Tx11, and outputs it to the serial bus 20 on the communication network.

The output control circuit 32 (or 42) (FIG. 3 or FIG. 4) of the interface chip 16 uses the data Tx10.
Start output terminal START
The start signal is output from _OUT1 and the start input terminal START_IN of the next interface chip 17 is output.
Give to 2. In the interface chip 17, when a start signal is input from the start input terminal START_IN2, the output control circuit 32 (or 4) of the start signal is input as described above.
2) (FIG. 3 or FIG. 4) performs data transmission processing. That is, the isochronous transmission buffer 34 (or 4
4) A header portion is added to the data Tx20 in (FIG. 3 or 4) and the data Tx20 is sent to the internal bus 10. Chip control means 1
5 receives the data Tx20 on the internal bus 10, converts it into serial data Tx21, and transmits it to the serial bus 20 on the communication network. Although the start signal is output from the start output terminal START_OUT2 to the start input terminal START_IN3 of the next interface chip 18, in this example, the transmission buffer (34 or 44) of the interface chip 18 is used.
Since there is no data to be transmitted, the start output terminal START_OU of the interface chip 18
A start signal is immediately output from T3 and applied to the end terminal END of the chip control means 15. When confirming that the start signal has returned to the end terminal END, the chip control means 15 ends the data transmission at this isochronous timing.

The chip control means 15 is supplied from the interface chips 16 to 18 when transmitting the data supplied from the interface chips 16 to 18 to the communication network via the serial bus 20 on the communication network. Each data may be transmitted on a separate isochronous channel, or the data supplied from a plurality of interface chips 16 to 18 may be grouped into one block and transmitted on one isochronous channel. For example, the chip control means 15 uses the separate isochronous channel to transmit the data transmitted from the interface chips 16 to 18 on the communication network every time the interface chips 16 to 18 perform the data transmission processing as described above. The data may be output to the serial bus 20. Alternatively, even if the interface chips 16 to 18 perform the data transmission processing as described above, the chip control unit 15 outputs the data from the interface chips 16 to 18 until it confirms that the start signal has returned to the end terminal END. Instead of outputting the transmitted data to the serial bus 20 on the communication network, after confirming that the start signal has returned to the end terminal END, the data transmitted from each of the interface chips 16 to 18 is converted into one data. You may make it grouped as what corresponds to an isochronous channel, and output it to the serial bus 20 on a communication network. This allows
For example, when the audio data is transmitted through the three audio channels of the right channel, the left channel, and the center channel, it is possible to allocate an individual isochronous channel to each audio channel and transmit the audio data, or It is also possible to group together each audio channel and allocate one isochronous channel to transmit the audio data.

Returning to the explanation of the operation example of FIG. 5, when the synchronous data packet Rx10 is transmitted from the other node to the serial bus 20 of the communication network after the data transmission processing, the chip control means 15 causes the synchronous data packet to be transmitted. Rx
Internal bus 1 by converting 10 into parallel data Rx11
0 and outputs the receivable signal Rx to the input terminals RxSTB1 to RxS of the interface chips 16 to 18 respectively.
Output to TB3. Each interface chip 16-1
In 8, when the receivable signal Rx is given via the capture inputs RxSTB1 to RxSTB3, the data of the bus 10 is captured in the capture control circuit 31 or 41 (FIG. 3 or 4). In the capture control circuit 31 or 41, the bus 1
The packet data fetched via 0 is separated into a header portion and a data portion, and the packet data is transmitted in accordance with the information indicated by the header portion.
At 18, it is determined whether the data is to be received. When it is determined that the packet data should be received, the data portion of the packet data is loaded into the reception buffer 33 or 43 (FIG. 3 or 4).

Upon reception, the data of the individual isochronous channels transmitted via the serial bus 20 of the communication network may be stored in the reception buffers of the different interface chips 16 to 18, or The data received by one isochronous channel may be divided into a plurality of data groups and stored in the reception buffers of different interface chips 16-18. For example, when the data part of the received synchronization packet data is composed of a plurality of data groups to be received by the plurality of interface chips 16 to 18, each interface chip 16 to 18 has a data part of the synchronization packet data. Predetermined data contained in (1) is selectively loaded into its own reception buffer 33 or 43 (FIG. 3 or 4).

Further, as an example, the header part of each packet data contains information indicating the channel of the packet as information indicating the type of data stored in the data part. As described above, each of the interface chips 16 to 18 is provided corresponding to each channel, and according to the channel information included in the header part of the received packet data, reception of any of the corresponding interface chips 16 to 18 is performed. The data part of the packet data is loaded into the buffer 33 or 43. Note that there are audio channels and MIDI channels as the types of channels, and the capture control circuit 31 or 41 (FIG. 3 or FIG. 4) uses the audio channels and MIDI channels.
The channels are also distinguished, and the data having the channel information of the audio channel is received by the interface chips 16 to 18 having the structure shown in FIG. 3, and the data having the channel information of the MIDI channel is the interface chip 16 having the structure shown in FIG. It is as above-mentioned that it is made to be received by.

For example, if the information contained in the header portion of the data Rx11 indicates that the interface chip 16 should receive this data Rx11, the interface chip 16 will cause this data Rx11 to be received.
To receive. When the reception of the data Rx11 is completed, the data Rx is read by the CPU 11 via the bus 19 and the reproducing process is performed.

When performing the reproducing process, the reception buffer 33 or 43 of each of the interface chips 16 to 18 is used.
The data stored in (FIG. 3 or FIG. 4) may be individually sent to the reproducing means (not shown), or the data may be selectively or freely combined and batched and sent to the reproducing means. May be. For example, when the interface chips 16 to 18 correspond to the right channel, the left channel, and the center channel of the digital audio signal, respectively, the interface chips 16
The digital audio data of the right channel, the left channel, and the central channel stored in 18 to 18 may be independently sent to the reproducing means, or the right channel and the left channel stored in the interface chips 16 and 17 may be independently transmitted. The digital audio data may be selectively combined and sent to the reproducing means, or the digital audio data of all channels stored in the interface chips 16 to 18 may be combined and sent to the reproducing means.

Note that, in the example of FIG. 1, the interface device is shown for the sake of convenience in a cascade connection of three interface chips. In that case,
Although it is possible to transmit the synchronous data packets for transmission of three channels, it is impossible to transmit the synchronous data packets for transmission of more channels. However, it goes without saying that by increasing the number of interface chips to be connected by a necessary number, it is possible to transmit the synchronous data packet for transmission of the required number of channels. For example, in order to enable transmission of synchronous data packets for transmission of 8 channels as shown in FIG.
The interface chips may be connected in cascade. In that case, for example, of these eight interface chips, the first four are configured with interface chips suitable for transmitting and receiving digital audio signals as shown in FIG. 3, and the remaining four are as shown in FIG. MIDI
The interface chips can be combined in various ways such as being configured with an interface chip suitable for transmitting and receiving signals, and by appropriately adopting such various combinations, the data size of transmission and reception can be freely changed according to the application. Therefore, it is possible to dramatically improve the data transfer efficiency. Further, as described above with reference to FIG. 4, the capacity of the transmission / reception buffer of the interface chip suitable for transmitting / receiving the MIDI signal may be relatively small. Of course, the MIDI signal may be transmitted and received by using the interface chip as shown in FIG.

By the way, in the above-mentioned embodiment, the case where the reception buffer and the transmission buffer of each interface chip cannot transmit a synchronous data packet larger than one channel is shown as an example, but the reception buffer 32 or 42 is shown. The capacity of the transmission buffer 34 or 44 may be capable of buffering the synchronous data packets for a plurality of channels. In that case, the number of interface chips connected in cascade may be smaller than the number of channels. Further, each interface chip does not necessarily have to be configured for both transmission and reception. That is, in the transmission-only node,
In the interface chip of FIG. 3 or 4, the receiving buffer 33 or 43 and its related circuit may be omitted, and in the receiving-only node, the receiving buffer 33 or 43 and FIG.
The transmission buffer 34 or 44 and the circuit related thereto may be omitted in the interface chip of FIG.

[0032]

According to the interface device of the present invention, there is an excellent effect that the total size of the buffer memory can be freely changed according to the application and the data transfer can be efficiently performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a transmission / reception node incorporating an interface device according to the present invention.

FIG. 2 is a diagram showing a configuration example of data transmitted between the transmission / reception nodes of FIG.

FIG. 3 is a diagram showing an example of an interface chip suitable for transmitting / receiving a digital audio signal.

FIG. 4 is a diagram showing an example of an interface chip suitable for transmitting and receiving a MIDI signal.

5 is a timing chart diagram for explaining the operation of the interface device of FIG. 1. FIG.

[Explanation of symbols]

10 ... Internal bus, 11 ... CPU, 12 ... ROM, 13 ...
RAM, 14 ... DMAC, 15 ... Chip control means, 16
~ 18 ... Interface chip, 19 ... CPU bus,
20 ... Serial bus, 31, 41 ... Acquisition control circuit,
32, 42 ... Output control circuit, 33, 43 ... Isochronous reception buffer, 34, 44 Isochronous transmission buffer, 35 ... DSP, 45 ... Parallel-serial converter,
46 ... Serial-parallel converter

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-8-297566 (JP, A) JP-A-8-110876 (JP, A) JP-A-7-226073 (JP, A) JP-A-62- 115945 (JP, A) JP 62-245448 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/28 200 G06F 5/06 G06F 13/38 310

Claims (7)

(57) [Claims] 1. An eye having an isochronous transfer cycle.
In order to perform the transmission of de chromatography <br/> Tapaketto via a communication network capable Sokuronasu transfer, a interface device that is used <br/> at the transmitting node, the buffer transmission all-out de Tapaketto an interface chip having a memory means for, controlling the interface chip, and control means for controlling the transmit data packet to said communication network, any number of the interface chip with respect to said control means Cascade connection to the communication network
Within one isochronous transfer cycle
The control means through the control means or the interface.
A start signal circulating through the chip is output to
-The face chip is
When the buffered data is output to the control means,
To output the start signal downstream, and the control means
The data output by the interface chip is packetized.
And send it to the communication network
In response to the feedback of the start signal,
Note 1 End data transmission within isochronous transfer cycle
An interface device which is characterized by being. 2. The communication network has a plurality of channels for performing the isochronous transfer, the interface chips are assigned channels to be transmitted, and the control means is assigned to the interface chips. The interface device according to claim 1, wherein the data output from the interface chip is packetized using the different channel and transmitted to the communication network. 3. The control means packetizes one or a plurality of data output from the interface chip into a single packet and transmits the packet to the communication network in response to the feedback of the start signal. The interface device according to claim 1. 4. An interface device used in a receiving node for receiving a data packet through a communication network having an isochronous transfer cycle and capable of isochronous transfer, for buffering received data. And an interface chip having a storage means for controlling the interface chip and controlling reception of data packets from the communication network, and connecting any number of the interface chips to the control means. In one isochronous transfer cycle of the communication network, the control means outputs a receivable signal to the interface chip in parallel in response to the reception of the data packet, and the interface chip responds to the input of the receivable signal. It determines whether or not the data included in the data packet is data to be received by the interface chip, and buffers the data included in the data packet in the storage unit when it is determined that the data is to be received. An interface device characterized by being. 5. The communication network has a plurality of channels for performing the isochronous transfer, the interface chip is assigned a channel to be received, and the data packet is assigned to the interface chip. 5. The interface device according to claim 4, wherein the data contained in the data packet is buffered in the storage unit when the data packet is a data packet of a different channel. 6. The data packet has a header containing information about the channel used to transmit the data packet, and the interface chip refers to the header to determine whether or not the data is to be received. The interface device according to claim 5. 7. The data packet includes one to a plurality of data sequences, and the interface chip is set with a data sequence to be received, respectively.
The interface according to claim 4, wherein, when the data packet includes data to be received by the interface chip, the data of the data series to be received by the interface chip is selectively buffered in the storage means. apparatus.