JP3303687B2 - Data compression method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data compression method for compressing data of a plurality of channels and converting the data into serial data, and more particularly to a data compression method for reducing a data output delay time in data compression.

[0002]

2. Description of the Related Art Conventionally, in this type of data compression method, for example, when data of n channels is transmitted in the form of a packet, the data of each channel to be packetized is shared based on data in a frame. In some cases, data in a frame is written to a memory, and compressed data is sequentially read out at the timing of each channel, thereby packetizing each channel.

In this method, when a memory having n I / O ports is used, a write address and a read address can be commonly used for each channel, and the above operation can be realized by one memory. can do. In this case, for example, if a write address by a clock of v [Hz] and a read address by a clock of 2 nv [Hz] are input to the memory, the data becomes 2
It will be compressed n times.

[0004]

However, in this method, on the input side, data of each channel input in parallel is written to the memory at the same timing (same address) in frame units, and On the output side, packets are sequentially read out in a time slot designated for each channel and packetized, so that a data output with respect to a data input of a memory that performs speed conversion has a delay time. Since the delay time is defined by the order in which data is read from the memory, a difference occurs in the delay time, and the maximum delay time occurs in the n-th channel that is read last. The delay time in the packetization is required for the data length (frame length) input to the memory.

If the delay time differs between the channels as described above, for example, if the packet length p is 25
At 6 [bit] and transmission speed V = 64 [kbps], the data length T is 4 [ms], and the maximum (n = 16th channel)
Requires a delay time twice as long as the data length. For this reason, in real-time data transmission or the like where it is desired to prevent a delay time from being generated between input and output, it is necessary to select a used channel having a small delay time among n channels. There is a problem that the channel is limited and is not suitable for the real-time transmission.

The present invention has been made in view of the above problems, and has as its object to provide a data compression method capable of minimizing a delay time of data output with respect to data input in packetization.

[0007]

In order to achieve the above object, according to the present invention, data input asynchronously from a plurality of channels is independently written into a memory, each of the data is compressed and read, and a packet format is read. In a data compression method for converting data into serial data, a write address is cyclically output at a fixed cycle, the input data is written to the memory for each channel, and a write address to the memory and transmission of the data are performed. In accordance with the timing, the output start of the read address for each channel is controlled, and the data input within a predetermined time immediately before the start of the packet transmission is read from the memory at the same time as the end of the writing, and the data input is controlled. Minimize the delay time of data output.

That is, as for the read address, an optimum output start value is determined for each channel in accordance with the write address to the memory and the data transmission timing, and the read address is output with the determined optimum value. Thus, the delay time of data output is minimized. 4. The control method according to claim 3, wherein in the control of the read address, when the data transmission rates of the respective channels are the same, the data input from the respective channels are sequentially read from the memory simultaneously with the completion of the writing, and the data output corresponding to the data input is performed. Is the same for each channel.

That is, data of each channel is written at a predetermined address of a write address which is cyclically output, and a read address is controlled for each channel so that reading is performed sequentially upon completion of the writing.
The data output delay time is made common to each channel and minimized.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A data compression method according to the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing an example of a schematic configuration of a data compression device using a data compression method according to the present invention. In the figure, the data compression device has a clock generation circuit 11 for generating a reference clock for an address, a write control circuit 12 for outputting a write address based on the reference clock, and a plurality of I / O ports. A memory 13 comprising a RAM in which input and output to the I / O port can be accessed asynchronously;
A read control circuit 14 for controlling output start timing of a read address, and a data selection circuit 1 for converting parallel data from the memory 13 into serial data and outputting the serial data
And 5.

In this data compression device, as in the prior art,
The write address from the write control circuit 12 is shared by each channel. On the other hand, the read control circuit 14
Determines the optimum value of the output start of the read address for each channel from the transmission timing, and outputs the read address based on this determination. That is, in this data compression device, as shown in FIG. 2, the data input by the write control circuit 12 within the time T immediately before the start of packet transmission is read out at the same time as the completion of writing to the memory 13. The control circuit 14 controls the read address for each channel (1 to 3 channels in this example) so that the delay times DA, DB, and DC of the data output with respect to the inputs of the data A, B, and C are uniformly set for each channel. And minimize it.

Next, a case where the data compression apparatus according to the present invention is connected to a predetermined line network, for example, an optical multi-drop line network will be described. This optical multi-drop line network
For example, it is used in a system having a transmission capacity of (transmission speed V = 64 [kbps]) × (number of channels N = 16), and the data compression device compresses parallel data input from each channel by 2n times. When the transmission speed v is 2.048 [Mb
ps] and the packet length p is converted into serial data of a packet format of 256 [bit] and transmitted.

As shown in FIG. 3, the write control circuit 12 sets the write address at 0 to 5 at a transmission rate of 64 [kbps].
The data is cyclically output to the memory 13 with the address value of "11". Data of a frame length T (= p / V = 4 [ms]) is input to the memory 13 in this embodiment from each channel. The packet is composed of data from a single channel (hereinafter referred to as "single channel data"), and each channel is sequentially transmitted at time slot t intervals fixedly assigned by a pre-assignment method. And

That is, since the time slot t is divided by the number of channels N, t = T / N = (p / V) / N (1) By substituting the above numerical values into this equation (1),
t = 250 [μs].

Since the number of bits of input data per time slot is p / N, substituting each numerical value into this results in p / N = 16 [bit]. Therefore, in the present embodiment, as shown in FIG.
The write address is started based on the time slot of the channel, and the input data AP of each channel is set to be written to the memory 13 every 16 bits. As a result, data of each channel for two cycles is written to the memory 13 while the address value of the write address from the write control circuit 12 reaches “0” to “511”.

In this embodiment, the time slot 250 [μ
s], the transmission timing is t × 15 = 3.
A delay difference of 75 [ms] occurs. Here, the read address Adr (ou
t) is Adr (out) = (p / N) · (n−1) + x (2) where n: channel number x: coefficient composed of p (m−1) m: data cycle, 1 Or an integer of 2. As described above, the read control circuit 14 sets the output start value of the read address based on the position of the transmission timing and the position of the write address. In the above equation (2), x = 0, that is, m = 1 and n = 1
The address value “0” of the read address Adr (out) at the time of (1) becomes the start address. Then, the read address set for each channel as shown in FIG. 4 and as described below is output from the read control circuit 14 to the memory 13. FIG. 4 is a diagram showing a 256-bit read address in an odd cycle set for each channel in the memory 13.

1 channel: 0 to 255, 256 to 511 2 channels: 16 to 271, 272 to (511, 0) to 153 channels: 32 to 287, 288 to (511, 0) to 31::: 16 channels : 240 to 495, 496 to (511, 0) to 239 By inputting the read address, single-channel data is selected from the memory 13 at time slot intervals and at a transmission speed of 2.048 [Mbps]. Circuit 15
To be sequentially output.

The read control circuit 14 outputs a data select signal based on a time slot to the data select circuit 15. The data selection circuit 15 fetches single channel data of each channel output from the memory 13 in accordance with the input data select signal, converts the single channel data into serial data in packet format, and transmits the serial data.

Therefore, in this embodiment, control is performed to set the output start value of the read address to the memory in which the data is written for each channel, based on the data write address and the transmission timing. As a result, in this embodiment, even if the write addresses are collectively used as in the related art, the read address is set to the optimum value for each channel. Data transmission can be performed with the delay time, and the delay time in each channel does not vary, so that the delay time can be made uniform. For this reason, even if the data compression method of this embodiment is used for a system that emphasizes the response speed or a system that performs real-time transmission, it is not necessary to limit the channels used as in the conventional example, and the delay time of data output is reduced. The transmission accuracy can be improved by minimizing it.

[0020]

As described above, according to the present invention, data input from a plurality of channels asynchronously is independently written into a memory, each of the data is compressed and read, and converted into packet-format serial data. In the data compression method, a write address is cyclically output at a fixed period, and the input data is written to the memory for each channel, and according to a write address to the memory and a transmission timing of the data, The output start of the read address for each channel is controlled, and the data input within a predetermined time immediately before the start of the packet transmission is sequentially read from the memory simultaneously with the end of the write. Output delay time can be minimized.

According to the third aspect of the present invention, in the control of the read address, when the data transmission speed of each of the channels is the same, the data input from each of the channels is sequentially read from the memory at the same time as the completion of the writing. The delay time of the data output with respect to the data input can be minimized, and the delay time can be the same for each channel.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a schematic configuration of a data compression device using a data compression method according to the present invention.

FIG. 2 is a schematic timing chart of writing and reading of data by the memory shown in FIG. 1;

FIG. 3 is a specific timing chart of writing and reading of data by the memory shown in FIG. 1;

FIG. 4 is a diagram showing a 256-bit read address set for each channel in the memory shown in FIG. 1;

[Explanation of symbols]

 Reference Signs List 11 clock generation circuit 12 write control circuit 13 memory 14 read control circuit 15 data selection circuit

Claims (3)

(57) [Claims] 1. A data compression method for asynchronously writing data input from a plurality of channels into a memory, compressing and reading the data, and converting the data into serial data in a packet format. The cyclic data is cyclically output, the input data is written to the memory for each channel, and the write address to the memory and the transmission of the data are set so that the delay time of the data output with respect to the data input is reduced. A data compression method characterized by controlling output start of a read address for each channel according to a timing. 2. The read address control according to claim 1, wherein the start of the output of the read address is controlled so that data input within a predetermined time immediately before the start of the packet transmission is read from the memory simultaneously with the end of the write. ,
2. The data compression method according to claim 1, wherein a delay time of the data output with respect to the data input is reduced. 3. The read address control according to claim 2, wherein when the data transmission rates of the respective channels are the same, the data input from the respective channels are sequentially read from the memory at the same time as the completion of the writing. 1
Or the data compression method according to 2.