JPH0628012B2 - Constant voltage generator - Google Patents

Description

The present invention relates to a constant voltage generating circuit, and more particularly to a constant voltage generating circuit configured by using MOS transistors.

[Conventional technology]

Conventionally, as one of the constant voltage generating circuits, there is one that is configured by using a MOS transistor and generates a constant voltage by utilizing a band gap of silicon.

FIG. 2 is a circuit diagram of an example of a conventional constant voltage generating circuit.

The constant voltage generating circuit, N-channel enhancement type first MOS transistors T ₁ first MOS transistor source connected gate and drain to the gate of T ₁ of the Toko a first power supply (low potential side power supply) V _a first current mirror circuit composed of an N-channel enhancement type second MOS transistor T ₂ connected to _ss , and a first M
A drain and a gate of the OS transistor T ₁ are connected to the drain thereof, and a source thereof is connected to the second power source (high-potential-side power source) V _DD . A P-channel enhancement type third MOS transistor T ₃ and a second MOS transistor T _{3 The} drain is connected to the drain of the _second MOS transistor T ₃
A second current mirror circuit composed of a P-channel enhancement type fourth MOS transistor T ₄ whose gate is connected to the gate of the same and whose source is connected to the second power supply V _DD , and the first MOS transistor T ₁ Of the source and the first power supply V _ss, and a resistor R ₁ connected to the first power source V _ss . Then, the constant voltage V _R1 is taken out from both ends of the resistor R ₁ . This constant voltage V _R1 is determined by the loop gain of the MOS transistors forming the above two sets of current mirror circuits.

Now, assuming that the channel width-to-length ratio W / L of the MOS transistors T ₁ to T ₄ is m ₁ , m ₂ , m ₃ , and m ₄ , respectively, the constant voltage V _R1 is given by the following equation.

[Problems to be Solved by the Invention] Since the above-described conventional constant voltage generating circuit generates a constant voltage by the loop gain, the MOS transistors T ₂ and T ₃ may be affected by a power supply fluctuation, especially a rapid decrease of the power supply voltage. The impedance state is entered and the constant voltage generation circuit cuts off.

Further, since it does not have a special starting circuit, it is started by the leak current of each element caused by increasing the power supply voltage. For this reason, when the power supply is cut off due to a sudden drop, it has a drawback that it is not restarted until the leak current reaches a certain level.

It is an object of the present invention to provide a constant voltage generation circuit that restarts immediately even if the power supply voltage drops sharply and is cut off unless the power is cut off.

[Means for solving problems]

The constant voltage generating circuit of the present invention is an N-channel enhancement type first MOS transistor, and an N-channel enhancement type first MOS transistor in which a gate and a drain are connected to a gate of the first MOS transistor and a source is connected to a first power supply. A first current mirror circuit composed of two MOS transistors, and a third P-channel enhancement type whose drain and gate are connected to the drain of the first MOS transistor and whose source is connected to the second power supply. A fourth P-channel enhancement type MOS transistor having a drain connected to the drains of the MOS transistor and the second MOS transistor, a gate connected to the gate of the third MOS transistor, and a source connected to the second power supply; And a second current mirror circuit configured by A drain connected to the drain of the static source is connected to the source of said third MOS transistor and a gate connected to said second power source and said third MO
A fifth P-channel depletion type MOS transistor having a threshold value smaller than that of the S transistor, and a resistor connected between the source of the first MOS transistor and the first power supply. Composed of.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In this embodiment, a first MOS transistor T _{1 of} N-channel enhancement type, a gate and a drain of the first MOS transistor T ₁ are connected to the gate of the _first MOS transistor T ₁ , and the source is a first power source (low potential side power source) V _ss. A first current mirror circuit composed of an N-channel enhancement type second MOS transistor T ₂ connected to the second MOS transistor T ₂ and a drain and a gate of the first MOS transistor T ₁ connected to the drain and the second source of the _first MOS transistor T ₁ . A third P-channel enhancement type MOS transistor T ₃ connected to the power supply (high-potential-side power supply) V _DD , and a drain connected to the drain of the _second MOS transistor T ₂ and connected to the gate of the _third MOS transistor T ₃ . the P-channel enhancement type having a source to the second power supply V _DD gate connected to connect the fourth MOS transistor T ₄ A second current mirror circuit formed in the gate to the second power supply V _DD source to a third source of the MOS transistor T ₃ drain to the second drain of the MOS transistor T ₂ is connected to the connected connection Shikatsu 3rd MO
Connected between a P-channel depletion type fifth MOS transistor T ₅ having a threshold value smaller than that of the S transistor T ₃ and the source of the first MOS transistor T ₁ and the first power supply V _ss. It is configured to include a resistor R ₁ that is, the constant voltage V _R1 is extracted from both ends of the resistor R _1.

That is, the constant voltage generating circuit of the present invention is different from the conventional constant voltage generating circuit shown in FIG. 2 in that the fifth threshold voltage is lower than the threshold voltage of the third MOS transistor T ₃ of the P-channel depletion type. A MOS transistor T ₅ is added.

The threshold value of the fifth MOS transistor T ₅ is the third M
Since it is set lower than the threshold value of the OS transistor T ₃ , the fifth MOS transistor T ₅ is non-conductive when the constant voltage generating circuit is normally biased.

Now, if the constant voltage generation circuit is cut off for some reason, the gate-source potential of the _third MOS transistor T ₃ drops. At this time, the gate-source potential of the fifth MOS transistor _{T 5} becomes a threshold or less, turned on, current flows through a path of the MOS transistor _{T 3,} T 5, _{T 2,} MOS transistors _{T 3} and _{T 2}
The bias current is restored, and the constant voltage generating circuit is restarted. That is, the fifth MOS transistor T ₅ constitutes a starting circuit.

〔The invention's effect〕

As described above, according to the present invention, since the starter circuit including the depletion type transistor is added, even if the constant voltage generating circuit is cut off due to a sudden decrease in the power supply voltage, etc. There is an effect that a constant voltage generating circuit that restarts can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional constant voltage generating circuit. R ₁ ... Resistor, T ₁ ... First MOS transistor (N-channel enhancement type), T ₂ ... Second MOS transistor (N-channel enhancement type), T ₃ ... Third
MOS transistor (P-channel enhancement type), T ₄ ... Fourth MOS transistor (P-channel enhancement type), T ₅ ... Fifth MOS transistor (P-channel depletion type).

Claims (1)

[Claims] 1. A first M of N-channel enhancement type.
A first current mirror circuit composed of an OS transistor and a second MOS transistor of N-channel enhancement type whose gate and drain are connected to the gate of the first MOS transistor and whose source is connected to the first power supply; A drain and a gate are connected to the drain of the first MOS transistor, and a drain is connected to the drain of the second MOS transistor and a P-channel enhancement type third MOS transistor whose source is connected to the second power supply. A second current mirror circuit composed of a P-channel enhancement type fourth MOS transistor having a gate connected to the gate of a third MOS transistor and a source connected to the second power supply; and the second MOS The drain is connected to the drain of the transistor and the third MO
A P-channel depletion type fifth MOS transistor having a source connected to the drain of the S transistor and a gate connected to the second power supply and having a threshold value smaller than that of the third MOS transistor; A constant voltage generating circuit including a resistor connected between a source of a first MOS transistor and the first power supply.