JPH03227115A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent an inverted input voltage from being fluctuated even when a power voltage is fluctuated by providing a depletion transistor(TR) as a constant current element in series with a MOS TR whose gate receives an input signal. CONSTITUTION:A depletion MOS TR TD1 in series connection with an N-channel MOS TR TN1 acts as a constant current element. Then the inversion of an input signal A is decided by the inversion of a 1st stage NOR gate and the constant current characteristic is realized by using the TR TD1 connected to an output of the NOR gate as a load and the input inverted voltage is almost independent of a power voltage. That is, a constant current resistor, especially a depletion TR is provided on the input 1st stage circuit of the signal input circuit to avoid a power voltage dependency and the degradation in the characteristic of the input inverting voltage due to the noise of power supply or ground at a low or a high power supply voltage is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a signal input circuit composed of CMOS type transistors.

[Conventional technology]

As shown in FIG. 10, the signal input circuit of a conventional CMO8 type semiconductor integrated circuit includes a Pch transistor and an Nch transistor.
The transistors were constructed in a completely complementary manner.

In FIG. 10, this signal input circuit includes a P-channel, N-channel MO8 transistor TP2 1 TNI' whose gate input is an input signal A', and a transistor T'N
N-channel MO8 transistor 'r connected in parallel to +'
N2', transistor TP2', T,1' connected in series, and output stage P and N channel transistors TP3', T,+,3'. Node P' is connected to transistor T,! At the gates of ', TN,' and the common connection point of transistors TP2' and TNI',
Connected.

[Problem to be solved by the invention]

As shown in Figure 11, in the conventional signal input circuit described above, the input inversion voltage depends on the power supply voltage, so the operating margin with respect to the input voltage standard becomes small at high or low power supply voltages, and buffers etc. The disadvantage is that the input inversion voltage deteriorates due to the influence of generated power supply and ground noise.

FIG. 12 is an input/output voltage characteristic diagram of the conventional input first stage shown in FIG. 10, and the inversion level of the input voltage largely depends on the power supply voltage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit in which the above-mentioned drawbacks are solved and the input inversion voltage does not change even if the power supply voltage changes.

[Means to solve the problem]

The structure of the semiconductor integrated circuit of the present invention is characterized in that an eS constant current element is provided in series with a MOS transistor applied to an input signal chain.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor integrated circuit E according to a first embodiment of the present invention. FIG. 2 is a characteristic diagram showing the dependence of the input inversion voltage of the circuit of FIG. 1 on the power supply voltage.

FIG. 3 is a characteristic diagram showing the input/output voltage characteristics of the first input stage of the circuit of FIG. 1. In FIG. 1, the semiconductor integrated circuit of this example includes an N-channel MOS transistor TN1 to which an input voltage A is added to the gate, and an N-channel MOS transistor TN1 connected in parallel to this.
Channel MOS transistor TS, 2 and transistor T h'+ are connected in series to P channel MO8) transistor TPI, depression type MO8, transistor T
DI, and P and N channel MOS transistors TP31 to TN3 that output an output signal B from a common connection point. The gates of transistors TPI and TN2 are connected, the gate of transistor Tot is connected to contact P,
The transistor TP3+TN3 gate is also connected to the contact P. Here, transistor T'D+ functions as a constant current element. The input inversion voltage of the input signal A is determined by the inversion of the first stage NOR gate.
By using the depletion transistor TD1 connected to the output of the R gate as a load, constant current characteristics are exhibited, and as shown in FIG. 2, the input inversion voltage hardly depends on the power supply voltage.

As shown in FIG. 3, the inversion level of the input voltage A at the first input stage does not vary much depending on whether the power supply voltage is high, medium, or low.

FIG. 4 is a circuit diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention. In FIG. 4, the semiconductor integrated circuit of this embodiment includes MOS transistors TI, ROM, and T2.
Although not shown, the transistor T and 3° TN3 shown in FIG. 1 are provided. In the following examples, this part is omitted. Here, the transistor TDi is a depression type.

FIG. 5 is a circuit diagram of a third embodiment of the present invention, which includes an inverter consisting of a depletion type MOS transistor T'b+ and MOS transistors TI and T2 connected in series.

FIG. 6 is a circuit diagram of a fourth embodiment of the present invention, which includes a 2NAND gate consisting of a depression type MOS transistor TDI and MOS transistors T1 to T4.

FIG. 7 is a circuit diagram of a fifth embodiment of the present invention, which is a depression type MOS transistor T. 1 and 2NAND gates consisting of MOS transistors T1 to T4.

FIG. 8 is a circuit diagram of a sixth embodiment of the present invention, which is a depression type MOS transistor T. 1 and 2NOR gates consisting of MOS transistors T1 to T4.

FIG. 9 is a circuit diagram of a seventh embodiment of the present invention, which includes depression type MOS transistors TD1. MO8) Equipped with a 2NOR gate consisting of run transistors T1 to T4.

〔Effect of the invention〕

As explained above, the present invention has a constant current resistor, especially a depletion transistor, in the input first stage circuit of the signal input circuit, thereby eliminating power supply voltage dependence, and furthermore, the power supply ground is connected to high and low power supply voltages. This has the effect of preventing deterioration of the characteristics of the input inversion voltage due to noise.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention, FIG. 2 is a characteristic diagram showing the input inversion voltage and power supply voltage dependence of the circuit in FIG. 1, and FIG. 4 to 9 are circuit diagrams showing semiconductor integrated circuits according to second to seventh embodiments of the present invention, respectively, and FIG. 10 is a circuit showing a conventional circuit. 11 and 12 are all characteristic diagrams of FIG. 10. A, A'... Input signal, B, B'...
Output signal, TNII TM01 TM31 TNI
r Tl r TN3 ・・・・・・N-channel enhancement MOS transistor, TPI・TP2・
TPI ・TP2 ・T'p3 °------P
channel enhancer) MOS transistor, TDI
...N-channel Teflon MO8 transistor, P, P'...Contact in circuit, Tl,...
T4...MOS transistor.

Claims (1)

[Claims] A semiconductor integrated circuit characterized in that a constant current element is provided in series with a MOS transistor to which an input signal is applied to the gate.