JPH03207091A - Internal power supply voltage drop circuit - Google Patents
Internal power supply voltage drop circuitInfo
- Publication number
- JPH03207091A JPH03207091A JP2001871A JP187190A JPH03207091A JP H03207091 A JPH03207091 A JP H03207091A JP 2001871 A JP2001871 A JP 2001871A JP 187190 A JP187190 A JP 187190A JP H03207091 A JPH03207091 A JP H03207091A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- voltage
- supply voltage
- vcc
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 241001385733 Aesculus indica Species 0.000 description 1
- 108091034135 Vault RNA Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
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Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は内部電源電圧降圧回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an internal power supply voltage step-down circuit.
従来のこの種の回路について第3,4図を参照にして説
明する。第3図に示すPチャネルMOSトランジスタQ
)lのスレッショルド電圧ヲl VT,とすると、同ト
ランジスタはゲート及びドレインがVTNTに接続され
ンースが電源電圧■。。に接続してある為、VCCとv
4アとの差電位がlV?Plより大きいときオンし小さ
いときオフする。この為、第4図に示すように、■,つ
ぐ常にV。0に対して]■,1だけ低い電圧が得られる
。A conventional circuit of this type will be explained with reference to FIGS. 3 and 4. P-channel MOS transistor Q shown in FIG.
) The threshold voltage of l is VT, then the gate and drain of the transistor are connected to VTNT, and the ground is the power supply voltage. . Since it is connected to VCC and v
Is the potential difference with 4A lV? It turns on when it is larger than Pl and turns off when it is smaller. For this reason, as shown in Figure 4, ■, always V. 0] ■, a voltage lower by 1 is obtained.
上述した従来の内部電源電圧降圧回路は、VCCo値に
かかわらず常に■。。−I Vtp lを出力する。The conventional internal power supply voltage step-down circuit described above is always ■ regardless of the VCCo value. . -I Output Vtp l.
例えばvcc” 3 (:V’)のときl VTp l
= 0. 8 〔V)とするとV INT= 2.
2 1:V:lとナル。For example, when vcc" 3 (:V'), l VTp l
= 0. 8 [V], then V INT=2.
2 1:V:l and naru.
従来の回路を5〔■〕電源系のメモリ回路に用いた場合
を考える。通常、メモリが正常に動作する電源範囲は■
。。=3.5[:V〕〜7〔■〕程度である。従来回路
を用いた場合、VCC=4.3 CvE〜7.8CV)
のときV TNT = Vcc l VTp lによ
りV INT = 3.5〔■〕〜7〔■〕となり、高
電圧側の電圧レベルはメモリの高電圧側の動作範囲に接
近するが、逆に低電圧側の電圧レベルはさらに下がるた
め、メモリの動作範囲は狭くなる。この為、メモリの電
源電圧の保証範囲4.4 (:V)〜5.5[V:]に
対しての動作マージンが非常に小さくなるという欠点が
ある。Let us consider the case where the conventional circuit is used in the memory circuit of the 5 [■] power supply system. Normally, the power range in which memory operates normally is ■
. . = about 3.5[:V] to 7[■]. When using the conventional circuit, VCC = 4.3 CvE ~ 7.8CV)
When V TNT = Vcc l VTp l, V INT = 3.5 [■] to 7 [■], and the voltage level on the high voltage side approaches the operating range on the high voltage side of the memory, but conversely, the voltage level on the low voltage side As the voltage level on the side drops further, the operating range of the memory becomes narrower. Therefore, there is a drawback that the operating margin for the guaranteed range of memory power supply voltage of 4.4 (:V) to 5.5 [V:] becomes very small.
又、スタティックRAMの場合、データ保持モード時は
VCC= 3 [vl)に対してVIN?= 2. 2
[V]となり、メモリ内の微小リーク等の影響により
メモリセルデータの破壊が起きやすく紅り、特性を悪化
させてしまうという欠点がある。Also, in the case of static RAM, in data retention mode, VCC = 3 [vl] and VIN? = 2. 2
[V], which has the disadvantage that memory cell data is likely to be destroyed due to the influence of minute leaks in the memory, causing redness and deterioration of characteristics.
本発明の目的は、メモリ等に対する動作電源範囲を拡張
できる内部電源電圧降圧回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an internal power supply voltage step-down circuit that can extend the operating power supply range for a memory or the like.
本発明の内部電源電圧降圧回路は、第1の電源と第2の
電源間に直列に接続された第1及び第2の抵抗と、前記
第1及び第2の抵抗の接続点がゲートに接続されソース
・ドレイン路が前記第1の電源と節点に接続された第1
の一導電型MOSトランジスタと、前記節点と前記第2
の電源間に接続された第3の抵抗と、ゲートが前記節点
に接続されソース・ドレイン路が前記第1の電源と出力
端子間に接続された第2の一導電型MOSトランジスタ
と、ゲートが前記第1の電源に接続されソース・ドレイ
ン路が前記第1の電源と前記出力端子間に接続された逆
導電型MOSトランジスタとを有することを特徴とする
。The internal power supply voltage step-down circuit of the present invention includes first and second resistors connected in series between a first power supply and a second power supply, and a connection point between the first and second resistors connected to a gate. and a source-drain path connected to the first power source and the node.
one conductivity type MOS transistor, the node and the second conductivity type MOS transistor;
a second one-conductivity type MOS transistor having a gate connected to the node and a source-drain path connected between the first power source and the output terminal; The device is characterized in that it includes an opposite conductivity type MOS transistor connected to the first power source and having a source-drain path connected between the first power source and the output terminal.
?実施例〕 本発明について第1図及び第2図を参照して説明する。? Example〕 The present invention will be explained with reference to FIGS. 1 and 2.
第1図は本発明の一実施例を説明するための回路図、第
2図は第1図に示す回路の電圧特性である。R 1+
+ R l 2 , R 1sは高抵抗素子、Q.,,
Q,■はPチャネルMOSトランジスタ、Q1,はNチ
ャネルMOSトランジスタである。FIG. 1 is a circuit diagram for explaining one embodiment of the present invention, and FIG. 2 is a voltage characteristic of the circuit shown in FIG. R 1+
+ R l 2 and R 1s are high resistance elements, Q. ,,
Q and ■ are P-channel MOS transistors, and Q1 is an N-channel MOS transistor.
このような回路構成において、トランジスタQ l 3
のスレッショルド電圧をVAN、抵抗R,,,R,tの
抵抗{tlu+,R2、トランジスタQ1、のスレツシ
ョルド電圧をIVtplとし、所定電圧vIに対し、V
TPI :V+−lVtpl=R+ :Rzとなるよう
に設定する。In such a circuit configuration, the transistor Q l 3
Let the threshold voltage of VAN be VAN, the threshold voltage of resistor R, , R, t {tlu+, R2, transistor Q1, IVtpl, and for a predetermined voltage vI, V
Set so that TPI:V+-lVtpl=R+:Rz.
?ず、V cc < V 1の時、第1の節点N+、の
電位は、抵抗R + +とR1■の抵抗値によりV。。? First, when V cc < V 1, the potential of the first node N+ is V due to the resistance values of resistors R + + and R1■. .
×R + +Rx となり■。0と節点N11との差電位はV。。−■。。×R + +Rx Next ■. The difference potential between 0 and node N11 is V. . −■. .
×トランジスタQl+はオフし、第2の節点Nut!込
抗Rl3を介し、GNDと接続されている為に、GND
レベルとなる。第2の節点N12がGNDレベルである
からトランジスタQ+2はオンしてv1NTは電源レベ
ル、すなわち、v ,N, = v ccとなる。×Transistor Ql+ is turned off, and the second node Nut! Since it is connected to GND through the resistor Rl3, GND
level. Since the second node N12 is at the GND level, the transistor Q+2 is turned on and v1NT becomes the power supply level, that is, v , N, = v cc.
次に、■。。≧V1のとき、VCCと第1の節点N11
と?ランジスタQl1がオンする。抵抗Rl1の抵抗値
をトランジスタQl+のオン抵抗よりも十分高くすれば
、第2の節点N1■は電源レベルとなりトランジスタq
+iはオフする。Next, ■. . When ≧V1, VCC and the first node N11
and? Transistor Ql1 turns on. If the resistance value of the resistor Rl1 is made sufficiently higher than the on-resistance of the transistor Ql+, the second node N1■ becomes the power supply level and the transistor q
+i is turned off.
VINTの電位は、VINYが供給される回路に流れる
電流により、低下するがV。。とVrNアの差電位がV
TNよりも大きくなるとトランジスタQBがオンし、ま
たVTNよりも小さくなるとオフする為にVINTの電
位は常に■。C VTNに保たれる。The potential of VINT decreases to V due to the current flowing through the circuit to which VINY is supplied. . The potential difference between and VrNa is V
Transistor QB turns on when it becomes larger than TN, and turns off when it becomes smaller than VTN, so the potential of VINT is always ■. C maintained in VTN.
以上説明した様に、所定電圧■1に対し抵抗R1、,う
に設定すれば、V c c < V +のときはV I
NT = V cc *Vcc≧■1のときはV IN
T ” V CC V TNで表わされる電圧を得る
ことができる。As explained above, if the resistor R1 is set for a predetermined voltage 1, then when V c < V +, V I
NT = V cc *V IN when Vcc≧■1
A voltage expressed as T''VCCVTN can be obtained.
?発明の効果〕
以上説明した様に、本発明の内部電源電圧降圧回路は、
所定電圧V1に対し、抵抗R,,,R,■の抵定すれば
、Voo<V,のときVINT”VCe+ vcc≧v
1のときVJNア= V ec V IN?で表わさ
れる電圧が得られる。? Effects of the Invention As explained above, the internal power supply voltage step-down circuit of the present invention has the following effects:
If the resistors R, , R, ■ are applied to the predetermined voltage V1, when Voo<V, VINT”VCe+ vcc≧v
When 1, VJN a = V ec V IN? A voltage expressed as is obtained.
すなわち、電源電圧■。。が所定電圧■1よりも高い電
圧のときは、vTNだけ降圧し、v1よりも低い電圧の
ときは降圧しない。この為、例えばVTN” 0. 8
V , V + = 4. 3 Vとすると、メモリ
の動作電源範囲V cc ” 3. 5 V 〜7.
O Vを3.5V〜7.8Vと低電側の特性を悪化させ
ることなく拡張することができる。又、スタティックR
AMのデータ保持モード時もV cc = V rNt
= 3. O Vであるので特性を悪化させることは
ない。In other words, the power supply voltage■. . When the voltage is higher than the predetermined voltage ■1, the voltage is stepped down by vTN, and when the voltage is lower than v1, the voltage is not stepped down. For this reason, for example, VTN” 0.8
V, V+ = 4. 3 V, the memory operating power supply range V cc ”3.5 V to 7.
OV can be expanded from 3.5V to 7.8V without deteriorating the characteristics on the low voltage side. Also, static R
Even in AM data retention mode, V cc = V rNt
= 3. Since it is OV, the characteristics will not be deteriorated.
第1図は本発明の一実施例を説明するための回路図、第
2図は第1図に示す回路の電源電圧に対?る内部電源電
圧特性を示す図、第3図は従来の内部電源電圧降圧回路
を示す回路図、第4図は第3図に示す回路の電源電圧に
対する内部電源電圧特性を示す図である。
R + + , R l 2 r R + g・・・・
・・高抵抗素子、Qll, Ql2IQ3l・・・・・
・PチャネルMOSトランジスタ、Q t s・・・・
・・NチャネルMOSトランジスタs N++,N,■
・・・・・・接点、VINT・・・・・・内部電源電圧
、VCC・・・・・・電源電圧、GND・・・・・・接
地。FIG. 1 is a circuit diagram for explaining one embodiment of the present invention, and FIG. 2 is a diagram showing the power supply voltage of the circuit shown in FIG. 1. FIG. 3 is a circuit diagram showing a conventional internal power supply voltage step-down circuit, and FIG. 4 is a diagram showing internal power supply voltage characteristics with respect to the power supply voltage of the circuit shown in FIG. 3. R + + , R l 2 r R + g...
・・High resistance element, Qll, Ql2IQ3l・・・・
・P channel MOS transistor, Qts...
・・N channel MOS transistor s N++, N, ■
...Contact, VINT...Internal power supply voltage, VCC...Power supply voltage, GND...Grounding.
Claims (1)
圧レベルの出力電圧を発生する内部電源電圧降圧回路に
おいて、前記電源電圧が所定電圧以下の時に動作して出
力電圧を発生する第1の電圧発生手段と、前記第1の電
圧発生が動作していない時に出力電圧を供給する第2の
電圧発生手段とを有することを特徴とする内部電源電圧
降圧回路。 2、第1の電源と第2の電源間に直列に接続された第1
及び第2の抵抗と、前記第1及び第2の抵抗の接続点が
ゲートに接続されソース・ドレイン路が前記第1の電源
と節点に接続された第1の一導電型MOSトランジスタ
と、前記節点と前記第2の電源間に接続された第3の抵
抗と、ゲートが前記節点に接続されソース・ドレイン路
が前記第1の電源と出力端子間に接続された第2の一導
電型MOSトランジスタと、ゲートが前記第1の電源に
接続されソース・ドレイン路が前記第1の電源と前記出
力端子間に接続された逆導電型MOSトランジスタとを
有することを特徴とする内部電源電圧降圧回路。[Scope of Claims] 1. In an internal power supply voltage step-down circuit that receives a power supply voltage as input and generates an output voltage at a voltage level corresponding to the power supply voltage level, the circuit operates when the power supply voltage is below a predetermined voltage to increase the output voltage. 1. An internal power supply voltage step-down circuit comprising: a first voltage generation means for generating an output voltage; and a second voltage generation means for supplying an output voltage when the first voltage generation is not operating. 2. The first power supply connected in series between the first power supply and the second power supply
and a second resistor, a first one-conductivity type MOS transistor having a gate connected to a connection point of the first and second resistances and a source/drain path connected to the first power source and the node; a third resistor connected between the node and the second power source; and a second one-conductivity type MOS having a gate connected to the node and a source/drain path connected between the first power source and an output terminal. An internal power supply voltage step-down circuit comprising: a transistor; and a reverse conductivity type MOS transistor whose gate is connected to the first power supply and whose source-drain path is connected between the first power supply and the output terminal. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001871A JPH03207091A (en) | 1990-01-08 | 1990-01-08 | Internal power supply voltage drop circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001871A JPH03207091A (en) | 1990-01-08 | 1990-01-08 | Internal power supply voltage drop circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03207091A true JPH03207091A (en) | 1991-09-10 |
Family
ID=11513618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001871A Pending JPH03207091A (en) | 1990-01-08 | 1990-01-08 | Internal power supply voltage drop circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03207091A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5726945A (en) * | 1995-10-24 | 1998-03-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with reduced power consumption and thin film transistor used in semiconductor memory device for achieving reduction in power consumption |
US5894244A (en) * | 1995-11-16 | 1999-04-13 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor potential supply device and semiconductor memory apparatus using the same |
US5973548A (en) * | 1997-01-07 | 1999-10-26 | Mitsubishi Denki Kabushiki Kaisha | Internal supply voltage generating circuit for generating internal supply voltage less susceptible to variation of external supply voltage |
US6246272B1 (en) * | 1993-01-29 | 2001-06-12 | Ricoh Company, Ltd. | Power supply voltage detecting apparatus |
-
1990
- 1990-01-08 JP JP2001871A patent/JPH03207091A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6246272B1 (en) * | 1993-01-29 | 2001-06-12 | Ricoh Company, Ltd. | Power supply voltage detecting apparatus |
US5726945A (en) * | 1995-10-24 | 1998-03-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with reduced power consumption and thin film transistor used in semiconductor memory device for achieving reduction in power consumption |
US6218724B1 (en) | 1995-10-24 | 2001-04-17 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor used in semiconductor memory for achieving reduction in power consumption |
US5894244A (en) * | 1995-11-16 | 1999-04-13 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor potential supply device and semiconductor memory apparatus using the same |
US5973548A (en) * | 1997-01-07 | 1999-10-26 | Mitsubishi Denki Kabushiki Kaisha | Internal supply voltage generating circuit for generating internal supply voltage less susceptible to variation of external supply voltage |
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