JPH04114291A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH04114291A
JPH04114291A JP2234676A JP23467690A JPH04114291A JP H04114291 A JPH04114291 A JP H04114291A JP 2234676 A JP2234676 A JP 2234676A JP 23467690 A JP23467690 A JP 23467690A JP H04114291 A JPH04114291 A JP H04114291A
Authority
JP
Japan
Prior art keywords
channel mos
mos transistor
current
gate
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2234676A
Other languages
Japanese (ja)
Inventor
Atsuo Yamaguchi
敦男 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2234676A priority Critical patent/JPH04114291A/en
Publication of JPH04114291A publication Critical patent/JPH04114291A/en
Pending legal-status Critical Current

Links

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Microcomputers (AREA)

Abstract

PURPOSE:To decrease power supply voltage dependency by providing a current mirror circuit composed of a pair of MOS transistors to feed a constant current, which is generated at the second MOS transistor, back to the first MOS transistor. CONSTITUTION:The gate of a P-channel MOS transistor 7 is not grounded but connected to the gate of a P-channel MOS transistor 4, and the P-channel MOS transistors 4 and 7 compose the current mirror circuit and are operated to let the current having the same value as an N-channel MOS transistor 3 flow to N-channel MOS transistors 1 and 2. In this case, since a current value set by the N-channel MOS transistor 3 is normal small, the condition of gate length >> gate width is established. Thus, the power supply voltage dependency of the current flowing to the N-channel MOS transistors 1 and 2 is decreased, and the power supply voltage dependency of a current decided by the N-channel MOS transistor 3 is decreased.

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は、アナログ回路を有するマイクロコンピュー
タ等において、電源電圧の変動に対してアナログ回路の
特性の変動を抑えるようにした半導体集積回路に関する
ものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit that suppresses fluctuations in characteristics of the analog circuit in response to fluctuations in power supply voltage in a microcomputer or the like having an analog circuit. It is.

〔従来の技術１ アナログ回路は流すバイアス電流により特性が変動する
ので、バイアス電流と電源電圧の変動に対してできるだ
け変化しないようにすのがよい。[Prior Art 1] Since the characteristics of an analog circuit vary depending on the bias current flowing therethrough, it is preferable to prevent the characteristics from changing as much as possible with respect to variations in the bias current and power supply voltage.

第２図に従来のバイアス回路の一例を示す。FIG. 2 shows an example of a conventional bias circuit.

１と２は各々ゲート・ドレインが接続されたＮチャネル
ＭＯＳトランジスタで、直列に接続されるＮチャネルＭ
ｏＳトランジスタ１のソースは接地され、ＮチャネルＭ
ＯＳトランジスタ２のドレインはＮチャネルＭＯ３Ｉ−
ランジスタ３のゲートに接続され、ＮチャネルＭＯ３ト
ランジスタ３のソースは接地され、ドレインはカレント
ミラー回路を構成するＰチャネルＭＯＳトランジスタ４
のゲートおよびトレインと、ＰチャネルＭＯＳトランジ
スタ５のゲートに接続され、ＰチャネルＭＯＳトランジ
スタ５のドレインはアナログ回路（図示せず）へ接続さ
れる。また、ＰチャネルＭＯＳトランジスタ６のゲート
は接地され、ドレインはＮチャネルＭＯＳトランジスタ
２のトレインに接続される。1 and 2 are N-channel MOS transistors whose gates and drains are connected, and N-channel MOS transistors connected in series.
The source of oS transistor 1 is grounded, and the N-channel M
The drain of OS transistor 2 is N-channel MO3I-
The source of the N-channel MO3 transistor 3 is connected to the gate of the transistor 3, and the drain thereof is connected to the P-channel MOS transistor 4, which constitutes a current mirror circuit.
and the gate of P-channel MOS transistor 5, and the drain of P-channel MOS transistor 5 is connected to an analog circuit (not shown). Further, the gate of P-channel MOS transistor 6 is grounded, and the drain is connected to the train of N-channel MOS transistor 2.

ＰチャネルＭＯＳトランジスタ６は電源電圧Ｖ　ｃｃに
よって流れる電流が変化するが、ＮチャネルＭＯＳｌ−
ランジスタ１，２によって発生する電圧はＮチャネルＭ
ＯＳトランジスタ１，２がダイオード接続しているため
、ＮチャネルＭＯＳトランジスタ３のゲートに加わる電
圧は、電源電圧Ｖ　ｃｃの変動に対して少な（なる。こ
のＰチャネルＭＯＳトランジスタ３に流れる電流がカレ
ントミラー回路を構成するＰチャネルＭＯＳトランジス
タ４，５を介して、アナログ回路にバイアス電流として
供給される。The current flowing through the P-channel MOS transistor 6 changes depending on the power supply voltage Vcc, but the current flowing through the P-channel MOS transistor 6 changes depending on the power supply voltage Vcc.
The voltage generated by transistors 1 and 2 is N-channel M
Since OS transistors 1 and 2 are diode-connected, the voltage applied to the gate of N-channel MOS transistor 3 is small with respect to fluctuations in power supply voltage Vcc.The current flowing through P-channel MOS transistor 3 is current mirrored. It is supplied as a bias current to the analog circuit through P-channel MOS transistors 4 and 5 forming the circuit.

［発明が解決しようとする課題１ 以上のような構成にすることにより、電源電圧Ｖ　ｅＣ
の変動に対するバイアスの電流の変動をいく分かは減ら
すことができるが、元の電流を決めるＰチャネルＭＯＳ
トランジスタ６の電流が電源電圧Ｖ　ｃｃの影響を直接
受けるため、アナログ回路へのバイアス電流の電源電圧
依存性を充分に減らすことができないという問題点があ
った。。[Problem to be solved by the invention 1 By having the above configuration, the power supply voltage V eC
It is possible to reduce some of the bias current variation due to variations in P-channel MOS, which determines the original current.
Since the current of the transistor 6 is directly affected by the power supply voltage Vcc, there is a problem that the dependence of the bias current to the analog circuit on the power supply voltage cannot be sufficiently reduced. .

この発明は、上記の問題点を解決するためになされたも
ので、電源電圧依存性の小さい半導体集積回路を提供す
ることを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor integrated circuit with low dependence on power supply voltage.

〔課題を解決するための手段］ この発明にかかる半導体集積回路は、ドレイン・ゲート
間を接続した第１のＭＯＳトランジスタを複数個直列に
接続し、そこに発生する電圧を電流値を設定するための
ゲート長がゲート幅と比較して極めて大きい第２のＭＯ
Ｓトランジスタのゲートに印加することによって構成さ
れる定電流源において、第２のＭＯＳトランジスタで発
生した定電流を、第１のＭＯＳトランジスタにフィード
バックする一対のＭＯＳトランジスタで構成されるカレ
ントミラー回路を設けたものである。[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention connects a plurality of first MOS transistors in series with each other having their drains and gates connected, and sets the voltage generated therein to a current value. A second MO whose gate length is extremely large compared to the gate width.
In the constant current source configured by applying it to the gate of the S transistor, a current mirror circuit configured with a pair of MOS transistors is provided that feeds back the constant current generated in the second MOS transistor to the first MOS transistor. It is something that

［作用］ この発明においては、電源電圧が直接ソース・ゲート間
に加わる素子がなくなるので、電源電圧の変動に対する
バイアス電流の変動を抑えることができる。[Operation] In the present invention, since there is no element to which the power supply voltage is directly applied between the source and the gate, it is possible to suppress fluctuations in the bias current due to fluctuations in the power supply voltage.

［実施例］ 第１図にこの発明の一実施例の回路図を示す。[Example] FIG. 1 shows a circuit diagram of an embodiment of the present invention.

１〜５は従来例と同じである。従来例におけるＰチャネ
ルＭＯＳトランジスタ６はなく、代りにＰチャネルＭＯ
Ｓトランジスタフが接続されている。ただし、Ｐチャネ
ルＭＯＳトランジスタ７のゲートは接地ではなく、Ｐチ
ャネルＭＯＳｌ−ランジスタ４のゲートに接続されてお
り、ＰチャネルＭＯＳトランジスタ４，７はカレントミ
ラー回路を構成しており、ＮチャネルＭＯＳトランジス
タ３の電流と同じ値の電流をＮチャネルＭＯＳトランジ
スタ１，２に流すように作用する。ＮチャネルＭＯＳト
ランジスタ３で設定する電流値は、通常率さい値となる
ため、ゲート長）ゲート幅とすることが必要である。特
に、ＮチャネルＭＯＳトランジスタ１，２に流れる電流
と同程度の値とするためには、ＮチャネルＭＯＳトラン
ジスタ１゜２に比ベゲート長）ゲート幅とすることが必
要である。また、ＰチャネルＭＯＳトランジスタ４゜５
．７を同一サイズとして設計すれば、それぞれに等しい
電流を流すことができる。1 to 5 are the same as the conventional example. There is no P-channel MOS transistor 6 in the conventional example, but a P-channel MOS transistor 6 is used instead.
S transistor is connected. However, the gate of P-channel MOS transistor 7 is not connected to the ground, but is connected to the gate of P-channel MOS transistor 4, and P-channel MOS transistors 4 and 7 form a current mirror circuit, and N-channel MOS transistor 3 It acts so that a current having the same value as the current flows through N channel MOS transistors 1 and 2. Since the current value set in the N-channel MOS transistor 3 is usually a small value, it is necessary to set the current value to a value equal to (gate length) (gate width). In particular, in order to obtain a current comparable to that of the N-channel MOS transistors 1 and 2, it is necessary to set the gate width to the N-channel MOS transistor 1.degree.2 (gate length). In addition, a P channel MOS transistor 4°5
．． If 7 are designed to have the same size, the same current can be passed through each of them.

以上のように構成したので、ＮチャネルＭＯＳトランジ
スタ２，１に流れる電流の電源電圧依存性が減りＮチャ
ネルＭＯＳトランジスタ３で決定される電流の電源電圧
依存性が減る。With the above configuration, the dependence of the current flowing through N-channel MOS transistors 2 and 1 on the power supply voltage is reduced, and the dependence of the current determined by N-channel MOS transistor 3 on the power supply voltage is reduced.

［発明の効果］ この発明は以上述べたように、ドレイン・ゲート間を接
続した第１のＭＯＳトランジスタを複数個直列に接続し
、そこに発生する電圧を電流値を設定するためのゲート
長がゲート幅と比較して極めて大きい第２のＭＯ３Ｉ−
ランジスタのゲートに印加することによって構成される
定電流源において、第２のＭＯ３Ｉ−ランジスタで発生
した定電流を、第１のＭＯＳトランジスタにフィードバ
ックする一対のＭＯ３Ｉ−ランジスタで構成されるカレ
ントミラー回路を設けたので、電源電圧依存性を減らす
ことができる。[Effects of the Invention] As described above, the present invention connects a plurality of first MOS transistors in series with each other having their drains and gates connected, and has a gate length for setting the current value of the voltage generated therein. The second MO3I- which is extremely large compared to the gate width
In a constant current source configured by applying it to the gate of a transistor, a current mirror circuit consisting of a pair of MO3I transistors feeds back the constant current generated in the second MO3I transistor to the first MOS transistor. Since this is provided, dependence on power supply voltage can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例を示す回路図、第２図は従
来例の回路図である。 図において、１，２．３はＮチャネルＭＯＳトランジス
タ、４，５．７はＰチャネルＭＯＳｌ−ランジスタ、 Ｖ　ｃｃは電源電圧である。 なお、 各図中の同一符号は同一または相当部分を示す。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. In the figure, 1 and 2.3 are N-channel MOS transistors, 4 and 5.7 are P-channel MOS transistors, and Vcc is a power supply voltage. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] ドレイン・ゲート間を接続した第１のＭＯＳトランジス
タを複数個直列に接続し、そこに発生する電圧を電流値
を設定するためのゲート長がゲート幅と比較して極めて
大きい第２のＭＯＳトランジスタのゲートに印加するこ
とによって構成される定電流源において、前記第２のＭ
ＯＳトランジスタで発生した定電流を、前記第１のＭＯ
Ｓトランジスタにフィードバックする一対のＭＯＳトラ
ンジスタで構成されるカレントミラー回路を設けたこと
を特徴とする半導体集積回路。A plurality of first MOS transistors connected between drains and gates are connected in series, and a second MOS transistor whose gate length is extremely large compared to the gate width is used to set the current value of the voltage generated there. In the constant current source configured by applying voltage to the gate, the second M
The constant current generated by the OS transistor is transferred to the first MO
A semiconductor integrated circuit comprising a current mirror circuit composed of a pair of MOS transistors that feeds back to an S transistor.
JP2234676A 1990-09-04 1990-09-04 Semiconductor integrated circuit Pending JPH04114291A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2234676A JPH04114291A (en) 1990-09-04 1990-09-04 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2234676A JPH04114291A (en) 1990-09-04 1990-09-04 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH04114291A true JPH04114291A (en) 1992-04-15

Family

ID=16974720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2234676A Pending JPH04114291A (en) 1990-09-04 1990-09-04 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH04114291A (en)

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