JPH086653A - Reference voltage generating circuit - Google Patents

Abstract

PURPOSE:To stably generate a constant voltage without depending upon variance in threshold voltage between MOS transistors(TR). CONSTITUTION:A load MOS TR and a driving MOS TR are composed of the same conduction type and the same operation type, i.e., N channel depletion type MOS TRs ND11 and ND12; and an output terminal TOUT is connected to the gate of the load MOS TR, a specific offset voltage Voff is applied to the source of the driving MOIS TR ND12, and the gate of the driving MOIS TR ND12 is connected to a ground GND line. Consequently, the constant voltage can stably be generated without depending upon the variance in threshold voltage between the MOB TRs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit which is composed of MOS transistors and outputs a constant voltage.

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram showing a basic configuration of a conventional reference voltage generating circuit. This circuit includes a depletion type NMOS transistor ND1 for load and an enhancement type NMOS transistor NE1 for driving.
Is connected in series between the power supply voltage V _CC and the ground GND, and has an input terminal T _{IN which} is a connection point between the gates of both transistors ND1 and NE1 and a connection point between the source of the transistor ND1 and the drain of the transistor NE1. Is connected to an output terminal T _OUT .

The voltage generated by this circuit is Vr, and this voltage Vr is set as shown in FIG.

FIG. 7 is a diagram showing the voltage-current characteristics of the circuit of FIG. In FIG. 7, the horizontal axis represents voltage and the vertical axis represents current. In the figure, the curve indicated by A indicates the characteristics of the load transistor, and the curve indicated by B indicates the characteristics of the driving transistor. Then, the constant voltage Vr is set from the intersection X of the curves A and B.

[0005]

However, in the case of the circuit configuration described above, the threshold voltage of the enhancement type transistor and the threshold voltage of the depletion type transistor are controlled separately in the normal IC manufacturing process. Therefore, some variation is unavoidable. As a result, even if each type of transistor is manufactured within the allowable standard, the voltage Vr varies in the range from Vr1 to Vr2 as shown in FIG.

Incidentally, in FIG. 8, a curve A shown by a solid line
1 and B1 show the characteristics when the threshold voltage becomes lower than the design value, that is, when the drain-source current Ids is large, and the curves A2 and B2 shown by broken lines have the threshold voltage higher than the design value. In other words, the characteristics are shown when the drain-source current Ids is small. As shown in FIG. 9, a load MOS transistor and a drive MOS
Since the transistors and the transistors vary without correlation, in the worst case, the voltage Vr varies from Vr1 to Vr as described above.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a reference voltage generating circuit capable of stably generating a constant voltage without depending on variations in threshold voltage of MOS transistors. To provide.

[0008]

To achieve the above object, a load MOS transistor and a drive MOS transistor are connected in series between a first potential and a second potential of the present invention, and this connection is made. In a reference voltage generating circuit that outputs a constant voltage from a point, the load MOS transistor and the drive MOS transistor are composed of MOS transistors of the same conductivity type and the same operation type, and the gate of the drive MOS transistor is at a constant potential. An offset voltage, which is connected and is offset by a constant voltage with respect to the second potential, is supplied to the source.

Further, in the reference voltage generating circuit of the present invention, the load MOS transistor and the drive MO transistor are provided.
The operation type of the S transistor is a depletion type, the gate of the load MOS transistor is connected to the connection point, and the gate of the drive MOS transistor is connected to the second potential.

In the reference voltage generating circuit of the present invention, the offset voltage is realized by the forward voltage of the PN junction.

[0011]

According to the present invention, by applying a predetermined offset voltage to the source of the driving MOS transistor, even if the threshold voltage of the transistor varies from the design value, the load MOS transistor and the driving MOS transistor As with transistors, variations in generated voltage are sufficiently small for practical use.

[0012]

1 is a circuit diagram showing a first embodiment of a reference voltage generating circuit according to the present invention. In FIG. 1, V _CC is a power supply voltage, GND is ground, Voff is an offset voltage, Vr is a generated (output) voltage, ND11 is a depletion type NMOS transistor for load, and ND12 is a depletion type NMOS transistor for driving. There is. That is, in the circuit of this embodiment, both the load MOS transistor and the drive MOS transistor are composed of the same conductivity type and the same operation type, that is, N-channel type and depletion type MOS transistors.

Depletion type NMOS transistor for load (hereinafter referred to as load MOS transistor) ND
The drain of 11 is connected to the supply line of the power supply voltage V _CC , and the source and the gate of the depletion type NM for driving.
It is connected to the drain of an OS transistor (hereinafter referred to as a driving MOS transistor) ND12, and an output terminal T _OUT is constituted by these connection points. Driving MOS
The gate of the transistor ND12 is connected to the ground GND line, and the source thereof is supplied with an offset voltage Voff of 0.2 to 0.6V. Offset voltage V of this source
Off can be given by the forward voltage of the PN junction, for example.

FIG. 2 is a diagram showing the voltage-current characteristics of the circuit of FIG. In FIG. 2, the horizontal axis represents voltage and the vertical axis represents current. Further, in the figure, the curves indicated by A11 and A12 indicate the characteristics of the load MOS transistor, the curves indicated by B11 and B12 indicate the characteristics of the driving MOS transistor, and the curves A11 and B11 indicated by the solid line indicate the threshold voltage. Is lower than the design value, that is, the drain-source current Ids is large, and the curves A12 and B12 shown by broken lines indicate that the threshold voltage is higher than the set value, that is, the drain-source. The characteristic is shown when the current Ids is small.

The generated voltage Vr is set at the intersections X11, X of the characteristic curves A11, A12 of the load MOS transistor ND11 and the characteristic curves B11, B12 of the driving transistor ND12.
Although it can be set from 12, the offset voltage Voff is applied to the source of the driving MOS transistor ND12 in the present embodiment as shown in FIG. 2, so that the threshold voltage becomes lower than the design value. In this case, the intersection X11 of the characteristic curves of both transistors and the intersection X12 of the characteristic curves of both transistors when the threshold voltage becomes lower than the design value are formed near the same voltage point. That is, drive M
By applying a predetermined offset voltage Voff to the source of the OS transistor ND12, even if the threshold voltage of the transistor varies from the design value as shown by the broken line in FIG. 2, the load MOS transistor ND11 and the drive M
Since the OS transistor ND12 has the same variation, that is, the increase and decrease of the drain-source current Ids are synchronized, the variation of the voltage Vr corresponding to the intersection is sufficiently small in practical use.

[0016] Figure 3 is a case which does not give a case of giving an offset voltage of 0.5V to the source of the driving transistor by using a similar circuit to the circuit of FIG. 1, the power supply voltage V _CC
It is a figure which shows the actual measurement result when changing with 0.5V space | interval between 3.5V-5.5V. In the figure, the curve indicated by B21 is the characteristic curve of the driving MOS transistor when the offset voltage Voff is applied, and the curve B22 is the characteristic curve of the driving MOS transistor when the offset voltage Voff is not applied. The curves indicated by A21 and A22 are for load MO.
The characteristic curve of the S transistor is shown. As shown in FIG. 3, even in actual measurement, the driving MOS transistor ND
By applying a predetermined offset voltage Voff to the 12 sources, even if the threshold voltage of the transistor varies from the design value, the variation of the voltage Vr corresponding to the intersection is greater than that when the offset voltage Voff is not provided. Small enough.

As described above, according to this embodiment,
The load MOS transistor and the drive MOS transistor have the same conductivity type and the same operation type, that is, N-channel, depletion type MOS transistors ND11, N.
D12, the gate of the load MOS transistor is connected to the output terminal T _OUT , the source of the drive MOS transistor ND12 is supplied with a predetermined offset voltage Voff, and the gate of the drive MOS transistor ND12 is connected to the ground GND line. Therefore, there is an advantage that a constant voltage can be stably generated without depending on the variation in the threshold voltage of the MOS transistor.

In this embodiment, the gate of the driving MOS transistor is set to the ground potential and the source offset voltage Voff is given by the forward voltage of the PN junction. This is the case in the case of the combination of the depletion type NMOS transistors. This is because the voltage that can be easily realized is used in the manufacturing process of the IC. Therefore, the amount of change in the drain-source current Ids of the load MOS transistor and the amount of change in the drain-source current Ids of the drive MOS transistor corresponding to the variation in the threshold voltage are as shown in FIGS. If the size of the transistor, the gate voltage, and the offset voltage Voff are selected so as to be almost equal at the position (Vr) of the intersection of each voltage-current curve,
It goes without saying that the present invention can be applied to a combination of enhancement type MOS transistors.

In this embodiment, the case of using the N-channel depletion type MOS transistor has been described as an example, but the present invention can be similarly applied to the P-channel depletion type and further to the P-channel and N-channel enhancement type. Needless to say.

FIG. 4 is a circuit diagram showing a second embodiment of the reference voltage generating circuit according to the present invention. This embodiment is different from the first embodiment described above in that a depletion type NMOS is used as a load and drive MOS transistor.
Instead of using the transistors ND11 and ND12, enhancement type NMOS transistors NE11 and NE are used.
I used 12. In this case, the gate of the enhancement type NMOS transistor NE11 for load is connected to the supply line of the power supply voltage V _CC , not to the output terminal T _OUT , and the gate of the enhancement type NMOS transistor NE12 for driving is not the ground GND but the constant potential. C
Connected to V.

FIG. 5 is a diagram showing the voltage-current characteristics of the circuit of FIG. Also in FIG. 5, the horizontal axis represents voltage and the vertical axis represents current. In the figure, the curves indicated by A31 and A32 are the characteristics of the load MOS transistor, and the curves indicated by B31 and B32 are the driving M.
Curves A31 and B31 shown by the solid line show the characteristics of the OS transistor, and show the characteristics when the threshold voltage becomes lower than the design value, that is, when the drain-source current Ids is large, and the curve A32 shown by the broken line. , B32 when the threshold voltage becomes higher than the designed value, that is, the drain-
The characteristic is shown when the source current Ids is small.

As shown in FIG. 5, when the enhancement type transistor is used as in the present embodiment, even when the threshold voltage of the transistor varies from the design value, the depletion type transistor described above is used. Similarly, the variation of the voltage Vr at the intersection is sufficiently smaller than that when the offset voltage Voff is not applied. As described above, also in this embodiment, the same effect as that of the above-described first embodiment, that is, since the load MOS transistor and the drive MOS transistor can be manufactured in the same manufacturing process, the drive capability ratio of both (Ratio of operating impedance)
Is less likely to vary and the generated voltage Vr is stable.

[0023]

As described above, according to the reference voltage generating circuit of the present invention, a constant voltage can be stably generated without depending on the variation of the threshold voltage of the MOS transistor.

[Brief description of drawings]

FIG. 1 is a first circuit of a reference voltage generating circuit according to the present invention.
3 is a circuit diagram showing an embodiment of FIG.

FIG. 2 is a diagram showing voltage-current characteristics of the circuit of FIG.

FIG. 3 is a diagram showing actual measurement results using a circuit similar to that of FIG. 1 with and without applying an offset voltage of 0.5 V to the source of a driving transistor.

FIG. 4 shows a second reference voltage generating circuit according to the present invention.
3 is a circuit diagram showing an embodiment of FIG.

5 is a diagram showing voltage-current characteristics of the circuit of FIG.

FIG. 6 is a circuit diagram showing a configuration example of a conventional reference voltage generating circuit.

7 is a diagram showing voltage-current characteristics of the circuit of FIG.

FIG. 8 is a voltage-current characteristic diagram for explaining problems of the circuit of FIG.

[Explanation of symbols]

V _CC ... Power supply voltage GND ... Ground Voff ... Offset voltage Vr ... Generation voltage ND11 ... Depletion type NMOS transistor ND12 for load ... Depletion type NMOS transistor NE11 ... Drive enhancement type NMOS transistor NE12 ... Enhancement type for drive NMOS transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/822 29/78 H03K 19/00 A

Claims (3)

[Claims] 1. A reference voltage generating circuit in which a load MOS transistor and a drive MOS transistor are connected in series between a first potential and a second potential, and a constant voltage is output from this connection point. The load MOS transistor and the drive MOS transistor are composed of MOS transistors of the same conductivity type and the same operation type, the gate of the drive MOS transistor is connected to a constant potential, and the source is connected to the second potential. Reference voltage generation circuit that is supplied with an offset voltage offset by a constant voltage. 2. The operation type of the load MOS transistor and the drive MOS transistor is a depletion type, the gate of the load MOS transistor is connected to the connection point, and the gate of the drive MOS transistor is at a second potential. The reference voltage generating circuit according to claim 1, which is connected to the. 3. The reference voltage generating circuit according to claim 1, wherein the offset voltage is a forward voltage of a PN junction.