JPH06275686A - Method and device for manufacturing semiconductor device - Google Patents

Method and device for manufacturing semiconductor device

Info

Publication number
JPH06275686A
JPH06275686A JP6006693A JP6006693A JPH06275686A JP H06275686 A JPH06275686 A JP H06275686A JP 6006693 A JP6006693 A JP 6006693A JP 6006693 A JP6006693 A JP 6006693A JP H06275686 A JPH06275686 A JP H06275686A
Authority
JP
Japan
Prior art keywords
semiconductor
defective
semiconductor element
semiconductor wafer
marked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6006693A
Other languages
Japanese (ja)
Inventor
Motoki Okabe
基樹 岡部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP6006693A priority Critical patent/JPH06275686A/en
Publication of JPH06275686A publication Critical patent/JPH06275686A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To solve a trouble, which is accompanied by the good or bad of the marking of a defect mark put on a characteristic defective of a plurality of semiconductor elements formed on a semiconductor wafer. CONSTITUTION:A characteristic inspection of a plurality of semiconductor elements 2 formed on a semiconductor wafer 1 is made in order, a defect mark is marked on a semiconductor element 2 having a characteristic failure and positional information on the marked semiconductor element 2 on the wafer 1 is made to store in a storage element 9. The elements 2 on the wafer 1 are imaged by a camera 11, positional information, which is obtained from the image, on the element 2 having the defect mark on the wafer 1 and the positional information, which is read out from the element 9, on the element 2 to be marked are compared with each other by a comparison decision circuit 13 and a good or bad decision on the marking is made by whether the contents of both information coincide with each other or not. By this decision, a control to send the wafer 1 having a non-defective mark to the following process is executed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体ウェーハに複数
形成された半導体素子の特性検査工程における製造方法
と製造装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing method and a manufacturing apparatus in a characteristic inspection process for a plurality of semiconductor elements formed on a semiconductor wafer.

【0002】[0002]

【従来の技術】1枚の半導体ウェーハに複数形成された
半導体素子の特性検査工程においては、特性不良と判定
された半導体素子上にインクや傷などの不良マークがマ
ーキングされる。半導体素子の特性検査が終了した半導
体ウェーハは、個々の半導体素子に分割され、不良マー
クの無い良品の半導体素子がリードフレームなどにマウ
ントされる。
2. Description of the Related Art In a characteristic inspection process for a plurality of semiconductor elements formed on one semiconductor wafer, defective marks such as ink and scratches are marked on the semiconductor elements determined to have defective characteristics. The semiconductor wafer on which the characteristic inspection of the semiconductor element has been completed is divided into individual semiconductor elements, and a good semiconductor element having no defective mark is mounted on a lead frame or the like.

【0003】半導体ウェーハの各半導体素子の特性検査
は、図3(a)に示すような特性検査装置(6)とマー
キング装置(7)を使って行われる。複数の半導体ウェ
ーハ(1)を多段に収納するマガジン(4)から1枚の半
導体ウェーハ(1)が水平な特性検査用テーブル(5)上
に供給される。図3(b)に示すように、半導体ウェー
ハ(1)には複数の半導体素子(2)が格子状の配列で形
成されている。
The characteristic inspection of each semiconductor element of the semiconductor wafer is performed by using a characteristic inspection device (6) and a marking device (7) as shown in FIG. 3 (a). One semiconductor wafer (1) is supplied onto a horizontal characteristic inspection table (5) from a magazine (4) that stores a plurality of semiconductor wafers (1) in multiple stages. As shown in FIG. 3B, the semiconductor wafer (1) has a plurality of semiconductor elements (2) arranged in a grid pattern.

【0004】テーブル(5)の上方に特性検査装置(6)
とマーキング装置(7)が配置され、テーブル(5)上に
半導体ウェーハ(1)が供給されると、特性検査装置
(6)が半導体ウェーハ(1)の複数の半導体素子(2)
の特性検査を順に行う。この特性検査の進行に並行し
て、特性不良の半導体素子(2)上に不良マーク(3)が
マーキングされる。
A characteristic inspection device (6) above the table (5)
When the semiconductor wafer (1) is supplied on the table (5) with the marking device (7) arranged, the characteristic inspection device (6) causes the plurality of semiconductor elements (2) of the semiconductor wafer (1).
The characteristic inspections of are sequentially performed. In parallel with the progress of the characteristic inspection, a defective mark (3) is marked on the semiconductor element (2) having a defective characteristic.

【0005】例えば、1つの半導体素子(2)の検査結
果が不良と判定されると、特性検査装置(5)からマー
キング装置(7)にマーキング指令信号が出力されて、
マーキング装置(7)が特性不良と判定された半導体素
子(2)上に不良マーク(3)をマーキングする。不良マ
ーク(3)は半導体ウェーハ(1)上に塗布されたドット
状のインクや、半導体ウェーハ(1)の上面に付けられ
た傷などである。
For example, when the inspection result of one semiconductor element (2) is determined to be defective, a marking command signal is output from the characteristic inspection device (5) to the marking device (7),
A marking device (7) marks a defective mark (3) on a semiconductor element (2) determined to have a defective characteristic. The defective mark (3) is, for example, dot-shaped ink applied on the semiconductor wafer (1) or scratches on the upper surface of the semiconductor wafer (1).

【0006】半導体ウェーハ(1)は特性検査が終了す
ると、テーブル(5)から別のマガジン(8)に収納され
る。マガジン(8)に収納された特性検査済みの半導体
ウェーハ(1)は、後工程の例えばマウント工程に送ら
れて、個々の半導体素子(2)に分割される。分割され
た個々の半導体素子(2)は、カメラで撮像された画像
から不良マーク(3)の有無が検知されて、特性の良品
と不良品に分別され、良品だけがリードフレームなどに
マウントされて半導体装置が製造される。
After the characteristic inspection is completed, the semiconductor wafer (1) is stored in another magazine (8) from the table (5). The characteristic-tested semiconductor wafer (1) housed in the magazine (8) is sent to a later step, for example, a mounting step, and divided into individual semiconductor elements (2). For each divided semiconductor element (2), the presence or absence of a defective mark (3) is detected from the image captured by the camera, and it is sorted into good and defective products with characteristics and only good products are mounted on a lead frame or the like. And a semiconductor device is manufactured.

【0007】[0007]

【発明が解決しようとする課題】半導体ウェーハの半導
体素子上にマーキングされる不良マークは、後工程の画
像処理で容易に認識される形状、色彩、サイズの鮮明な
ものであるが、マーキング装置の動作不良やマーキング
条件によって不良マークが不鮮明となり、マウント工程
の画像処理で正確に検知できなくなることがある。
The defective mark to be marked on the semiconductor element of the semiconductor wafer has a clear shape, color and size which can be easily recognized in the image processing in the subsequent process. A defective mark may become unclear due to a malfunction or marking conditions and may not be accurately detected by image processing in the mounting process.

【0008】例えば、マーキング装置が、特性不良の半
導体素子上に定量のインクを塗布してマーキングするイ
ンクノズルを備えたものの場合、インクノズルからのイ
ンクの出方の良不良で半導体素子上にマーキングされる
インクの量や形態が変動し、インクの不良マークが掠れ
た不鮮明なものになることがある。また、マーキング装
置が、特性不良の半導体素子上にピンで傷を付けるもの
の場合、ピンの曲がりや磨耗で半導体素子上に付けられ
る傷の深さ、サイズが小さくなり、傷の不良マークが不
鮮明になることがある。
For example, in the case where the marking device is provided with an ink nozzle for applying a fixed amount of ink on a semiconductor element having a poor characteristic to perform marking, marking is performed on the semiconductor element due to a good or poor way of ejecting the ink from the ink nozzle. The amount and form of the generated ink may fluctuate, and the defective mark of the ink may be blurred and unclear. If the marking device scratches the semiconductor element with defective characteristics with a pin, the depth and size of the scratch on the semiconductor element will be reduced due to bending or wear of the pin, making the defective mark of the scratch unclear. May be.

【0009】このような不鮮明な不良マークは、後工程
で半導体ウェーハから分割された個々の半導体素子の画
像処理時に認識されないことがある。その結果、不鮮明
な不良マークがマーキングされた特性不良の半導体素子
が、特性良品の半導体素子と誤認されてリードフレーム
などにマウントされる不具合が発生していた。また、か
かる不鮮明な不良マークのマーキングは、複数の半導体
ウェーハにおいて連続的に発生することが多くて、上記
不具合が複数の半導体ウェーハで連続的に発生し、半導
体装置の製造歩留まりを悪くする原因になっている。
Such an unclear defect mark may not be recognized during image processing of individual semiconductor devices divided from a semiconductor wafer in a later process. As a result, there has been a problem that a semiconductor element having a poor characteristic with an unclear defective mark is mistakenly recognized as a semiconductor element having a good characteristic and mounted on a lead frame or the like. Further, such unclear marking of defective marks often occurs continuously in a plurality of semiconductor wafers, and the above-mentioned defect occurs continuously in a plurality of semiconductor wafers, which is a cause of deteriorating the manufacturing yield of semiconductor devices. Has become.

【0010】本発明の目的は、半導体ウェーハの半導体
素子にマーキングされる不良マークの出来の良不良が原
因する不具合を解消した半導体装置の製造方法と製造装
置を提供することにある。
An object of the present invention is to provide a method and an apparatus for manufacturing a semiconductor device, which eliminates the problems caused by the quality of defective marks to be marked on semiconductor elements of a semiconductor wafer.

【0011】[0011]

【課題を解決するための手段】本発明は、半導体ウェー
ハに複数形成された半導体素子の特性検査を順に行い、
特性不良と判定された半導体素子上に不良マークをマー
キングすると共に、不良マークをマーキングした半導体
素子の半導体ウェーハにおける位置情報を記憶素子に記
憶させる特性検査工程の後工程に、特性検査後の半導体
ウェーハの各半導体素子をカメラで撮像し、その画像処
理から半導体素子上の不良マークの有無を検出して、不
良マーク有りと認識された半導体素子の半導体ウェーハ
における位置情報と、前記記憶素子から読み出した被マ
ーキング半導体素子の位置情報を比較する不良マーク認
識工程を設けることにより、上記目的を達成するもので
ある。
According to the present invention, a plurality of semiconductor elements formed on a semiconductor wafer are sequentially inspected for characteristics,
A semiconductor wafer after the characteristic inspection is performed in a step subsequent to the characteristic inspection step in which a defective mark is marked on the semiconductor element determined to have the characteristic defect and the position information in the semiconductor wafer of the semiconductor element with the defective mark is stored in a storage element. Each semiconductor element is imaged with a camera, the presence or absence of a defective mark on the semiconductor element is detected from the image processing, and the position information on the semiconductor wafer of the semiconductor element recognized as having a defective mark and the position information are read from the storage element. The above object is achieved by providing a defective mark recognition step of comparing the positional information of the semiconductor elements to be marked.

【0012】また、本発明は、半導体ウェーハに複数形
成された半導体素子の特性検査を順に行い、特性不良と
判定された半導体素子上に不良マークをマーキングする
と共に、不良マークをマーキングした半導体素子の半導
体ウェーハにおける位置情報を記憶素子に記憶させる特
性検査装置と、特性検査後の半導体ウェーハの各半導体
素子をカメラで撮像し、その画像処理から半導体素子上
の不良マークの有無を検出する画像認識装置と、画像認
識装置で不良マーク有りと認識された半導体素子の半導
体ウェーハにおける位置情報と、前記特性検査装置の記
憶素子から読み出した被マーキング半導体素子の位置情
報を比較して、半導体素子の不良マークの形態の良否を
判定する比較判定回路とを具備した半導体装置の製造装
置にて、上記目的を達成する。
Further, according to the present invention, a plurality of semiconductor elements formed on a semiconductor wafer are sequentially inspected for characteristics, and a defective mark is marked on a semiconductor element determined to have a defective characteristic. A characteristic inspection device that stores position information on a semiconductor wafer in a storage element, and an image recognition device that images each semiconductor element of the semiconductor wafer after the characteristic inspection with a camera and detects the presence or absence of a defective mark on the semiconductor element from the image processing. And the position information of the semiconductor element, which is recognized by the image recognition apparatus as having a defective mark on the semiconductor wafer, and the position information of the marked semiconductor element read from the storage element of the characteristic inspection apparatus, are compared to obtain a defective mark of the semiconductor element. In a semiconductor device manufacturing apparatus including a comparison / determination circuit for determining the quality of Accomplish.

【0013】[0013]

【作用】半導体ウェーハの半導体素子の特性検査時に行
われた被マーキング半導体素子の半導体ウェーハにおけ
る位置情報と、特性検査後の半導体素子画像から不良マ
ーク有りと認識された半導体素子の半導体ウェーハにお
ける位置情報を比較して、2つの位置情報が一致する
と、不良マークが良好にマーキングされていると判定で
きる。また、被マーキング半導体素子の位置情報と不良
マーク認識半導体素子の位置情報が一致しない場合は、
不良マークが画像処理で認識できない程度に不鮮明であ
って、マーキング装置の動作不良発生などが予測でき
る。
Function: Position information on the semiconductor wafer of the semiconductor element to be marked, which is performed during the characteristic inspection of the semiconductor element of the semiconductor wafer, and position information on the semiconductor wafer of the semiconductor element recognized as having a defective mark from the semiconductor element image after the characteristic inspection. If the two pieces of position information match with each other, it can be determined that the defective mark is properly marked. If the position information of the marked semiconductor device and the position information of the defective mark recognition semiconductor device do not match,
The defective mark is so unclear that it cannot be recognized by image processing, and the occurrence of malfunction of the marking device can be predicted.

【0014】[0014]

【実施例】以下、本発明を図1及び図2を参照して説明
する。なお、図1に示される製造装置の図3製造装置と
同一、又は、相当部分には同一符号を付して、説明は省
略する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. It should be noted that the same or corresponding portions of the manufacturing apparatus shown in FIG. 1 as those of the manufacturing apparatus of FIG.

【0015】マガジン(4)からテーブル(5)上に供給
された1枚の半導体ウェーハ(1)の複数の半導体素子
(2)の特性検査を特性検査装置(6)で順に行い、特性
検査結果が不良の半導体素子(2)に不良マーク(3)を
マーキング装置(7)でマーキングする。また、特性検
査装置(6)に付設した記憶素子(9)に、不良マーク
(3)が付与された被マーキング半導体素子(2)の半導
体ウェーハ(1)における位置情報を記憶させる。
Characteristic inspection of a plurality of semiconductor elements (2) of one semiconductor wafer (1) supplied from the magazine (4) onto the table (5) is sequentially performed by the characteristic inspection device (6), and the characteristic inspection result is obtained. The defective device (2) is marked with a defective mark (3) by a marking device (7). Further, the storage element (9) attached to the characteristic inspection device (6) stores the position information of the semiconductor element (2) to be marked with the defective mark (3) on the semiconductor wafer (1).

【0016】全ての半導体素子(2)の特性検査が終了
した半導体ウェーハ(1)を別の不良マーク認識用テー
ブル(10)に移動させ、テーブル(10)の上方に配置さ
れたカメラ(11)で半導体ウェーハ(1)の各半導体素
子(2)を撮像する。カメラ(11)で撮像された画像デ
ータを画像認識装置(12)に送り、ここで画像処理して
半導体素子(2)上の不良マーク(3)の有無を検出し、
不良マーク有りと認識された半導体素子(2)の半導体
ウェーハ(1)における位置情報を得る。
The semiconductor wafer (1) whose characteristics have been inspected for all the semiconductor elements (2) is moved to another defective mark recognition table (10), and a camera (11) arranged above the table (10). Each semiconductor element (2) of the semiconductor wafer (1) is imaged with. The image data captured by the camera (11) is sent to the image recognition device (12), where image processing is performed to detect the presence or absence of the defective mark (3) on the semiconductor element (2),
The position information on the semiconductor wafer (1) of the semiconductor element (2) recognized as having a defective mark is obtained.

【0017】画像認識装置(12)が半導体ウェーハ
(1)の全半導体素子(2)の画像処理を終了し、全ての
不良マーク認識半導体素子(2)の位置情報を得ると、
特性検査装置(6)の記憶素子(9)に記憶された被マー
キング半導体素子(2)の位置情報を読み出して、この
位置情報D1と画像認識装置(12)からの不良マーク認
識半導体素子(2)の位置情報D2とを比較判定回路(1
3)に入力させる。比較判定回路(13)は2つの位置情
報D1、D2の内容が一致するか否かを比較し、比較結果
から不良マーク(3)のマーキング良否判定をする。2
つの位置情報D1、D2とその比較は、次のようにして行
われる。
When the image recognition device (12) finishes the image processing of all the semiconductor elements (2) of the semiconductor wafer (1) and obtains the position information of all the defective mark recognition semiconductor elements (2),
The position information of the marked semiconductor element (2) stored in the storage element (9) of the characteristic inspection device (6) is read out, and this position information D 1 and the defective mark recognition semiconductor element from the image recognition device (12) ( 2) Position information D 2 of comparison judgment circuit (1
Enter in 3). The comparison / determination circuit (13) compares whether or not the contents of the two pieces of position information D 1 and D 2 match, and determines whether the defective mark (3) is defective or not based on the comparison result. Two
The two pieces of position information D 1 and D 2 and their comparison are performed as follows.

【0018】例えば、図2(a)に示されるように、半
導体ウェーハ(1)のN番目に特性検査された半導体素
子(2')の特性が不良で、不良マーク(3)がマーキン
グされたとすると、記憶素子(9)はそのメモリマップ
のN番目にマーキング有りの情報を記憶する。この半導
体ウェーハ(1)がカメラ(11)で撮像され、画像認識
装置(12)でN番目の半導体素子(2')にマーキングさ
れた不良マーク(3)が認識されたとする。この場合、
比較判定回路(13)は、半導体ウェーハ(1)のN番目
の半導体素子(2')に対して同一内容のマーキング有り
の信号と不良マーク有りの信号を比較して、不良マーク
(3)が鮮明で正常にマーキングされていると判定し、
マーキングOKの信号を出力する。
For example, as shown in FIG. 2 (a), the semiconductor wafer (1) has the Nth characteristic-tested semiconductor element (2 ') that has a defective characteristic and is marked with a defective mark (3). Then, the storage element (9) stores the N-th information with marking in the memory map. It is assumed that the semiconductor wafer (1) is imaged by the camera (11) and the defective mark (3) marked on the N-th semiconductor element (2 ′) is recognized by the image recognition device (12). in this case,
The comparison / determination circuit (13) compares the signal with marking and the signal with defective mark of the same content with respect to the N-th semiconductor element (2 ′) of the semiconductor wafer (1), and the defective mark (3) is detected. Judged as clear and normal marking,
The marking OK signal is output.

【0019】このような判定が半導体ウェーハ(1)の
被マーキング半導体素子(2')の全てに対して行われ
る。1枚の半導体ウェーハ(1)の画像認識後、比較判
定回路(13)の最終判定結果がマーキングOKである
と、半導体ウェーハ(1)はテーブル(10)からマガジ
ン(8)に供給されて、後工程に送られる。
Such a determination is performed for all the marked semiconductor elements (2 ') of the semiconductor wafer (1). After the image recognition of one semiconductor wafer (1), if the final judgment result of the comparison judgment circuit (13) is marking OK, the semiconductor wafer (1) is supplied from the table (10) to the magazine (8), It is sent to the subsequent process.

【0020】図2(b)に示されるように、半導体ウェ
ーハ(1)のN番目の半導体素子(2')が特性不良で、
これにマーキングされる不良マーク(3)が掠れたサイ
ズ小の不鮮明なものである場合も、記憶素子(9)はそ
のメモリマップのN番目にマーキング有りの情報を記憶
する。この半導体ウェーハ(1)のN番目の半導体素子
(2')の不良マーク(3)が画像認識装置(12)で認識
できない不鮮明な場合、画像認識装置(12)は比較判定
回路(13)にN番目の半導体素子(2')が不良マーク無
しの情報を出力する。すると比較判定回路(13)は、半
導体ウェーハ(1)のN番目の半導体素子(2')に対し
てマーキング有りの情報と不良マーク無しの情報の相反
する2つの情報を比較して、マーキングが不良になって
いるマーキングNGの信号を出力する。
As shown in FIG. 2B, the N-th semiconductor element (2 ') of the semiconductor wafer (1) has a defective characteristic,
Even when the defective mark (3) to be marked on this is blurred and small in size, the storage element (9) stores the N-th information with marking in the memory map. When the defective mark (3) of the N-th semiconductor element (2 ') of the semiconductor wafer (1) is unclear which cannot be recognized by the image recognition device (12), the image recognition device (12) causes the comparison judgment circuit (13) to detect it. The N-th semiconductor element (2 ') outputs information without a defective mark. Then, the comparison / determination circuit (13) compares two pieces of contradictory information, that is, the information with the marking and the information without the defective mark with respect to the N-th semiconductor element (2 ′) of the semiconductor wafer (1), and the marking is performed. The signal of the defective marking NG is output.

【0021】また、図2(c)に示されるように、半導
体ウェーハ(1)のN番目の半導体素子(2')が特性不
良であるにも拘らず、これに不良マークがマーキングさ
れないことがある。このような場合でも、記憶素子
(9)はそのメモリマップのN番目にマーキング有りの
情報を記憶する。他方、画像認識装置(12)は比較判定
回路(13)にN番目の半導体素子(2')が不良マーク無
しの情報を出力する。その結果、比較判定回路(13)
は、半導体ウェーハ(1)のN番目の半導体素子(2')
に対してマーキング有りの情報と不良マーク無しの情報
を比較して、マーキングNGの信号を出力する。
Further, as shown in FIG. 2C, although the N-th semiconductor element (2 ') of the semiconductor wafer (1) has a defective characteristic, it may not be marked with a defective mark. is there. Even in such a case, the storage element (9) stores the Nth marking information in the memory map. On the other hand, the image recognition device (12) outputs information to the comparison / determination circuit (13) that the N-th semiconductor element (2 ') has no defective mark. As a result, comparison judgment circuit (13)
Is the N-th semiconductor element (2 ') of the semiconductor wafer (1)
In comparison with the information with marking and the information without defective mark, a signal of marking NG is output.

【0022】図2(b)や(c)のように比較判定回路
(13)がマーキングNGの出力をすると、特性検査工程
でマーキングが正常に行われていないと認知されて、後
続半導体ウェーハの特性検査、マーキングが停止され、
マーキング装置(7)の調整などが行われる。 したが
って、テーブル(10)からマガジン(8)にはマーキン
グOKの半導体ウェーハ(1)だけが供給される。マガ
ジン(8)に収納された半導体ウェーハ(1)をマウント
工程に送り、半導体ウェーハ(1)から分割された個々
の半導体素子(2)を画像処理すると、特性不良の半導
体素子(2')の不良マーク(3)は鮮明であるから、特
性不良の半導体素子(2')が特性良品と誤認される心配
が皆無となる。
When the comparison / judgment circuit (13) outputs the marking NG as shown in FIGS. 2 (b) and 2 (c), it is recognized that the marking is not normally performed in the characteristic inspection process, and the subsequent semiconductor wafer Characteristic inspection, marking stopped,
Adjustment of the marking device (7) is performed. Therefore, only the semiconductor wafers (1) with marking OK are supplied from the table (10) to the magazine (8). When the semiconductor wafer (1) stored in the magazine (8) is sent to the mounting process and the individual semiconductor elements (2) divided from the semiconductor wafer (1) are subjected to image processing, the semiconductor elements (2 ′) with defective characteristics are detected. Since the defective mark (3) is clear, there is no concern that the semiconductor element (2 ') with defective characteristics will be mistaken for a good product.

【0023】なお、本発明の説明の都合上、半導体ウェ
ーハ(1)の各半導体素子(2)の特性検査を行うテーブ
ル(5)と、不良マーク(3)を認識するテーブル(10)
を分けたが、1つのテーブルで特性検査と不良マーク認
識を行うようにすることも可能である。
For convenience of explanation of the present invention, a table (5) for inspecting the characteristics of each semiconductor element (2) of the semiconductor wafer (1) and a table (10) for recognizing a defective mark (3).
However, it is also possible to perform the characteristic inspection and the defective mark recognition with one table.

【0024】[0024]

【発明の効果】本発明によれば、半導体ウェーハの被マ
ーキング半導体素子の半導体ウェーハにおける位置情報
と、特性検査後の半導体素子画像から不良マーク有りと
認識された半導体素子の半導体ウェーハにおける位置情
報の内容が一致するか否かの比較で、特性検査工程のマ
ーキングの良否判定ができ、この良否判定により特性検
査工程の複数半導体ウェーハのマーキング不良連続発生
の防止が可能となり、また、マーキング良好な半導体ウ
ェーハを後工程に送ることができて、半導体装置の製造
歩留まりを向上させることが可能となる。
According to the present invention, the positional information on the semiconductor wafer of the semiconductor element to be marked on the semiconductor wafer and the positional information on the semiconductor wafer of the semiconductor element recognized as having a defective mark from the semiconductor element image after the characteristic inspection are displayed. By comparing whether the contents match or not, it is possible to judge the quality of the marking in the characteristic inspection process, and by this quality judgment it is possible to prevent the continuous occurrence of defective marking on multiple semiconductor wafers in the characteristic inspection process. The wafer can be sent to the subsequent process, and the manufacturing yield of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す半導体装置の製造装置
の概略を示す側面図
FIG. 1 is a side view showing an outline of a semiconductor device manufacturing apparatus showing an embodiment of the present invention.

【図2】本発明の動作原理を説明するためのブロック図
で、(a)は2つのマーキング情報が一致した場合、
(b)及び(c)は2つのマーキング情報が一致しない
場合が示される。
FIG. 2 is a block diagram for explaining the operation principle of the present invention, in which (a) is a case where two pieces of marking information match.
(B) and (c) show cases where the two marking information do not match.

【図3】(a)は従来の半導体装置の製造装置の概略を
示す側面図、(b)は図3(a)における半導体ウェー
ハの平面図
3A is a side view schematically showing a conventional semiconductor device manufacturing apparatus, and FIG. 3B is a plan view of the semiconductor wafer in FIG. 3A.

【符号の説明】[Explanation of symbols]

1 半導体ウェーハ 2 半導体素子 2' 半導体素子 3 不良マーク 6 特性検査装置 9 記憶素子 11 カメラ 12 画像認識装置 13 比較判定回路 1 Semiconductor wafer 2 Semiconductor element 2'Semiconductor element 3 Defect mark 6 Characteristic inspection device 9 Storage element 11 Camera 12 Image recognition device 13 Comparison judgment circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体ウェーハに複数形成された半導体
素子の特性検査を順に行い、特性不良と判定された半導
体素子上に不良マークをマーキングすると共に、不良マ
ークをマーキングした半導体素子の半導体ウェーハにお
ける位置情報を記憶素子に記憶させる特性検査工程と、 特性検査後の半導体ウェーハの各半導体素子をカメラで
撮像し、その画像処理から半導体素子上の前記不良マー
クの有無を検出して、不良マーク有りと認識された半導
体素子の半導体ウェーハにおける位置情報と、前記記憶
素子から読み出した被マーキング半導体素子の位置情報
を比較する不良マーク認識工程とを含むことを特徴とす
る半導体装置の製造方法。
1. A semiconductor device having a plurality of semiconductor elements formed on a semiconductor wafer is sequentially inspected for characteristics, a defective mark is marked on the semiconductor element determined to have a defective characteristic, and the position of the semiconductor element marked with the defective mark on the semiconductor wafer. A characteristic inspection process of storing information in a memory element, and image pickup of each semiconductor element of the semiconductor wafer after the characteristic inspection with a camera, and the presence or absence of the defective mark on the semiconductor element is detected from the image processing to detect that there is a defective mark. A method of manufacturing a semiconductor device, comprising: a defective mark recognition step of comparing the position information of the recognized semiconductor element on the semiconductor wafer with the position information of the marked semiconductor element read from the storage element.
【請求項2】 半導体ウェーハに複数形成された半導体
素子の特性検査を順に行い、特性不良と判定された半導
体素子上に不良マークをマーキングすると共に、不良マ
ークをマーキングした半導体素子の半導体ウェーハにお
ける位置情報を記憶素子に記憶させる特性検査装置と、 特性検査後の半導体ウェーハの各半導体素子をカメラで
撮像し、その画像処理から半導体素子上の前記不良マー
クの有無を検出する画像認識装置と、 画像認識装置で不良マーク有りと認識された半導体素子
の半導体ウェーハにおける位置情報と、前記特性検査装
置の記憶素子から読み出した被マーキング半導体素子の
位置情報を比較して、特性検査工程のマーキングの良否
を判定する比較判定回路とを具備したことを特徴とする
半導体装置の製造装置。
2. A plurality of semiconductor elements formed on a semiconductor wafer are sequentially subjected to characteristic inspection to mark a defective mark on a semiconductor element determined to have a defective characteristic and the position of the semiconductor element on which the defective mark is marked on the semiconductor wafer. A characteristic inspection device that stores information in a storage element, an image recognition device that images each semiconductor element of a semiconductor wafer after the characteristic inspection with a camera, and detects the presence or absence of the defective mark on the semiconductor element from the image processing, The position information on the semiconductor wafer of the semiconductor element recognized as having a defective mark by the recognition device and the position information of the marked semiconductor element read from the storage element of the characteristic inspection device are compared to determine whether the marking in the characteristic inspection process is good or bad. An apparatus for manufacturing a semiconductor device, comprising: a comparison / determination circuit for determining.
JP6006693A 1993-03-19 1993-03-19 Method and device for manufacturing semiconductor device Withdrawn JPH06275686A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6006693A JPH06275686A (en) 1993-03-19 1993-03-19 Method and device for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6006693A JPH06275686A (en) 1993-03-19 1993-03-19 Method and device for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPH06275686A true JPH06275686A (en) 1994-09-30

Family

ID=13131346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6006693A Withdrawn JPH06275686A (en) 1993-03-19 1993-03-19 Method and device for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH06275686A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100327101B1 (en) * 1999-08-11 2002-03-18 김주환 An automatic teaching method in marking inspection process of a semiconductor packages
KR20030029003A (en) * 2001-10-04 2003-04-11 주식회사 로코스텍 The BGA package process control system related to X-mark
JP2008010485A (en) * 2006-06-27 2008-01-17 Denso Corp Wafer inspection system and method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100327101B1 (en) * 1999-08-11 2002-03-18 김주환 An automatic teaching method in marking inspection process of a semiconductor packages
KR20030029003A (en) * 2001-10-04 2003-04-11 주식회사 로코스텍 The BGA package process control system related to X-mark
JP2008010485A (en) * 2006-06-27 2008-01-17 Denso Corp Wafer inspection system and method

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