JPH06275652A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an elecrode in contact with a semiconductor substrate, the contact width or length being very small, by a method wherein the semiconductor surface is gradually exposed from a position corresponding with a recess, by etching an upper layer film having the recess in the vicinity of the central part of a hole for forming an electrode, and the exposed region is made smaller than the size of the hole for forming the electrode. CONSTITUTION:A lower layer film 41 is formed on the surface of a semiconductor substrate 21. A hole 45 for forming an electrode is formed in a specific position of the lower layer film 41. An upper layer film 42 which has a recess 40 in the vicinity of the central part of the hole 45 is formed only on the semiconductor substrate 21 in the hole 45. By etching the upper layer 42, the surface of the semiconductor substrate 21 is gradually exposed from the position corresponding to the recess 40. Hence the region where the semiconductor substrate 21 is exposed is smaller than the hole 45. Metal for an electrode is deposited in contact with the exposed substrate surface, and an electrode 49 is formed. Thereby the contact of the semiconductor substrate and the electrode can be made smaller than the hole for forming the electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as a Schottky gate type field effect transistor in which electrodes are provided on a semiconductor substrate.

[0002]

2. Description of the Related Art GaAs compound semiconductors have electron mobility and drift velocity several times higher than Si, and are therefore suitable as materials for high-speed switching devices. Of these devices using GaAs compound semiconductors, the most advanced research is currently underway,
A Schottky gate type field effect transistor (MESFET: MEtal Semiconductor Fifo) is put into practical use.
eld Effect Transistor).

The basic structure of this GaAs MESFET is
It is shown in FIG. An N-type active region 2 formed by diffusing N-type impurities such as Si is formed in a predetermined region near the surface of the semi-insulating GaAs substrate 1. A Schottky gate electrode 3 which is in Schottky contact with the GaAs substrate 1 is formed on the N-type active region 2. A pair of N ⁺ -type high-concentration impurity regions 4 and 5 in which N-type impurities such as Si are diffused at a high concentration are formed in the GaAs substrate 1 with the Schottky gate electrode 3 interposed therebetween. Source and drain electrodes 6 and 7 are formed on the pair of N ⁺ -type high-concentration impurity regions 4 and 5. The electrodes 6 and 7 are N ⁺ type high concentration impurity regions 4 and
5 is in ohmic contact. 8 is a GaAs substrate 1
Is a surface protective film for preventing alteration of the surface of, and is made of, for example, SiO ₂ or SiON.

In this configuration, the voltage applied to the Schottky gate electrode 3 causes the Schottky gate electrode 3 and the GaAs to move.
The spread of the depletion layer 9 formed near the interface with the substrate 1 can be controlled. This controls the current flowing between the source and the drain. FIG. 6 is a diagram for explaining a method of forming the Schottky gate electrode 3. First, as shown in FIG. 6A, a resist 11 having a window 10 corresponding to the formation position of the Schottky gate electrode 3 on the surface of the GaAs substrate 1.
Are patterned by applying a photolithography technique. The window 10 has a reverse tapered shape in cross section.

Next, as shown in FIG. 6B, the GaAs substrate 1
The gate metal 12 is vapor-deposited perpendicularly to the GaAs substrate 1
A Schottky gate electrode 3 is formed which is in Schottky contact with. Then, as shown in FIG. 6C, the metal 12 on the resist 11 is lifted off together with the resist 11, and the Schottky gate electrode 3 is left on the substrate 1.

[0006]

In order to improve the operating speed of GaAs MESFETs and enhance static characteristics such as high frequency characteristics, it is essential to shorten the gate length. However, in the method of forming the Schottky gate electrode 3 by vertically depositing the gate metal by using the resist 11 patterned by the photolithography technique as a mask as described above, when the resist 11 is exposed, the gate length is shortened depending on the wavelength of the exposure source. There are restrictions on conversion. Specifically, the gate length cannot be 0.3 μm or less.

Therefore, an object of the present invention is to solve the above technical problems and to provide a method of manufacturing a semiconductor device capable of forming an electrode in contact with a semiconductor substrate with an extremely fine width or length. is there.

[0008]

A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises a step of forming an underlayer film on a surface of a semiconductor substrate and an electrode forming step at a predetermined position of the underlayer film. A step of forming a hole, at least on the semiconductor substrate in the electrode forming hole, a step of forming an upper layer film having a depression near the central portion of the electrode forming hole, and etching the upper layer film, A step of exposing the surface of the semiconductor substrate at a position corresponding to the recess; and a step of depositing a metal for an electrode so as to contact the surface of the semiconductor substrate exposed in the vicinity of the central portion of the electrode forming hole to form an electrode. And a step of forming.

[0009]

According to the present invention, the lower layer film is first formed on the surface of the semiconductor substrate, and the electrode forming hole is formed at a predetermined position of the lower layer film. Then, in the electrode forming hole,
An upper layer film having a depression is formed near the central portion. When the upper layer film is etched, the surface of the semiconductor substrate is gradually exposed from the position corresponding to the depression. A metal for an electrode is deposited so as to contact the exposed surface of the semiconductor substrate,
Electrodes are formed.

The upper layer film has a recess near the center of the electrode forming hole. When the upper layer film is etched, the surface of the semiconductor substrate is gradually exposed from the position corresponding to the recess. Therefore, the area where the semiconductor substrate is exposed can be made smaller than the size of the electrode forming hole. As a result, the width or length of the contact portion between the semiconductor substrate and the electrode can be made smaller than the width or length of the electrode forming hole.

[0011]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. 1, 2 and 3 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. In this embodiment, a GaAs Schottky gate type field effect transistor (hereinafter referred to as "GaAs MESFET") is manufactured, and in particular, the manufacturing method according to one embodiment of the present invention is applied for forming the Schottky gate electrode.

First, as shown in FIG. 1 (a), semi-insulating Ga
A pair of windows 2 are formed on the surface of the As substrate 21 with a predetermined space.
A resist 24 having 2, 23 is patterned.
Then, Si ions as N-type impurities are implanted into the GaAs substrate 21 at high concentration using the resist 24 as a mask. Furthermore, after the resist 24 is peeled off, as shown in FIG.
A resist 26 having a window 25 corresponding to an active region where an element is to be formed is patterned as shown in FIG. Then, Si ions are implanted at a low concentration using the resist 26 as a mask. After this ion implantation, the resist 2
6 was peeled off, and further 78 in the arsine atmosphere.
Annealing is performed at a high temperature of 0 ° C to 800 ° C. As a result, as shown in FIG. 1C, the implanted Si ions are activated and an N-type active region 27 and a pair of N ⁺ -type high-concentration impurity regions 28 and 29 are formed.

From this state, a resist 30 is patterned as shown in FIG. 1 (c). This resist 30
Has windows 31 and 32 at positions immediately above the N ⁺ type high concentration impurity regions 28 and 29. These windows 31, 32
Has an inverse taper shape in which the cross-sectional area gradually increases as it approaches the GaAs substrate 21. Such inversely tapered windows 31 and 32 can be formed by a so-called image inversion method. This image inversion method will be described later.

Further, an ohmic metal is vertically vapor-deposited toward the GaAs substrate 21 to form an ohmic metal layer 33, and the state shown in FIG. 1 (c) is obtained. In order to vertically evaporate the metal, for example, an electron beam heating evaporation method or a resistance heating evaporation method may be used. For the ohmic metal layer 33, for example, AuGe (for example, 4000 Å) is deposited on the lower layer side,
This is a two-layer structure film in which Ni (for example, 50Å) is deposited on the upper layer side.

From the state shown in FIG. 1C, the resist 30 and the ohmic metal layer 33 on the resist 30 are removed by the lift-off method. Then, the ohmic metal layer 33 left on the GaAs substrate 21 is alloyed,
As shown in (d), N ⁺ -type high-concentration impurity regions 28 and 29
A source electrode 35 and a drain electrode 36, which are in ohmic contact with, are formed. The alloy treatment can be performed, for example, by performing a heat treatment in a N ₂ atmosphere at a temperature of about 450 ° C. for 5 minutes to 10 minutes.

From this state, next, as shown in FIG. 2D, a SiON film 41 as a lower layer film is formed by a CVD method (chemical vapor deposition method) so as to cover the surface of the GaAs substrate 1. Formed by. The thickness of the SiON film 41 is, for example, 2
It is said to be about 000Å. A resist 44 having a window 43 at a position where a Schottky gate electrode is to be formed between the pair of N ⁺ type high concentration impurity regions 28 and 29 is patterned on the surface of the SiON film 41 by photolithography. The width x of the window 43 in the gate length direction (horizontal direction in FIG. 2) is about 0.4 μm. The minimum value of the width x cannot be smaller than the wavelength (for example, 0.36 μm) of the light generated from the exposure source used when exposing the resist 44.

From this state, the SiON film 41 is anisotropically etched by RIE (reactive ion etching). Then, when the resist 44 is peeled off, the state shown in FIG. That is, the SiON film 41 is in a state where the electrode forming hole 45 having the width x is formed at the position where the Schottky gate electrode is to be formed. Next, as shown in FIG. 2F, a SiN film 42 as an upper layer film is formed so as to cover the surface of the GaAs substrate 21 exposed from the SiON film 41 and the electrode forming holes 45. It is formed. The SiN film 42 is formed to have a recess 46 near the center of the electrode forming hole 45. Specifically, SiN
The film thickness t of the film 42 may be selected to be about ½ of the width x of the electrode forming hole 45 in the gate length direction. For example, if the width x is about 0.4 μm, the film thickness t is 2000Å to 300.
It is set to 0Å.

From this state, a resist 38 is patterned as shown in FIG. 3 (g). This resist 38 is also patterned by the above-mentioned image inversion method, and has an inversely tapered window 39 formed immediately above the electrode forming hole 45. Further, anisotropic etching is performed by the RIE method using the resist 38 as a mask.
By this anisotropic etching, the SiN film 42 exposed from the window 39 is etched. As the etching progresses, as indicated by reference numeral 40 in FIG.
The GaAs substrate 21 is exposed from the recess 46. At this stage, anisotropic etching is completed.

Next, as shown in FIG. 3H, a gate metal layer 47 is deposited by vertical vapor deposition. The gate metal layer 47 has, for example, a Ti layer (1000 Å) as a lower layer,
The middle layer is Pt layer (500 Å), the upper layer is Au (2500 Å)
It is a film with a three-layer structure. After this, as shown in FIG. 3I, the resist 38 and the gate metal layer 47 thereon are lifted off, and the SiN in the electrode forming hole 45 is lifted off.
A Schottky gate electrode 49 which is in Schottky contact with the N-type active region 27 is formed in the hole 48 formed in the film 42. From this state, a protective film 65 is formed on the entire surface, and contact holes 66 and 67 are formed above the source electrode 35 and the drain electrode 36, respectively. Then, the metal wirings 68, 69 are buried in the contact holes 66, 67 to complete the GaAs MESFET.

GaAs MESFE prepared in this way
At T, the width at which the Schottky gate electrode 49 is in contact with the GaAs substrate 21, that is, the gate length Lg is extremely shorter than the width x of the electrode forming hole 45 formed by applying the photolithography technique ( For example, if Lg is 0.
It can be about 2 μm. ). Therefore, the gate length Lg can be made shorter than the wavelength of the light from the exposure source used when patterning the resist 44 (FIG. 2 (d)) by photolithography. That is, the gate length Lg can be shortened beyond the limit of miniaturization limited by the wavelength of the exposure source.

Moreover, as shown in FIG. 3 (i),
Since the Schottky gate electrode 49 has a substantially T-shaped cross-section, the Schottky gate electrode 49 can have a sufficiently large cross-sectional area. That is, it can be formed with low resistance. In this way, the Schottky gate electrode 49 having a low resistance and an extremely short gate length Lg can be formed on the surface of the GaAs substrate 21, so that the GaAs MESFET manufactured according to the method of this embodiment has good static characteristics. Can have. That is, the high frequency characteristics become good,
Further, since the so-called K value corresponding to the rate of change of the source-drain current with respect to the fluctuation of the gate voltage can be increased, high-speed operation can be realized and noise can be suppressed.

FIG. 4 is a simplified sectional view for explaining the above-mentioned image inversion method. First, as shown in FIG. 4A, a positive resist 60 is applied to the surface of the substrate 51,
As shown in (b), a mask 52 is arranged in a region where a window is to be opened and exposure is performed. When the development process is performed in this state, Fig. 4 (f)
Thus, a resist pattern having a trapezoidal cross section can be obtained.
In the image inversion method, the development process is not performed immediately from the state shown in FIG. 4B, but the heat treatment (for example, 11
At 5 ° C for 90 seconds). By this processing, FIG.
The resist 60 in the region 53 exposed in the step (b) is changed to a substance that is difficult to dissolve even if it is subjected to the subsequent exposure and development processes.

Therefore, as shown in FIG. 4D, the entire surface is exposed. Then, when development processing is performed after that, as shown in FIG.
As shown in (e), the resist 60 in the shielded region 54 is dissolved in the exposure step of FIG. 4 (b). That is, a resist pattern in the completely opposite state to the case of FIG. 4 (f) is obtained. This resist pattern has an inversely tapered window 55 in the portion shielded by the mask 52 in the first exposure step.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, in the above embodiment, Si as the upper layer film
Although the N film 42 is formed on the entire surface of the GaAs substrate 21, the SiN film 42 may be formed only on the region near the electrode forming hole 45. Also, in the above embodiment, Ga
The present invention is applied for forming the Schottky gate electrode 49 of AsMESFET.
The present invention can be applied not only to the FET but also to the manufacture of any semiconductor device. That is, it is widely applicable to the case of forming an electrode to be contacted with a minute width or length on the surface of a semiconductor substrate, and in particular, an electrode finer than the wavelength of light of an exposure source used in photolithography is used. It can be effectively applied when pattern formation is desired.

In addition, various design changes can be made without changing the gist of the present invention.

[0026]

As described above, according to the present invention, the lower layer film having the electrode forming holes is formed on the surface of the semiconductor substrate, and the upper layer film is formed at least in the electrode forming holes. Since this upper layer film has a recess near the center of the hole for electrode formation, when the upper layer film is etched, the surface of the semiconductor substrate is gradually exposed from the position corresponding to the recess. Therefore, the region where the semiconductor substrate is exposed can be made smaller than the size of the electrode forming hole, and the width or length of the contact portion between the semiconductor substrate and the electrode can be made smaller than the width or length of the electrode forming hole. can do.

In this way, for example, if the electrode forming holes are formed as fine as possible, it is possible to form electrodes that are in contact with the semiconductor substrate with a width or length that is even smaller than that.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a manufacturing step that follows the step of FIG.

FIG. 3 is a cross-sectional view showing a manufacturing step in order of steps, which follows the step of FIG.

FIG. 4 is a cross-sectional view for explaining a so-called image inversion method for forming a resist having an inversely tapered window.

FIG. 5 is a cross-sectional view showing a configuration of a GaAs Schottky gate type field effect transistor.

FIG. 6 is a cross-sectional view showing a conventional method for forming a Schottky gate electrode in the order of steps.

[Explanation of symbols]

 21 semi-insulating GaAs substrate 41 SiON film (lower layer film) 42 SiN film (upper layer film) 44 resist 45 electrode forming hole 46 recess 49 Schottky gate electrode

Claims (1)

[Claims] 1. A step of forming an underlayer film on a surface of a semiconductor substrate, a step of forming an electrode forming hole at a predetermined position of the underlayer film, and at least on the semiconductor substrate in the electrode forming hole,
A step of forming an upper layer film having a depression near the center of the electrode forming hole; a step of etching the upper layer film to expose the surface of the semiconductor substrate at a position corresponding to the depression; And a step of depositing an electrode metal so as to contact the surface of the semiconductor substrate exposed in the vicinity of the central portion of the hole to form an electrode.