JPH0571176B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a field effect transistor having low source resistance and high drain breakdown voltage.

<Conventional technology> Conventional field effect transistor (referred to as FET)
In order to reduce the source resistance (R _sp ) and simplify the manufacturing process, an active layer 12 is formed on the main surface of the semiconductor substrate 11 as shown in FIG. Using the gate electrode 13 formed on the surface as a mask, impurities having the same conductivity type as the active layer 12 are introduced by diffusion or ion implantation to form a highly concentrated source region 14 and drain region 15. Some devices are manufactured by aligning the source and drain regions 14, 15 with the gate region. In the figure, 16 is a source electrode, and 17 is a drain electrode.

<Problems to be solved by the invention> However, in conventional field effect transistors of this type, when the drain voltage is increased to 10V or more, the gate voltage
There were problems such as the space between the drains was easily destroyed, a sufficient drain breakdown voltage could not be obtained, and the gate-drain capacitance increased. This decrease in drain breakdown voltage and increase in gate-drain capacitance is due to the fact that the high concentration region 15 on the drain side is close to the gate electrode 13, but this is because the high concentration region 14 on the source side is This is caused by the formation of the gate electrode 13 in a self-aligned manner.

Conventional self-alignment methods have also attempted to separate the high concentration region on the drain side from the gate electrode in order to improve drain breakdown voltage, but with this method, the high concentration region on the source side is also separated from the gate electrode at the same time. As a result, the source resistance increases and good FET characteristics cannot be obtained.

In addition, to improve FET characteristics, the gate length Lg (Fig. 2)
Although it is effective to shorten the gate length Lg, there is a problem in that the gate length Lg cannot be made shorter than a certain value because reducing the gate length Lg increases the gate resistance and hinders the improvement of FET characteristics.

The present invention was devised in view of the above-mentioned points, and in order to solve the above-mentioned conventional problems, the high concentration region on the source side is formed at an arbitrary distance _L1 from the gate electrode, and the high concentration region on the drain side is By forming the concentration region at an arbitrary distance _L2 from the gate electrode and making _L2 larger than _L1 , it is possible to prevent an increase in source resistance and improve drain breakdown voltage, while at the same time reducing the gate length by shortening the gate length. The object of the present invention is to provide a method for manufacturing a field effect transistor that suppresses an increase in resistance.

<Means for Solving the Problems> In order to achieve the above object, an active layer is formed on the main surface of the semiconductor substrate of the present invention, and a source electrode, a gate electrode, and a drain electrode are formed on the same surface as the active layer. A field effect transistor arranged in parallel, in which a source region and a drain region containing a high concentration of impurities of the same conductivity type as the active layer are formed so as to be in contact with the active layer; A predetermined distance between the positions where the layers are in contact with each other and the gate electrode, that is, the distance between the position where the source region and the active layer region are in contact with each other and the gate electrode is the distance between the drain region and the active layer region. A method for manufacturing a field effect transistor in which a relationship smaller than the distance between an adjacent position and a gate electrode exists, and a source region and a drain region are formed in self-alignment with the gate electrode, When ion implantation is performed to form an active layer on the semiconductor substrate, and then a source electrode, a gate electrode, and a drain electrode are juxtaposed on the same surface to form a field effect transistor, the active layer surface of the semiconductor substrate is a step of forming a gate electrode made of two layers of heat-resistant metal; a step of applying resist to the entire surface of the semiconductor substrate and forming a photomask on the region other than the active layer; and diagonal exposure from the source side. forming an ion implantation mask on the region from the drain side side wall of the gate electrode to the desired position on the drain side and on the region other than the active layer by developing; A step of ion-implanting impurities having the same conductivity type as the layer at a high concentration to form high concentration regions that will become source and drain regions, and step 2 of forming the gate electrode described above.
A process of etching the heat-resistant metal in contact with the semiconductor substrate among the heat-resistant metals in the layer, a process of activating the above-mentioned active layer and high concentration region by heat treatment, and forming source and drain electrodes on the above-mentioned high-concentration region. It is configured to include a step of.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1A to 1G are cross-sectional views showing the manufacturing process of a field effect transistor for explaining one embodiment of the present invention.

In FIG. 1a, in the case of a semiconductor substrate 21, for example a semi-insulating GaAs substrate, impurities such as Si are introduced by ion implantation to form an n-type active layer 22. In FIG.

Next, the high melting point metal 23 and the high melting point metal 24 are applied to the semiconductor substrate 21 using an appropriate deposition method such as a sputtering method.
is deposited on the main surface of the metal to form two heat-resistant metal layers. As the high melting point metal 23, for example, in the case of GaAs, a high melting point metal such as Mo.W, whose shot key characteristics do not deteriorate due to heat treatment, or its silicide is suitable. Further, the high melting point metal 24 must not change in quality due to heat treatment and can serve as a mask when etching the high melting point metal 23.
An appropriate metal is selected depending on what is used as the high melting point metal 23. High melting point metal 23 and high melting point metal 2
An example of a combination of 4 is MoSi ₂ and Mo, Mo and
There are Au etc.

Next, a pattern for gate electrode processing is formed using a resist 25 on the deposited high melting point metal 23 and high melting point metal 24 . The dimensions of this resist 25 are set to be longer, for example, by about 0.4 μm than the required gate length.

Next, as shown in FIG. 1B, the high melting point metal 23 and the high melting point metal 24 are etched using the resist 25 as a mask to form a gate electrode.

Next, as shown in FIG. 1c, after removing the resist 25, a resist 251 having the same thickness as the gate electrodes 23, 24 is applied,
After using a mask to match the part that will become the insulating layer, the source side is exposed to light from an acute angle and developed. At this time, the gate electrodes 23 and 24 serve as masks, and a resist 252 remains on the drain side of the gate electrodes as shown in FIG. 1d. Furthermore, this remaining area 2
52 can be arbitrarily controlled by the thickness of the gate electrodes 23 and 24 and the exposure angle. In this way, a pattern for ion implantation is formed using the resist 251.

Next, as shown in FIG.
52 and the gate electrodes 23 and 24 as a mask, the high concentration region 2 is implanted with high concentration impurities having the same conductivity type as the active layer 22.
7, 28 are formed. At this time, the high concentration region 28 on the drain side is separated from the gate electrode by a length α due to the resist 252 described above. The length α is determined by three points: the thickness of the gate electrodes 23 and 24, the angle of exposure, and the acceleration energy during ion implantation.

Next, as shown in FIG. 1F, after the resists 251 and 252 are peeled off, the high melting point metal 23 is etched using the high melting point metal 24 as a mask. Assuming that the amount of etching at this time is b, as a result of this step, the refractory metal 23 is formed at a distance b from the source side high concentration region 27 and at a distance a+b from the drain side high concentration region 28. be done. As distances a and b, for example, a=
Appropriate values are approximately 0.4 μm and b = 0.2 μm.

Next, as shown in FIG. 1g, the active layer 22 and the high concentration regions 27 and 28 are activated by heat treatment, and ohmic contact is made on the upper parts of the high concentration regions 27 and 28 by a list-off method using a resist. The metals 29 and 30 to be formed are deposited. Through the heat treatment for alloying, the metals 29 and 30 become the source electrode 29 and drain electrode 3 of the field effect transistor, respectively.
It becomes 1.

As a result of the above, the gate electrodes (high melting point metals 23, 24
), whereas the source side high concentration region 27 is at a distance of
Separated by L ₁ (=b), drain side high concentration region 28
can produce field effect transistors separated by a distance L ₂ (=a+b). Further, by setting the distance l ₁ and the distance L ₂ to appropriate values, it is possible to improve drain breakdown voltage, gate-drain capacitance, etc. in a self-aligned field effect transistor without increasing the source resistance.

Furthermore, even if the gate length is shortened, the two layers of metal constituting the gate electrode, that is, the high melting point metals 23 and 24
Among them, the length of the metal 24 that does not contact the active layer region 22 is kept constant, and the gate resistance hardly increases. Therefore, the characteristics of the field effect transistor are effectively improved.

<Effects of the Invention> As detailed above, the method of the present invention provides the following effects compared to the conventional embodiments.

When the distances between the gate electrode (consisting of two layers of heat-resistant metal) and the source or drain electrode are _L1 and _L2 , respectively, the distance _L1 is, for example, 0.2 to
0.3 μm, and distance L ₂ can be controlled with high precision and repeatability of, for example, 0.4 to several μm, improving drain breakdown voltage and increasing gate-drain capacitance without increasing the source resistance of self-aligned transistors. can be prevented.

Even if the gate length is shortened, the gate resistance hardly increases, so the characteristics of the field effect transistor are effectively improved.

A field effect transistor with an asymmetric structure can be easily manufactured with good reproducibility without using complicated techniques such as oblique vapor deposition or oblique ion implantation.

[Brief explanation of the drawing]

FIGS. 1A to 1G are cross-sectional views showing the manufacturing process of a field effect transistor for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a conventional field effect transistor. 21...Semiconductor substrate, 22...Active layer, 23,
24... High melting point metal (gate electrode), 25, 25
1,252...Resist, 26...Mask, 27
. . . Highly doped source region, 28… Highly doped drain region, 29… Source electrode, 30… Drain electrode.

Claims (1)

[Claims] 1. Ion implantation is performed to form an active layer on the main surface of a semiconductor substrate, and then a source electrode, a gate electrode, and a drain electrode are juxtaposed on the same surface to form a field effect transistor. In this case, a step of forming a gate electrode made of two layers of heat-resistant metal on the surface of the active layer of the semiconductor substrate, and a step of applying a resist to the entire surface of the semiconductor substrate and forming a photomask on a region other than the active layer. By exposing and developing obliquely from the source side, an ion implantation mask is formed over the region from the drain side side wall of the gate electrode to a desired position on the drain side and over the region other than the active layer. a step of ion-implanting impurities having the same conductivity type as the active layer at a high concentration to form high-concentration regions that will become source and drain regions; The method is characterized by including the following steps: etching a heat-resistant metal in contact with the semiconductor substrate; activating the active layer and high concentration region by heat treatment; and forming source and drain electrodes on the high concentration region. A method for manufacturing a field effect transistor.