JPH06260926A - Level shift circuit for logical signal - Google Patents

Abstract

PURPOSE:To reduce the delay time of a logical output signal and also to reduce the necessary area of a semiconductor chip in regard of a semiconductor integrated circuit. CONSTITUTION:A PMOS FET 1, a PMOS FET 2 and an NMOS FET 3 are connected in series between a positive power line VC and a negative power line VE of a high voltage system. Then a PMOS FET 4 and an NMOS FET 6 connected in series to each other are connected in parallel to those FET 1-3. Furthermore a PMOS FET 5 is connected in parallel to the FET 4. Then the connection point between the FET 2 and 3 is connected to the gate of the FET 6, and the connection point between the FET 4 and 6 is connected to the gate of the FET 3 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic signal level shift circuit for converting a low voltage system level logic signal into a high output high voltage system level logic signal in an output stage of a logic circuit.

[0002]

2. Description of the Related Art Tables 1 and 2 show logic signals of low voltage system level, for example, "H" (positive side line voltage V _CC = 5V) and "L" (negative side line voltage V _SS = 0V). ,
For example, the positive side line voltage V _CC = 5V, the negative side line voltage V _EE
= NOR conversion to a high voltage level of -20V (usually
(Referred to as negative power supply conversion) of logic signal or positive power supply line voltage V _DD = 25V, negative power supply line voltage V
The truth table of the level shift circuit of the logic signal which NOR-converts to the high voltage system level of _SS = 0V (usually called plus power supply conversion) is shown.

[0003]

[Table 1]

[0004]

[Table 2]

FIGS. 3 and 4 are circuit diagrams showing first and second conventional examples of logic signal level shift circuits, respectively. FIG. 3 shows a minus power supply conversion level shift circuit corresponding to Table 1, and FIG. Shows a positive power supply conversion level shift circuit corresponding to Table 2. In FIG. 3, this negative power supply conversion level shift circuit is used for the high voltage system positive power supply line V _C.
P MOSFE in which the source / drain and the drain / source are connected in series between the (power line voltage V _CC ) and the negative power line V _E (power line voltage V _EE ).
T 13 and N MOSFET 14 and P MO having these source / drain and drain / source connected in series to these MOSFETs connected in series
SFET 15 and N MOSFET 16 and NO whose output terminal is connected to the gate of P MOSFET 13
R gate 17 and its input terminal are P MOSFET 13
And an inverter 18 whose output terminal is connected to the gate of the P MOSFET 15
The drain of SFET 13 is the gate of N MOSFET 16, and the drain of P MOSFET 15 is N MOSF.
NOR gate 1 connected to the gate of ET14
Two input terminals 7 are connected to the signal input terminals IN1 and IN2, respectively, and the drain of the P MOSFET 15 is connected to the signal output terminal OUT1 and the drain of the P MOSFET 13 is connected to the signal output terminal OUT2.

The operation of this level shift circuit is as follows.
is there. Now, to the signal input terminals IN1 and IN2 respectively
Low voltage system level A = “H” (positive side line voltage V
_CC, B = “H” (positive side line voltage V_CCLogical entry
If a force signal is input, the output of NOR gate 17
Is "L", the P MOSFET 13 is not turned on.
It This “L” signal is output from the “H” signal by the inverter 18.
Since it is converted into a signal, the P MOSFET 15 is turned off.
It P MOSFET 13 is on, P MOSFET 1
5 turns off, the N MOSFET 16 turns on and N
The MOSFET 14 is turned off. Therefore, the signal output terminal O
UT1 logic output signal Q = V_EE, Signal output terminal OUT2
Output signal rQ = V_CCHigh voltage system level logic signal
Is converted to. Further, A = “L” (negative side line voltage V_SS
, B = “H” (positive side line voltage V_CC) Logic input
When a signal is input, the logic output is performed in the same procedure.
Signal Q = V _EE, RQ = V_CC, A = “H”, B = “L”
Is a logical input signal, the logical output signal Q = V_EE, RQ =
V_CCOf A = “L” and B = “L” logic input signals
Is a logical output signal Q = V_CC, RQ = V_EEHigh voltage system level
Are converted to logic signals.

Further, in FIG. 4, the positive power supply conversion level shift circuit has a positive power supply line V _D (power supply line voltage V _DD ) and a negative power supply line V _S (power supply line voltage V _SS ) of a high voltage system. P MOSFET 1 in which the source / drain and the drain / source are connected in series between
9 and an N MOSFET 20, and a P MOSF in which the source / drain and the drain / source of the MOSFET connected in series are connected in series.
ET21 and N MOSFET 22, an NOR gate 23 whose output terminal is connected to the gate of N MOSFET 20, an inverter 24 whose input terminal is connected to the gate of N MOSFET 20 and whose output terminal is connected to the gate of N MOSFET 22, N MOSFE
The drain of T20 is N to the gate of P MOSFET 21.
The drain of the MOSFET 22 is connected to the P MOSFET 19
Of the NOR gate 23, and the input terminal of the NOR gate 23 is connected to the signal input terminals IN1 and IN2.
The drain of the MOSFET 22 is a signal output terminal OUT1.
The drain of the N MOSFET 20 to the signal output terminal O
It is connected to UT2.

The operation of this level shift circuit is as follows. Now, to the signal input terminals IN1 and IN2, the low voltage system level A = “H” (the positive side line voltage V
_Assuming that a logic input signal of _CC ) and B = “H” (of positive side line voltage V _CC ) is input, the output of the NOR gate 23 becomes “L”, and the N MOSFET 20 is turned off. Since this "L" signal is converted into an "H" signal by the inverter 24, the N MOSFET 22 is turned on. N MOSFET 20 is off, N MOSFET 2
2 is turned on, the P MOSFET 19 is turned on and P MOSFET 19 is turned on.
The MOSFET 21 is turned off. Therefore, the signal output terminal O
UT1 logic output signal Q = V _SS , signal output terminal OUT2
Is converted into a logic signal of a high voltage system level of rQ = V _DD . Further, A = “L” (negative side line voltage V _SS
, B = “H” (of positive side line voltage V _CC ), a logic output signal Q = V _SS , rQ = V _DD , A = “ H ”, B =
When the logic input signal is “L”, the logic output signal Q = V _SS ,
When rQ = V _DD , A = “L” and B = “L”, the logic input signal is converted into a logic signal of high voltage system of logic output signal Q = V _DD , rQ = V _SS .

[0009]

Since the level shift circuit described above uses the NOR gate and the inverter,
There is a problem that the delay time of the logic output signal becomes long, or when formed as a semiconductor integrated circuit, the required area of the semiconductor chip becomes large due to these NOR gates or inverters.

An object of the present invention is to solve these problems, to provide a logic signal level shift circuit which reduces the delay time of a logic output signal and has a small area required for a semiconductor chip when formed as a semiconductor integrated circuit. Especially.

[0011]

In order to achieve the above-mentioned object, a logic signal level shift circuit according to the present invention has a main terminal between a positive power supply line and a negative power supply line of a high voltage system. First P-MOSFET, second connected in series
A P MOSFET and a first N MOSFET,
A third P-MOSFET and a second N-MOSFET whose main terminals are connected in series to these MOSFETs connected in series, and the third P-MOSF
A fourth P having its main terminal connected in parallel to the main terminal of ET
And a third P-MOSFE
The connection point between the main terminal of T and the main terminal of the second N MOSFET is connected to the gate of the first N MOSFET,
The main terminal of the second P MOSFET and the first N MO
The connection point of the main terminals of the SFET is connected to the second N-MOSFE.
Connect to the gate of T. Alternatively, a first P MOSFET, a first N MOSFET, and a second N MOSFET whose main terminals are connected in series between a high-voltage power supply line and a negative power supply line, and these are connected in series. A second P MOSFET and a third N MOSFET whose main terminals are connected in series to the connected MOSFET in parallel, and the third N MOSFET.
A fourth N having its main terminal connected in parallel to the main terminal of T
And a second P-MOSFET
A main terminal of the first P MOSFET and a main terminal of the third P MOSFET are connected to the gate of the first P MOSFET, and the first P MOSFET and the first N MOSFET are connected.
The connection point of T is connected to the gate of the second P MOSFET. Further, it is formed as a semiconductor integrated circuit.

[0012]

In any of the logic signal level shift circuits according to the present invention, the MOSFET connected to the high voltage system line is directly driven by the low voltage system logic signal or the inversion signal of this logic signal. As a result, the number of input stages is reduced and the output delay time is remarkably shortened as compared with the conventional NOR gate and inverter. In addition, the NOR gate and the inverter, which require a large area of the semiconductor chip, are eliminated and the MO is removed.
Since the circuit is composed of only SFETs, when it is formed as a semiconductor integrated circuit, it becomes a level shift circuit for logic signals that requires a small area of a semiconductor chip.

[0013]

1 and 2 show the logic signals of the present invention.
Of the first and second embodiments of the level shift circuit of
It is a road map, and Fig. 1 shows the negative power conversion level shift circuit.
2 shows a positive power supply conversion level shift circuit. Figure
1, the minus power supply conversion level shift circuit
Is the positive power supply line V of the high voltage system_C(Power line voltage V
_CC) And the negative power supply line V_E(Power line voltage V_EE) With
Source / drain, source / drain and
P-MOSFE with drain and source connected in series
T1, P MOSFET2 and N MOSFET3
And in parallel with these series connected MOSFETs
Source / drain and drain / source in series
Connected P MOSFET 4 and N MOSFET
6 and its source and drain are P-MOSFE
P MOSFET connected to the source / drain of T4
5, the drain of P MOSFET 2 and N M
The connection point of the drain of OSFET3 is N MOSFET6
The drain of the P MOSFET 4 and the N MO
The connection point of the drain of SFET6 is N MOSFET3
The gate of P MOSFET 1 is connected to each gate.
Is connected to the signal input terminal IN1 by the gate of P MOSFET2.
To the signal input terminal IN2 and the gate of the P MOSFET 4
Is connected to the signal input terminal IN3 and the gate of the P MOSFET5.
Is connected to the signal input terminal IN4, and is connected to the N MOSFET
The drain of 3 is connected to the signal output terminal OUT1,
The drain of ET6 is connected to the signal output terminal OUT2.
Has been continued.

The operation of this level shift circuit is as follows. Now, to the signal input terminals IN1 and IN2, A = “H” (of the positive line voltage V _CC ) of the low voltage system level,
When a logic input signal of B = “H” (of positive side line voltage V _CC ) is input and rA or rB of the inverted signal of the logic input signal A or B is input to the signal input terminals IN3 and IN4, respectively, P MOSFET1 And P MO
SFET2 turns off, P MOSFET4 and P M
OSFET5 is turned on. P MOSFET1 and P
When the MOSFET 2 is turned off, the N MOSFET 6 is turned off, and the P MOSFET 4 and the P MOSFET 5 are
Is turned on, the N MOSFET 3 is turned on. Therefore, the logic output signal Q = V _{EE of} the signal output terminal OUT1 and the logic output signal rQ = V _CC of the signal output terminal OUT2 are converted into logic signals of the high voltage system level. Further, A = “L” (of the negative side line voltage V _SS ), B = “H” (the positive side line voltage V _CC)
When the logic input signal of () is input, the logic output signal Q = V _EE , rQ = V _CC , A =
Logic output signals Q = V _EE and rQ = V _CC when the logic input signals are “H” and B = “L”, and logic outputs when the logic input signals are A = “L” and B = “L” Signal Q = V _CC , rQ = V
Converted to high-voltage level logic signal of _EE .

Further, in FIG. 2, the positive power supply conversion level shift circuit has a high-voltage positive power supply line V.
_{Between the D} (power supply line voltage V _DD ) and the negative power supply line V _S (power supply line voltage V _SS ), their source and drain,
Source / drain and drain / source connected in series P MOSFET 10, N MOSFET 11 and N MOSFET 12, and P MOSFET in which the source / drain and drain / source are connected in series to these series connected MOSFETs.
7 and N MOSFET 9, and N MOSFET 8 whose drain and source are respectively connected in parallel, and the drain of P MOSFET 7 and the N MOSFET
The drain of 8 is connected to the drain of P MOSFET 10 and the N MOSFET at the gate of P MOSFET 10.
The drain of 8 is connected to the gate of the P MOSFET 7, the gate of the N MOSFET 8 is connected to the signal input terminal IN1, the gate of the N MOSFET 9 is connected to the signal input terminal IN2, the gate of the P MOSFET 11 is connected to the signal input terminal IN3, and The gate of the MOSFET 12 is connected to the gate of the signal input terminal IN4,
The drain of ET7 is connected to the signal output terminal OUT1 by P MO
The drains of the SFET 10 are connected to the signal output terminal OUT2, respectively.

The operation of this level shift circuit is as follows. Now, the low voltage system level A = “H” (of the positive line voltage V _CC ) B is applied to each of the signal input terminals IN1 and IN2.
= "H" (of positive side line voltage V _CC ) of the logic input signal is input to the signal input terminals IN3 and IN4 when the logic input signal A is rA or r of the inverted signal of B.
Input B, N MOSFET 8 and N MOS
FET9 turns on, NMOSFET11 and NMO
The SFET 12 turns off. N MOSFET8 and N
When the MOSFET 9 is turned on, the P MOSFET 10 is turned on, and the N MOSFET 11 and the N MOSF are turned on.
When ET12 is turned off, P MOSFET 7 is turned off. Therefore, the logical output signal Q = V of the signal output terminal OUT1
_SS , the logic output signal of the signal output terminal OUT2 is converted to a high voltage system logic signal of rQ = V _DD . "A" =
When a logical input signal of "L" (for negative side line voltage V _SS ) and B = "H" (for positive side line voltage V _CC ) is input,
By the operation of the same procedure, the logical output signals Q = V _SS , rQ = V _DD
When A = “H” and B = “L”, the logic output signal Q = V _SS , rQ = V _DD , A = “L”, B =
When the logical input signal is “L”, the logical output signal Q = V _DD ,
It is converted into a high voltage system level logic signal of rQ = V _SS .

[0017]

According to the present invention, a logic signal level shift circuit having a small delay time of a logic output signal and a small required area of a semiconductor chip when formed as a semiconductor integrated circuit can be obtained. The effect is extremely large in a circuit such as a liquid crystal driver.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a logic signal level shift circuit of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of a logic signal level shift circuit of the present invention.

FIG. 3 is a circuit diagram showing a first conventional example of a logic signal level shift circuit.

FIG. 4 is a circuit diagram showing a second conventional example of a logic signal level shift circuit.

[Explanation of symbols]

 1 P MOSFET (first) 2 P MOSFET (second) 3 N MOSFET (first) 4 P MOSFET (third) 5 P MOSFET (fourth) 6 N MOSFET (second) 7 P MOSFET (second) 8 N MOSFET (fourth) 9 N MOSFET (third) 10 P MOSFET (first) 11 N MOSFET (first) 12 N MOSFET (second)

Claims (3)

[Claims] 1. A logic signal level shift circuit for converting a logic signal of a low voltage system level into a logic signal of a high voltage system level, the circuit being provided between a positive side power source line and a negative side power source line of a high voltage system. A first P M whose main terminals are connected in series
OSFET, second P MOSFET and first N MOSFET
MOSFET and MOSFET connected in series
A third P whose main terminals are connected in parallel with each other in series.
A MOSFET and a second N MOSFET, and a fourth P MOSFET in which a main terminal of the third P MOSFET is connected in parallel to a main terminal of the third P MOSFET.
Main terminal of the P MOSFET and the second NMOSF
The connection point of the main terminal of ET is connected to the gate of the first N MOSFET, and the connection point of the main terminal of the second P MOSFET and the main terminal of the first N MOSFET is connected to the second
A level shift circuit for logic signals, characterized in that the level shift circuit is connected to the gate of the N MOSFET. 2. A logic signal level shift circuit for converting a low voltage system level logic signal into a high voltage system level logic signal, wherein the high voltage system level shift circuit is provided between a high voltage system positive side power supply line and a negative side power supply line. A first P M whose main terminals are connected in series
OSFET, first N MOSFET and second N MOSFET
MOSFET and MOSFET connected in series
A second P whose main terminals are connected in series in parallel with
A MOSFET and a third N MOSFET, and a fourth N MOSFET whose main terminal is connected in parallel to the main terminal of the third N MOSFET.
Main terminal of the P MOSFET and the third P MOSF
The connection point of the main terminal of ET is connected to the gate of the first P MOSFET, and the connection point of the first P MOSFET and the first N MOSFET is connected to the second P MOS.
Logic signal level shift circuit characterized by being connected to the gate of an FET 3. The logic signal level shift circuit according to claim 1, wherein the level shift circuit is formed as a semiconductor integrated circuit.