JPH06244526A - Manufacture of printed-wiring board - Google Patents

Manufacture of printed-wiring board

Info

Publication number
JPH06244526A
JPH06244526A JP5477193A JP5477193A JPH06244526A JP H06244526 A JPH06244526 A JP H06244526A JP 5477193 A JP5477193 A JP 5477193A JP 5477193 A JP5477193 A JP 5477193A JP H06244526 A JPH06244526 A JP H06244526A
Authority
JP
Japan
Prior art keywords
substrate
hole
wiring board
printed wiring
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5477193A
Other languages
Japanese (ja)
Other versions
JP3415186B2 (en
Inventor
Taketo Tsukamoto
健人 塚本
Toshio Ofusa
俊雄 大房
Sotaro Toki
荘太郎 土岐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP5477193A priority Critical patent/JP3415186B2/en
Publication of JPH06244526A publication Critical patent/JPH06244526A/en
Application granted granted Critical
Publication of JP3415186B2 publication Critical patent/JP3415186B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To provide the manufacturing method, of a printed-wiring board, wherein it can form a continuity hole in the board with good accuracy and it's productivity is high. CONSTITUTION:Parts in which a continuity hole is to be formed in metal thin- film layers 4, 5 formed on both faces of a board 1 which has been formed in such a way that a glass cloth 2 has been impregnated with a resin 3 and hardened are removed. Then, while a magnetic field is being applied in the vertical direction of the board 1, the resin 3 on the board is removed by a reactive ton etching operation 6, a hole is worked, a plating operation 7 is executed to the hole which has been made, and the continuity hole 8 is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はプリント配線基板の製造
方法に関するもので、特に基板の表面と裏面との電気的
導通を取るための表裏貫通した導通孔または任意の導体
層と他の導体層との電気的導通を取るための非貫通の導
通孔を形成する方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a through hole which penetrates the front surface and the back surface or an arbitrary conductor layer and another conductor layer for electrically connecting the front surface and the back surface of the board. The present invention relates to a method of forming a non-penetrating conduction hole for establishing electrical conduction with.

【0002】[0002]

【従来の技術】プリント配線基板では、基板の表面の配
線パターンと裏面の配線パターンとの電気的導通を取る
ための手段として、基板に貫通孔をあけ、これをめっき
で導通処理して表裏貫通した導通孔を形成する方法が従
来一般に行われている。
2. Description of the Related Art In a printed wiring board, a through hole is formed in the board as a means for establishing electrical continuity between the wiring pattern on the front surface of the board and the wiring pattern on the back surface of the board. Conventionally, a method of forming such a through hole is generally performed.

【0003】[0003]

【発明が解決しようとする課題】ところで、上記の基板
に貫通孔をあける方法としては従来はドリルを用いて行
なうのが一般的である。
By the way, as a method of forming a through hole in the above-mentioned substrate, a drill is generally used conventionally.

【0004】しかしながら、このようなドリルを用いた
機械的な孔あけによる手法では、加工時に基板にストレ
スがかかり、また削りかすが発生するため、めっきを行
なう前にこれを十分に取り除いておかないと貫通孔内の
めっきの不着による断線が生じやすく、信頼性に欠ける
結果となる。また、最近の電子機器への高機能化・多機
能化・小型化の要求に対応して複数の素子を一つの標準
パッケージ内に納めたより高密度の実装が求められてお
り、このような高密度実装を行なうためにはますます小
さな径の貫通孔を精度良く形成する必要があるが、ドリ
ルによる機械的な孔あけでは精度上の限界がある。しか
も、1つの基板に何箇所もの貫通孔を形成する場合に
は、機械的な孔あけではきわめて時間がかかることにな
る。
However, in such a method using mechanical drilling using a drill, stress is applied to the substrate during processing and shavings are generated. Therefore, this must be sufficiently removed before plating. A disconnection due to non-adhesion of plating in the through hole is likely to occur, resulting in lack of reliability. In addition, in response to the recent demand for higher functionality, higher functionality, and smaller size of electronic equipment, higher density packaging that houses multiple elements in a single standard package is required. In order to perform high-density mounting, it is necessary to form through holes with smaller and smaller diameters with high accuracy, but mechanical drilling with a drill has a limit in accuracy. Moreover, when forming a number of through holes in one substrate, mechanical drilling takes a very long time.

【0005】一方、特公平 2-57356号公報には、CF4
及びO2 を含む反応性ガス雰囲気中でプラズマエッチン
グにより貫通孔を形成する方法が開示されているが、エ
ッチング速度が非常に遅く加工に時間がかかること、サ
イドエッチ量が大きく貫通孔内の端部のめっきが着きに
くくめっき不着による断線が生じやすいこと等の問題が
ある。
On the other hand, Japanese Patent Publication No. 2-57356 discloses CF 4
And a method of forming a through hole by plasma etching in a reactive gas atmosphere containing O 2 is disclosed. However, the etching rate is very slow, the processing takes a long time, the side etch amount is large, and the end portion in the through hole is large. There is a problem that the plating of the part is hard to be adhered, and the disconnection is likely to occur due to the non-adhesion of the plating.

【0006】本発明は上記従来の問題に鑑みなされたも
ので、基板に導通孔を精度良く形成出来、しかも生産性
の高いプリント配線基板の製造方法を提供することを目
的とする。
The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a method of manufacturing a printed wiring board, which is capable of forming a conductive hole in a board with high accuracy and has high productivity.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するた
め、本発明は、プリント配線基板を構成する少なくとも
一層の基板に表面と裏面との電気的導通を取るための表
裏貫通した導通孔または任意の導体層と他の導体層との
電気的導通を取るための非貫通の導通孔を形成するプリ
ント配線基板の製造方法において、前記基板に設けた金
属薄膜層の導通孔を形成する部分を除去し、次いで磁場
を前記基板の垂直方向にかけながら反応性イオンエッチ
ングにより前記基板の孔あけ加工を行ない、しかる後め
っきによる導通処理を行なうことにより導通孔を形成す
ることを特徴としている。
In order to achieve the above object, the present invention provides a through-hole or an optional through-hole for electrically connecting the front surface and the back surface of at least one layer of a printed wiring board. In a method of manufacturing a printed wiring board for forming a non-penetrating conduction hole for electrically connecting a conductor layer with another conductor layer, a portion of the metal thin film layer provided on the substrate where the conduction hole is formed is removed. Then, a hole is formed in the substrate by reactive ion etching while applying a magnetic field in the vertical direction of the substrate, and then a conduction process is performed by plating to form a conduction hole.

【0008】以下、本発明を詳述する。The present invention will be described in detail below.

【0009】図1は本発明に係るプリント配線基板の製
造方法の一例を工程順に示す断面図である。
FIG. 1 is a sectional view showing an example of a method of manufacturing a printed wiring board according to the present invention in the order of steps.

【0010】同図(a)に示すように、使用する基板1
はガラスクロス2に例えばエポキシ、ポリイミド等の樹
脂3を含浸させ硬化させて出来たもので、これによって
必要な材料強度を持たせている。また、基板1の両面に
はそれぞれ銅などの導電性の金属薄膜層4,5を有して
いる。該金属薄膜層4,5はそれぞれ基板1の表面と裏
面の配線パターン等を形成する。
As shown in FIG. 1A, the substrate 1 to be used
Is made by impregnating the glass cloth 2 with a resin 3 such as epoxy or polyimide and curing it, thereby giving a necessary material strength. Further, conductive metal thin film layers 4 and 5 such as copper are provided on both surfaces of the substrate 1, respectively. The metal thin film layers 4 and 5 respectively form wiring patterns on the front surface and the back surface of the substrate 1.

【0011】次に、同図(b)に示すように、上記基板
1の両面に設けた金属薄膜層4,5の導通孔を形成する
部分をフォトエッチングによるパターニングで除去す
る。すなわち、金属薄膜層4,5の表面に感光性樹脂を
塗布又は電着し、次いでパターン露光を行ない、これを
現像してレジストパターンを形成し、露出した部分の金
属薄膜層をエッチングで除去して、最後にレジストパタ
ーンを除去することにより、金属薄膜層4,5をパター
ニングする。
Next, as shown in FIG. 1B, the portions of the metal thin film layers 4 and 5 provided on both surfaces of the substrate 1 where the conductive holes are formed are removed by patterning by photoetching. That is, a photosensitive resin is applied or electrodeposited on the surfaces of the metal thin film layers 4 and 5, and then pattern exposure is performed, which is developed to form a resist pattern, and the exposed metal thin film layers are removed by etching. Finally, the metal thin film layers 4 and 5 are patterned by removing the resist pattern.

【0012】次いで、同図(c)に示すように、基板1
の孔あけ加工を行なう。該孔あけ加工は、先にパターニ
ングした金属薄膜層4,5をマスクにして、磁場を基板
1の垂直方向にかけながら反応性イオンエッチング6に
より行なう。
Then, as shown in FIG.
Perform the drilling process. The hole forming process is performed by reactive ion etching 6 while applying a magnetic field in the vertical direction of the substrate 1 by using the previously patterned metal thin film layers 4 and 5 as a mask.

【0013】図4にかかる反応性イオンエッチングを行
なう装置の概略模式図を示した。2枚の平行平板電極
9,10のうちのカソード10側にNとSの2枚の永久
磁石11を図示するように配置したもので、加工する基
板1をカソード10上に設置する。また、導入ガスとし
てはCF4 及びO2 を含む反応性ガスを使用する。これ
によって、磁場を基板1の垂直方向にかけながらプラズ
マを生じさせ、反応性イオンエッチングを行なう。この
方法によると、エッチング速度が大きく、サイドエッチ
量は小さいので、短時間で精度の良い加工を行える。な
お、導入ガスの流量、ガス圧、出力等は任意に適当な値
に設定されるが、特にガス圧は 0.1Torr以上の高圧力
とした方がエッチング速度の点では好ましい。
FIG. 4 shows a schematic diagram of an apparatus for performing reactive ion etching. One of the two parallel plate electrodes 9 and 10 is provided with two permanent magnets 11 of N and S on the cathode 10 side, and the substrate 1 to be processed is placed on the cathode 10. A reactive gas containing CF 4 and O 2 is used as the introduction gas. As a result, plasma is generated while applying a magnetic field in the vertical direction of the substrate 1, and reactive ion etching is performed. According to this method, since the etching rate is high and the side etching amount is small, it is possible to perform accurate processing in a short time. The flow rate, gas pressure, output, etc. of the introduced gas are arbitrarily set to appropriate values, but it is particularly preferable to set the gas pressure to a high pressure of 0.1 Torr or higher in terms of etching rate.

【0014】このような磁場を基板1の垂直方向にかけ
ながら行なう反応性イオンエッチング6により、基板1
を構成する樹脂3は除去され、ガラスクロス2はエッチ
ングされずにそのまま孔加工部分に露出する。
By the reactive ion etching 6 performed while applying such a magnetic field in the vertical direction of the substrate 1, the substrate 1
The resin 3 constituting the above is removed, and the glass cloth 2 is not etched but is exposed as it is in the hole-processed portion.

【0015】しかる後、同図(d)に示すように、孔あ
けした部分にめっき膜7を施して導通孔8を形成する。
めっきの方法としては無電解めっきと電解めっきの組合
せが特に好適である。なお、上述したように、ガラスク
ロス2は孔加工部分に露出し残存しているが、縦方向と
横方向のガラス繊維の束の間に貫通孔(同図(c)の符
号2aで示す部分)が形成されているので、この貫通孔
の内部にもめっき膜7が形成され、その結果、基板1の
表面と裏面とが電気的に導通する。
After that, as shown in FIG. 3D, a plated film 7 is applied to the holed portion to form a conductive hole 8.
As a plating method, a combination of electroless plating and electrolytic plating is particularly suitable. As described above, the glass cloth 2 is exposed and remains in the hole-processed portion, but there is a through hole (the portion indicated by reference numeral 2a in the same figure (c)) between the bundles of glass fibers in the vertical direction and the horizontal direction. Since it is formed, the plating film 7 is also formed inside this through hole, and as a result, the front surface and the back surface of the substrate 1 are electrically connected.

【0016】図2は本発明に係るプリント配線基板の製
造方法の他の例を工程順に示す断面図であり、図1と同
一箇所には同一符号を付して適宜重複説明を省略する。
FIG. 2 is a sectional view showing another example of the method for manufacturing a printed wiring board according to the present invention in the order of steps. The same portions as those in FIG.

【0017】本製造工程においては、前述のガラスクロ
ス2を用いた基板1の代わりに、アラミド繊維2′にエ
ポキシ、ポリイミド等の樹脂3′を含浸させ硬化させて
出来た基板1′を使用する(図2(a)参照)。なお、
アラミド繊維でなくても適度な剛性を有するものであれ
ば他の繊維状高分子材料を用いても一向に差支えない。
In this manufacturing process, instead of the substrate 1 using the glass cloth 2 described above, a substrate 1'made by impregnating an aramid fiber 2'with a resin 3'such as epoxy or polyimide and curing it is used. (See FIG. 2 (a)). In addition,
Other fibrous polymer materials may be used as long as they are not aramid fibers and have appropriate rigidity.

【0018】次に、同図(b)に示すように、前述と全
く同様にして、上記基板1′の両面に設けた金属薄膜層
4,5の導通孔を形成する部分をフォトエッチングによ
るパターニングで除去する。
Next, as shown in FIG. 2B, the portions of the metal thin film layers 4 and 5 provided on both surfaces of the substrate 1'for forming the conductive holes are patterned by photoetching in the same manner as described above. To remove.

【0019】次いで、同図(c)に示すように、前述と
同様に磁場を基板1′の垂直方向にかけながら反応性イ
オンエッチング6により基板1′の孔あけ加工を行な
う。図示より明らかなように、前述のガラスクロス2を
用いた場合と異なり、基板1′を構成する樹脂3′だけ
でなくアラミド繊維2′も完全にエッチング除去され、
貫通孔を形成する。
Then, as shown in FIG. 3C, the boring of the substrate 1'is performed by the reactive ion etching 6 while applying a magnetic field in the vertical direction of the substrate 1'as described above. As is clear from the figure, unlike the case where the glass cloth 2 is used, not only the resin 3'constituting the substrate 1 ', but also the aramid fiber 2'is completely removed by etching.
A through hole is formed.

【0020】しかる後、同図(d)に示すように、出来
た貫通孔に無電解めっき等によるめっき膜7を施して導
通孔8を形成する。
Thereafter, as shown in FIG. 3D, the through hole thus formed is provided with a plating film 7 by electroless plating or the like to form a conduction hole 8.

【0021】このようにアラミド繊維2′等を用いた場
合には、上述のエッチングによる孔あけ工程においてア
ラミド繊維2′等も完全にエッチング除去された貫通孔
が形成されるため、前述のガラスクロス2を用いた場合
のように例えば孔あけした部分にガラスクロス2の貫通
孔2aが存在していないような小径の導通孔8であって
も全く問題なく形成できるという利点がある。
When the aramid fibers 2'and the like are used as described above, since the aramid fibers 2'and the like are completely etched and removed to form the through holes in the above-described etching step, the glass cloth described above is formed. There is an advantage that even a small-diameter conduction hole 8 in which the through hole 2a of the glass cloth 2 does not exist in the holed portion as in the case of using 2 can be formed without any problem.

【0022】また、本発明は上述のような表裏貫通した
導通孔だけでなく、複数の導体層のうちの任意の導体層
と他の導体層との電気的導通を取るための非貫通の導通
孔(一般にVIAホールとも呼ばれている)も形成でき
る。図3はその一例を示したもので、金属薄膜層4,
4′,4″において金属薄膜層4と4′及び4′と4″
のそれぞれの電気的導通を取るための非貫通の導通孔
8′を形成した場合を示している。
Further, the present invention is not limited to the above-mentioned conduction holes penetrating through the front and back surfaces, but also non-penetrating conduction for electrically connecting any conductor layer of a plurality of conductor layers to another conductor layer. Holes (also commonly called VIA holes) can also be formed. FIG. 3 shows an example thereof, which includes the metal thin film layer 4,
4 ', 4 "at metal thin film layers 4 and 4' and 4 'and 4"
The case where a non-penetrating conduction hole 8'for forming electrical continuity is formed.

【0023】[0023]

【作用】本発明は、基板に導通孔を形成するに際し、磁
場を基板の垂直方向にかけながら反応性イオンエッチン
グにより基板の孔あけ加工を行なう。
According to the present invention, when forming the conductive hole in the substrate, the hole is formed in the substrate by reactive ion etching while applying a magnetic field in the vertical direction of the substrate.

【0024】これによって、小さな径の導通孔であって
も精度良く形成出来、しかもエッチング速度が早いため
加工に要する時間が少なくて済むようになる。
As a result, even a small-diameter conduction hole can be formed with high accuracy, and since the etching rate is high, the time required for processing can be reduced.

【0025】さらに、孔あけ加工のサイドエッチ量が小
さいため、導通孔内のめっき不着による断線等の不具合
は生じないので信頼性が非常に高くなる。
Further, since the side etching amount in the drilling process is small, problems such as disconnection due to non-sticking of the plating in the conductive holes do not occur, so the reliability is very high.

【0026】[0026]

【実施例】以下、実施例により本発明を更に具体的に説
明する。
The present invention will be described in more detail with reference to the following examples.

【0027】実施例−1 ガラスクロスにエポキシ樹脂を含浸させ硬化させてなる
厚さ 100μmのガラスエポキシ板の両面にそれぞれ厚さ
18μmの銅箔層を設けた銅張積層基板の表面及び裏面に
感光性樹脂「フォトED P−1000(商品名)」
(日本ペイント(株)製)を電着により付着させ、これ
にマスク露光法により所定の円孔のパターンを焼き付
け、メタケイ酸ソーダ溶液で現像し、露光した部分の上
記感光性樹脂を除去した。次いで、塩化第2鉄溶液で露
出部の銅箔をエッチングし、5%水酸化ナトリウム溶液
で残存する感光性樹脂を剥離し、水洗、乾燥することに
よりガラスエポキシ板の両面に導通孔を形成する部分の
銅箔を除去した孔径 0.6mmのパターンを形成した。
Example 1 A glass epoxy plate having a thickness of 100 μm obtained by impregnating a glass cloth with an epoxy resin and curing the same was formed on each side.
Photosensitive resin "Photo ED P-1000 (trade name)" on the front and back surfaces of a copper clad laminated substrate provided with a copper foil layer of 18 μm
(Manufactured by Nippon Paint Co., Ltd.) was adhered by electrodeposition, a pattern of predetermined circular holes was baked on this by a mask exposure method, and developed with a sodium metasilicate solution to remove the above-mentioned photosensitive resin in the exposed portion. Next, the exposed copper foil is etched with a ferric chloride solution, the remaining photosensitive resin is peeled off with a 5% sodium hydroxide solution, washed with water, and dried to form conductive holes on both surfaces of the glass epoxy plate. A pattern having a hole diameter of 0.6 mm was formed by removing the copper foil in a portion.

【0028】次に、出来た試料を日本真空技術(株)製
マグネットエンハンスRIE装置(構造は図4に示した
ものと同様)のチャンバー内に設置し、以下の条件でエ
ッチングによる基板の孔あけ加工を行なった。このとき
の基板のエポキシ樹脂層のエッチング速度はおよそ5μ
m/分であった。なお、ガラスクロスはエッチングされ
ないが、ヤーン(ガラス繊維の束)間に約 0.1mm角の貫
通孔が複数個形成されていた。処理条件 導入ガス :O2 (流量60SCCM)+CF4 (流量20
SCCM) 圧 力 : 400mTorr 高周波出力: 450W
Next, the prepared sample is placed in the chamber of a magnet enhancement RIE device manufactured by Japan Vacuum Technology Co., Ltd. (the structure is the same as that shown in FIG. 4), and a hole is formed in the substrate by etching under the following conditions. Processing was performed. At this time, the etching rate of the epoxy resin layer of the substrate is about 5μ.
It was m / min. Although the glass cloth was not etched, a plurality of through holes each having a size of about 0.1 mm square were formed between the yarns (a bundle of glass fibers). Processing conditions Introduction gas: O 2 (flow rate 60 SCCM) + CF 4 (flow rate 20
SCCM) Pressure: 400mTorr High frequency output: 450W

【0029】しかる後、チャンバー内から試料を取り出
し、前処理を実施後、めっき液「スルカップ(商品
名)」(上村工業(株)製)に浸漬させて無電解銅めっ
き(55℃,3分)を行ない、さらに電解銅めっきでめっ
き厚約30μmの導通孔を形成した。
Thereafter, the sample was taken out of the chamber, pretreated, and then immersed in a plating solution "Sulcup (trade name)" (manufactured by Uemura Kogyo Co., Ltd.) for electroless copper plating (55 ° C, 3 minutes). ), And a conductive hole having a plating thickness of about 30 μm was formed by electrolytic copper plating.

【0030】実施例−2 実施例−1のガラスクロスの代わりにアラミド繊維「ケ
ブラー(商品名)」(デュポン社製)を用いた銅張積層
基板の両面に実施例−1と全く同様にして導通孔を形成
する部分の銅箔を除去したパターンを形成した。
Example-2 The same procedure as in Example-1 was performed on both sides of a copper-clad laminated substrate using aramid fiber "Kevlar (trade name)" (manufactured by DuPont) in place of the glass cloth of Example-1. A pattern was formed by removing the copper foil in the portion where the conduction hole is formed.

【0031】次に、この試料を実施例−1と全く同様の
条件にてエッチングを行ない基板の孔あけ加工を行なっ
た。このときの基板のエッチング速度は約5μm/分で
あり、アラミド繊維も完全にエッチング除去された貫通
孔が形成された。
Next, this sample was subjected to etching under the same conditions as in Example 1 to perforate the substrate. The etching rate of the substrate at this time was about 5 μm / min, and the aramid fiber was completely removed by etching to form a through hole.

【0032】しかる後、実施例−1と同様に、出来た貫
通孔の銅めっきを行ない、導通孔を形成した。
Then, as in Example-1, the through holes thus formed were plated with copper to form conductive holes.

【0033】実施例−3 アラミド繊維(前出)にエポキシ樹脂を含浸させ硬化さ
せて出来たアラミドエポキシ板と銅箔層とを図3に示す
如く順次積層し全体が5層からなる銅張積層基板の表面
及び裏面のそれぞれに実施例−1と全く同様にして導通
孔を形成する部分の銅箔を除去したパターン(表面と裏
面のパターンの位置は異なっている)を形成した。
Example 3 An aramid epoxy plate made by impregnating an aramid fiber (described above) with an epoxy resin and curing it and a copper foil layer were sequentially laminated as shown in FIG. Patterns (the positions of the patterns on the front surface and the back surface are different) were formed on the front surface and the back surface of the substrate, respectively, in the same manner as in Example 1 from which the copper foil in the portions where the conductive holes were formed was removed.

【0034】次に、この試料を実施例−1と全く同様の
条件にてエッチングを行ない基板の孔あけ加工を行なっ
た。このとき、基板の表面及び裏面のそれぞれからまん
中の銅箔層に到る非貫通孔が形成された(図3参照)。
Next, this sample was etched under the same conditions as in Example 1 to perforate the substrate. At this time, a non-through hole was formed from each of the front surface and the back surface of the substrate to the middle copper foil layer (see FIG. 3).

【0035】しかる後、実施例−1と同様に、出来た孔
の銅めっきを行ない、導通孔(VIAホール)を形成し
た。
Thereafter, as in the case of Example 1, the holes thus formed were plated with copper to form conductive holes (VIA holes).

【0036】[0036]

【発明の効果】以上詳細に説明したように、本発明によ
れば、基板に設けた金属薄膜層の導通孔を形成する部分
を除去し、次いで磁場を前記基板の垂直方向にかけなが
ら反応性イオンエッチングにより前記基板の孔あけ加工
を行ない、しかる後めっきによる導通処理を行なうこと
によって、基板の表面と裏面との電気的導通を取るため
の導通孔を形成するようにしたので、小さな径の導通孔
であっても精度良く形成することが出来る。特に最近の
高密度実装によりますます小径の導通孔を精度良く形成
することが求められており、本発明はこの要求に適う優
れた方法である。
As described in detail above, according to the present invention, the portion of the metal thin film layer on the substrate which forms the through hole is removed, and then the reactive ion is applied while applying a magnetic field in the vertical direction of the substrate. Since a hole is formed in the substrate by etching, and then a conduction process is performed by plating to form a conduction hole for electrical conduction between the front surface and the back surface of the substrate, a conduction of a small diameter is performed. Even holes can be formed with high precision. In particular, due to recent high-density mounting, it is required to form conductive holes of smaller diameter with higher precision, and the present invention is an excellent method that meets this requirement.

【0037】しかも、エッチング速度が早いため、基板
の孔あけ加工に要する時間が少なくて済むようになり、
生産性が著しく向上する。
Moreover, since the etching rate is high, the time required for boring the substrate can be shortened.
Productivity is significantly improved.

【0038】さらに、基板の孔あけ加工のサイドエッチ
量が小さいため、導通孔内のめっき不着による断線等の
不具合は全く生じないので出来た製品の信頼性が非常に
高くなる。
Further, since the side etching amount of the hole forming process of the substrate is small, there is no problem such as disconnection due to non-adhesion of plating in the conduction hole, so that the reliability of the manufactured product is very high.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のプリント配線基板の製造方法の一例を
工程順に示す断面図である。
FIG. 1 is a cross-sectional view showing an example of a method for manufacturing a printed wiring board of the present invention in the order of steps.

【図2】本発明のプリント配線基板の製造方法の他の例
を工程順に示す断面図である。
FIG. 2 is a cross-sectional view showing another example of the method for manufacturing a printed wiring board of the present invention in the order of steps.

【図3】本発明のプリント配線基板の製造方法のその他
の例を工程順に示す断面図である。
FIG. 3 is a cross-sectional view showing another example of the method for manufacturing a printed wiring board of the present invention in the order of steps.

【図4】本発明に使用する反応性イオンエッチング装置
の概略模式図である。
FIG. 4 is a schematic diagram of a reactive ion etching apparatus used in the present invention.

【符号の説明】[Explanation of symbols]

1,1′ 基板 2 ガラスクロス 2′ アラミド繊維 3,3′ 樹脂 4,5 金属薄膜層 6 イオンエッチング 7 めっき膜 8 導通孔 9 アノード 10 カソード 11 永久磁石 1,1 'Substrate 2 Glass cloth 2'Aramid fiber 3,3' Resin 4,5 Metal thin film layer 6 Ion etching 7 Plating film 8 Conducting hole 9 Anode 10 Cathode 11 Permanent magnet

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 プリント配線基板を構成する少なくとも
一層の基板に表面と裏面との電気的導通を取るための表
裏貫通した導通孔または任意の導体層と他の導体層との
電気的導通を取るための非貫通の導通孔を形成するプリ
ント配線基板の製造方法において、前記基板に設けた金
属薄膜層の導通孔を形成する部分を除去し、次いで磁場
を前記基板の垂直方向にかけながら反応性イオンエッチ
ングにより前記基板の孔あけ加工を行ない、しかる後め
っきによる導通処理を行なうことにより導通孔を形成す
ることを特徴とするプリント配線基板の製造方法。
1. A conductive hole penetrating through the front surface and the back surface for electrically connecting the front surface and the back surface to at least one substrate constituting a printed wiring board or electrically connecting the conductor layer to another conductor layer. In the method of manufacturing a printed wiring board for forming a non-penetrating conductive hole for removing a portion of the metal thin film layer on the substrate where the conductive hole is formed, the reactive ion is applied while applying a magnetic field in the vertical direction of the substrate. A method for manufacturing a printed wiring board, characterized in that a hole is formed in the substrate by etching, and then a conduction process is performed by plating to form a conduction hole.
【請求項2】 前記基板はガラスクロスに樹脂を含浸さ
せたものを使用することを特徴とする請求項1記載のプ
リント配線基板の製造方法。
2. The method of manufacturing a printed wiring board according to claim 1, wherein the substrate is a glass cloth impregnated with a resin.
【請求項3】 前記基板はアラミド繊維等の繊維状高分
子材料に樹脂を含浸させたものを使用することを特徴と
する請求項1記載のプリント配線基板の製造方法。
3. The method for manufacturing a printed wiring board according to claim 1, wherein the substrate is a fibrous polymer material such as aramid fiber impregnated with a resin.
JP5477193A 1993-02-19 1993-02-19 Manufacturing method of printed wiring board Expired - Fee Related JP3415186B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5477193A JP3415186B2 (en) 1993-02-19 1993-02-19 Manufacturing method of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5477193A JP3415186B2 (en) 1993-02-19 1993-02-19 Manufacturing method of printed wiring board

Publications (2)

Publication Number Publication Date
JPH06244526A true JPH06244526A (en) 1994-09-02
JP3415186B2 JP3415186B2 (en) 2003-06-09

Family

ID=12980038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5477193A Expired - Fee Related JP3415186B2 (en) 1993-02-19 1993-02-19 Manufacturing method of printed wiring board

Country Status (1)

Country Link
JP (1) JP3415186B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014135516A (en) * 2008-07-09 2014-07-24 Semiconductor Energy Lab Co Ltd Method of manufacturing semiconductor device
WO2014181923A1 (en) * 2013-05-07 2014-11-13 주식회사 엠디에스 Method for forming substrate hole and apparatus for forming substrate hole

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014135516A (en) * 2008-07-09 2014-07-24 Semiconductor Energy Lab Co Ltd Method of manufacturing semiconductor device
WO2014181923A1 (en) * 2013-05-07 2014-11-13 주식회사 엠디에스 Method for forming substrate hole and apparatus for forming substrate hole

Also Published As

Publication number Publication date
JP3415186B2 (en) 2003-06-09

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