JPH06224553A - Manufacture of multilayer printed board - Google Patents

Manufacture of multilayer printed board

Info

Publication number
JPH06224553A
JPH06224553A JP866993A JP866993A JPH06224553A JP H06224553 A JPH06224553 A JP H06224553A JP 866993 A JP866993 A JP 866993A JP 866993 A JP866993 A JP 866993A JP H06224553 A JPH06224553 A JP H06224553A
Authority
JP
Japan
Prior art keywords
layer
copper foil
core material
printed wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP866993A
Other languages
Japanese (ja)
Inventor
Kiyoshi Hyodo
清志 兵頭
Toyomitsu Amada
豊光 天田
Akitaka Nakayama
明隆 中山
Yonezo Maruyama
米蔵 丸山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP866993A priority Critical patent/JPH06224553A/en
Publication of JPH06224553A publication Critical patent/JPH06224553A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To prevent layer deviation by using core material which has four or less layers with an internal layer circuit which is laminated by masslamination system and laminating outer layer copper foil on the top and bottom by pin lamination system. CONSTITUTION:Core material 20 is formed of four layers by mass lamination system. The core material 20 has an internal layer circuit L3 on the one plane of the internal insulating layer and an internal layer circuit L4 on the other plane. Copper coil 20a is adhered on the front plane of the insulating layer on the external side of the internal layer circuit L3 and copper foil 2Ob is adhered on the front plane of the insulating layer on the external side of the internal layer circuit L4. A reference pin 11 is permitted to fit in each reference hole 10, an external layer foil 4, a prescribed sheets of prepreg P, the core material 20, an external layer copper foil 3 and a pressing plate 14 are placed on a pressing plate 13 in such order. Then, the layers are heated and pressurized by heat press to be adhered and cured and a six layer printed board provided with the internal layer circuits L2, L3, L4 and L5 in the internal layer, the external layer copper foil 3 adhered on the front plane and the external layer copper foil 4 adhered on the rear plane is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多層印刷配線板の製造
方法に関する。多層印刷配線板の積層方法には、基準ピ
ンを用い積層形の間に内層パターンをもったコア材とプ
リプレグと外層用銅箔とを重ね、熱プレスにより加熱・
加圧を行い、接着・キュアさせるピンラミネーション方
式と、基準ピンを用いることなく加熱・加圧を行い、接
着・キュアさせるマスラミネーション方式とがある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board. To laminate a multilayer printed wiring board, a reference pin is used to stack a core material having an inner layer pattern, a prepreg, and an outer layer copper foil between the laminated layers, and heat is applied by hot pressing.
There are a pin lamination method in which pressure is applied to bond and cure, and a mass lamination method in which heating and pressure are applied to bond and cure without using a reference pin.

【0002】マスラミネーション方式は、所望に大きい
定尺の銅張積層板を用いることで、多層印刷配線板を多
数個取りすることができ安価である。しかし、積層精度
(各層間の位置合わせ精度)が低いため、小径ビア, I
VH(Interstial Via Hole) , 或いは微細パターンを有
する多層印刷配線板に適用すると層ずれが発生すること
が多い。
The mass lamination method is inexpensive because a large number of multi-layer printed wiring boards can be obtained by using a copper clad laminate having a desired large size. However, since the stacking accuracy (positioning accuracy between layers) is low, small vias, I
When applied to a VH (Interstial Via Hole) or a multilayer printed wiring board having a fine pattern, a layer shift often occurs.

【0003】したがって、装置メーカーが、4層程度ま
での多層印刷配線板を必要とする場合は、積層メーカー
からマスラミネーション方式で製造した安価な多層印刷
配線板を購入し、購入後に表面層の回路形成を行って、
所望の搭載部品を実装している。
Therefore, when a device maker requires a multilayer printed wiring board of up to about four layers, an inexpensive multilayer printed wiring board manufactured by a mass lamination method is purchased from a laminated maker, and after the purchase, the circuit of the surface layer is manufactured. Forming,
The desired mounting parts are mounted.

【0004】一方、ピンラミネーション方式は、マスラ
ミネーション方式に較べてコスト高ではあるが、積層精
度が高精度である。したがって、従来小径ビア, IV
H, 或いは微細パターンを有する多層印刷配線板は、積
層メーカーから購入することなく、装置メーカーがピン
ラミネーション方式で自社製造し搭載部品を実装してい
る。
On the other hand, the pin lamination method is higher in cost than the mass lamination method, but the stacking accuracy is high. Therefore, conventional small-diameter vias, IV
A multi-layer printed wiring board having an H or fine pattern is manufactured by a device manufacturer in-house by a pin lamination method and mounted components are not purchased from a laminated manufacturer.

【0005】[0005]

【従来の技術】以下6層の多層印刷配線板を例にして、
図5,6を参照しながら装置メーカーの従来の製造方法
(ピンラミネーション方式)について説明する。
2. Description of the Related Art A six-layer printed wiring board will be described below as an example.
A conventional manufacturing method (pin lamination method) of a device manufacturer will be described with reference to FIGS.

【0006】図において1は、基材の表面に銅箔1aが、
裏面に銅箔1bがそれぞれ張着された両面銅張積層板であ
る。銅箔の箔厚は35μm 〜70μm であり、両面銅張積層
板の板厚は、多層印刷配線板の層数により異なるが、6
層の場合はほぼ0.25mm、12層の場合はほぼ0.1mm であ
る。
In FIG. 1, reference numeral 1 denotes a copper foil 1a on the surface of the base material.
A double-sided copper-clad laminate having a copper foil 1b adhered to the back surface thereof. The copper foil has a thickness of 35 μm to 70 μm, and the thickness of the double-sided copper-clad laminate varies depending on the number of layers of the multilayer printed wiring board.
The thickness is approximately 0.25 mm in the case of layers and approximately 0.1 mm in the case of 12 layers.

【0007】2は、基材の表面に銅箔2aが、裏面に銅箔
2bがそれぞれ張着された、両面銅張積層板1と同寸法の
両面銅張積層板である。3,4は箔厚が0.18μm 程度の
外形が両面銅張積層板1に等しい外層用銅箔であって、
外層用銅箔3及び4はそれぞれの4隅に基準孔10を穿孔
してある。
No. 2 is a copper foil 2a on the surface of the base material and a copper foil 2a on the back surface.
2b is a double-sided copper-clad laminate having the same dimensions as the double-sided copper-clad laminate 1, each of which is adhered. 3 and 4 are copper foils for outer layers whose foil thickness is about 0.18 μm and whose outer shape is equal to that of the double-sided copper clad laminate 1.
The outer layer copper foils 3 and 4 have reference holes 10 at their four corners.

【0008】Pは、外層用銅箔と両面銅張積層板の間に
介在して両者を接着する所望の厚さのプリプレグであ
る。13は、熱プレスの下プレートに固着する押圧板であ
り、14は熱プレスの上プレートに固着する押圧板であ
る。
P is a prepreg of a desired thickness that is interposed between the outer layer copper foil and the double-sided copper-clad laminate to bond them. Reference numeral 13 is a pressing plate fixed to the lower plate of the heat press, and 14 is a pressing plate fixed to the upper plate of the heat press.

【0009】押圧板13,14 には、4隅のそれぞれに基準
ピン11がしっくりと遊貫する基準孔10を有する。装置メ
ーカーは、ピンラミネーション方式で多層印刷配線板を
製造するものであるが、先ず、図5(A) に図示したよう
に、2枚の両面銅張積層板1,2を積層メーカーから購
入し、図5(B) に図示したように、両面銅張積層板1,
2のそれぞれの4隅に基準孔10を穿孔し、両面にフォト
レジストを塗布した後に、基準孔10に挿着した基準ピン
にハードマスクの基準孔を嵌合し、露光・現像し、エッ
チングして、両面銅張積層板1の表面の銅箔1aを内層回
路L2 にし、裏面の銅箔1bを内層回路L3 とし、さらに
所望によりめっきしてIVH18を設ける。
The pressing plates 13 and 14 have reference holes 10 at each of the four corners, through which reference pins 11 fit smoothly. The equipment maker manufactures a multilayer printed wiring board by the pin lamination method. First, as shown in FIG. 5 (A), two double-sided copper-clad laminates 1 and 2 are purchased from the laminate maker. , As shown in FIG. 5 (B), double-sided copper clad laminate 1,
After forming reference holes 10 in each of the four corners of 2, and applying photoresist on both sides, the reference holes of the hard mask are fitted to the reference pins inserted in the reference holes 10, exposed, developed, and etched. Te, and the copper foil 1a of the double-sided copper clad laminate 1 surface to the inner layer circuit L 2, and the back surface of the copper foil 1b with the inner layer circuit L 3, provided IVH18 further plated desired.

【0010】また、同様にして他の両面銅張積層板2の
表面の銅箔2aを所望の内層回路L4とし、裏面の銅箔2b
を所望の内層回路L5 としている。次に、図5(C) に図
示したように、基準ピン11にそれぞれの基準孔10を嵌合
させて、押圧板13上に、外層用銅箔4, 所望枚数(加圧
圧縮された後に所望の層厚の絶縁層が形成されるような
枚数) のプリプレグP, 両面銅張積層板2,所望枚数の
プリプレグP,両面銅張積層板1,所望枚数のプリプレ
グP,外層用銅箔3,押圧板14をこの順に重ねる。
Similarly, the copper foil 2a on the surface of the other double-sided copper-clad laminate 2 is used as a desired inner layer circuit L 4, and the copper foil 2b on the back surface is formed.
Is the desired inner layer circuit L 5 . Next, as shown in FIG. 5 (C), the reference holes 10 are fitted into the reference pins 11, and the outer layer copper foil 4, the desired number of sheets (after being pressed and compressed) are placed on the pressing plate 13. Number of prepregs P, double-sided copper-clad laminate 2, desired number of prepregs P, double-sided copper-clad laminate 1, desired number of prepregs P, outer layer copper foil 3) , The pressing plate 14 is stacked in this order.

【0011】そして熱プレスにより加熱・加圧を行い、
接着・キュアさせて、図6(A) に示す、内層に内層回路
2 ,L3 ,L4 ,L5 を有し、表面に外層用銅箔3が
張着され、裏面に外層用銅箔4が張着された6層の印刷
配線板としている。
Then, heat and pressure are applied by a hot press,
As shown in FIG. 6 (A), after adhesion and curing, the inner layer has inner layer circuits L 2 , L 3 , L 4 , and L 5 , the outer layer copper foil 3 is adhered to the front surface, and the outer layer copper is attached to the back surface. The printed wiring board is a six-layer printed circuit board on which the foil 4 is attached.

【0012】次に、図6(B) に図示したように、基準孔
10に挿着した基準ピンにハードマスクの基準孔を嵌合
し、表面の外層用銅箔3を所望のマスクを用いて露光・
現像し、エッチングして所望の表面回路Ls とし、裏面
の外層用銅箔4をエッチングして所望の裏面回路Lb と
して、6 層の多層印刷配線板を製造している。
Next, as shown in FIG. 6B, a reference hole is formed.
The reference pin of the hard mask is fitted to the reference pin inserted in 10, and the outer layer copper foil 3 is exposed using the desired mask.
A six-layer multilayer printed wiring board is manufactured by developing and etching to form a desired front surface circuit Ls, and etching the back surface outer layer copper foil 4 to form a desired back surface circuit Lb.

【0013】なお、8層の多層印刷配線板は両面銅張積
層板を3枚、10層の多層印刷配線板は両面銅張積層板
を4枚、12層の多層印刷配線板は両面銅張積層板を5
枚をそれぞれ使用して、前述に準じてピンラミネーショ
ン方式で製造している。
The 8-layer multilayer printed wiring board has three double-sided copper-clad laminates, the 10-layer multilayer printed wiring board has four double-sided copper-clad laminates, and the 12-layer multilayer printed-wiring board has double-sided copper-clad laminates. 5 laminated plates
Each piece is used and manufactured by the pin lamination method according to the above.

【0014】[0014]

【発明が解決しようとする課題】ところで、ピンラミネ
ーション方式は前述のように積層精度は高いが、量産的
ではない。したがって上述のようにピンラミネーション
方式で6層以上の多層印刷配線板を製造すると、内層回
路形成工程数が多いことにより納期が長くなるという問
題点があった。
The pin lamination method has high stacking accuracy as described above, but is not mass-produced. Therefore, when a multilayer printed wiring board having 6 or more layers is manufactured by the pin lamination method as described above, there is a problem that the delivery time becomes long due to the large number of inner layer circuit forming steps.

【0015】本発明はこのような点に鑑みて創作された
もので、納期が短縮される多層印刷配線板の製造方法を
提供することを目的としている。
The present invention was created in view of the above points, and it is an object of the present invention to provide a method for manufacturing a multilayer printed wiring board with a short delivery time.

【0016】[0016]

【課題を解決するための手段】上記の目的を達成するた
めに本発明は、図1に例示したように、マスラミネーシ
ョン方式で製造した4層の印刷配線板に基準孔10を設け
てコア材20とし、コア材20の上下にプリプレグPを介し
てそれぞれ外層用銅箔3,4 を、ピンラミネーション方式
により積層する構成とする。
In order to achieve the above object, the present invention provides a core material by providing reference holes 10 in a four-layer printed wiring board manufactured by a mass lamination method as illustrated in FIG. The outer layer copper foils 3 and 4 are laminated on the upper and lower sides of the core material 20 via the prepreg P by a pin lamination method.

【0017】また、図3に例示したように、マスラミネ
ーション方式で製造した3層乃至4層の複数の印刷配線
板に基準孔10を設けてコア材とし、それぞれのコア材間
にプリプレグPが介在し、最上層のコア材の上にプリプ
レグPを介して外層用銅箔3を、最下層のコア材の下に
プリプレグPを介して他の外層用銅箔4を、ピンラミネ
ーション方式により積層する構成とする。
Further, as illustrated in FIG. 3, reference holes 10 are provided in a plurality of printed wiring boards of three to four layers manufactured by a mass lamination method as core materials, and prepregs P are provided between the respective core materials. The outer layer copper foil 3 is laminated on the uppermost core material via the prepreg P, and the other outer layer copper foil 4 is laminated on the lowermost core material via the prepreg P by the pin lamination method. The configuration is

【0018】或いはまた、図4に例示したように、マス
ラミネーション方式で製造した少なくとも一枚の3層乃
至4層の印刷配線板と、両面にパターンが形成された少
なくとも一枚の印刷配線板とを有し、それぞれの印刷配
線板に基準孔10を設けてコア材とし、それぞれのコア材
間にプリプレグPが介在し、最上層のコア材の上にプリ
プレグPを介して外層用銅箔3を、最下層のコア材の下
にプリプレグPを介して他の外層用銅箔4を、ピンラミ
ネーション方式により積層する構成とする。
Alternatively, as shown in FIG. 4, at least one printed wiring board of three to four layers manufactured by a mass lamination method and at least one printed wiring board having a pattern formed on both sides thereof. Each of the printed wiring boards has a reference hole 10 as a core material, and a prepreg P is interposed between the core materials, and the outer layer copper foil 3 is provided on the uppermost core material via the prepreg P. The other outer layer copper foil 4 is laminated under the core material of the lowermost layer through the prepreg P by the pin lamination method.

【0019】[0019]

【作用】本発明によれば、コア材は内層回路は既に形成
されマスラミネーション方式で積層した4層以下のもの
である。そして、4層程度のコア材はマスラミネーショ
ン方式で製造しても、そのコア材内の2つの内層回路層
間の層ずれは殆ど発生しない。
According to the present invention, the core material has four layers or less in which the inner layer circuit is already formed and laminated by the mass lamination method. Even if the core material of about 4 layers is manufactured by the mass lamination method, the layer displacement between the two inner layer circuit layers in the core material hardly occurs.

【0020】本発明はこのようなコア材と外層用銅箔と
を用いて、ピンラミネーション方式にり6層以上の多層
印刷配線板を製造するものである。即ち、積層精度が高
いので、小径ビア, IVH, 或いは微細パターンを有す
る多層印刷配線板に適用して何ら支障がない。
The present invention uses such a core material and an outer layer copper foil to manufacture a multilayer printed wiring board having 6 or more layers by a pin lamination method. That is, since the stacking accuracy is high, there is no problem when applied to a multilayer printed wiring board having a small diameter via, IVH, or a fine pattern.

【0021】一方これらのコア材は、表裏の銅箔をパタ
ーン化して内層回路を設けることでピンラミネーション
方式のコア材として使用されている。したがって、例え
ば6層の多層印刷配線板では従来方法のものに比較し
て、内層回路形成工程が2内層分だけ節減され、10層
の多層印刷配線板では従来方法のものに比較して、内層
回路形成工程が4内層分だけ節減される。よって、内層
回路形成工程数が少ないので納期が短縮される。
On the other hand, these core materials are used as pin lamination type core materials by patterning the copper foils on the front and back to provide inner layer circuits. Therefore, for example, in the case of a 6-layer multilayer printed wiring board, the inner layer circuit forming process is reduced by 2 inner layers as compared with the conventional method, and in the 10-layer multilayer printed wiring board as compared with the conventional method, the inner layer circuit forming process is reduced. The circuit forming process is reduced by four inner layers. Therefore, the number of steps for forming the inner layer circuit is small and the delivery time is shortened.

【0022】また、コア材はピンラミネーション方式で
製造したものであるから、ピンラミネーション方式で製
造した同層数のコア材よりも安価である。したがって、
本発明方法によれば多層印刷配線板の低コスト化が推進
される。
Further, since the core material is manufactured by the pin lamination method, it is cheaper than the core material having the same number of layers manufactured by the pin lamination method. Therefore,
The method of the present invention promotes cost reduction of a multilayer printed wiring board.

【0023】[0023]

【実施例】以下図を参照しながら、本発明を具体的に説
明する。なお、全図を通じて同一符号は同一対象物を示
す。
The present invention will be described in detail with reference to the drawings. The same reference numerals denote the same objects throughout the drawings.

【0024】図1の(A) 〜(D) は、本発明の実施例の製
造工程の前段を示す図、図2の(A),(B) は本発明の実施
例の製造工程の後段を示す図、図3の(A),(B) は本発明
の他の実施例の図、図4の(A),(B) は本発明のさらに他
の実施例の図である。
1 (A) to 1 (D) are views showing a former stage of the manufacturing process of the embodiment of the present invention, and FIGS. 2 (A) and 2 (B) are latter stages of the manufacturing process of the embodiment of the present invention. 3A and 3B are views of another embodiment of the present invention, and FIGS. 4A and 4B are views of yet another embodiment of the present invention.

【0025】図1,2において、20は、マスラミネーシ
ョン方式で製造した4層のコア材である。コア材20は、
内部絶縁層の一方の面に内層回路L3 が形成され、他方
の面に内層回路L4 が形成されている。そして内層回路
3 の外側の絶縁層の表面に銅箔20a (箔厚は35μm 〜
70μm )が張着され、内層回路L4 の外側の絶縁層の表
面に銅箔20b が張着されている。
In FIGS. 1 and 2, 20 is a four-layer core material manufactured by the mass lamination method. The core material 20 is
The inner layer circuit L 3 is formed on one surface of the inner insulating layer, and the inner layer circuit L 4 is formed on the other surface. Then, on the surface of the insulating layer outside the inner layer circuit L 3 , a copper foil 20a (foil thickness of 35 μm
70 μm) and the copper foil 20b is adhered to the surface of the outer insulating layer of the inner layer circuit L 4 .

【0026】また、この内層回路L3 と内層回路L4
形成された面の4隅のそれぞれに、基準孔10の内径に等
しい円形の基準マークS(銅箔をエッチングして形成さ
れたマーク)を設けてある。
Further, circular reference marks S (marks formed by etching a copper foil) having the same inner diameter as the reference hole 10 are formed at each of four corners of the surface on which the inner layer circuit L 3 and the inner layer circuit L 4 are formed. ) Is provided.

【0027】さらにまた、この内層回路L3 と内層回路
4 とを接続するIVH18を設けてある。3,4は箔厚
が0.18μm 程度の外形が両面銅張積層板1に等しい外層
用銅箔であって、外層用銅箔3及び4はそれぞれの4隅
に基準孔10を穿孔してある。
Furthermore, an IVH 18 for connecting the inner layer circuit L 3 and the inner layer circuit L 4 is provided. 3 and 4 are outer layer copper foils having an outer thickness equal to that of the double-sided copper clad laminate 1 having a foil thickness of about 0.18 μm, and the outer layer copper foils 3 and 4 are provided with reference holes 10 at their four corners. .

【0028】Pは、外層用銅箔と両面銅張積層板の間に
介在して両者を接着する所望の厚さのプリプレグであ
る。13は、熱プレスの下プレートに固着する押圧板であ
り、14は熱プレスの上プレートに固着する押圧板であ
る。
P is a prepreg of a desired thickness that is interposed between the outer layer copper foil and the double-sided copper-clad laminate to bond them. Reference numeral 13 is a pressing plate fixed to the lower plate of the heat press, and 14 is a pressing plate fixed to the upper plate of the heat press.

【0029】押圧板13,14 には、4隅のそれぞれに基準
ピン11がしっくりと遊貫する基準孔10を有する。図1
(B) に図示したように、コア材20の4隅のそれぞれの基
準マークSに一致する基準孔10を穿孔する。(基準マー
クSはコア材20の内層に形成されているが、X線を照射
することで基準マークSの位置は外部から確認でき
る。)そして、両面にフォトレジストを塗布した後に、
基準孔10に挿着した基準ピンにハードマスクの基準孔を
嵌合し、露光・現像し、エッチングして、図1(C) に図
示したように、内層回路L3 側の銅箔20a を内層回路L
2 とし、内層回路L4側の銅箔20b を内層回路L5 とす
る。
The pressing plates 13 and 14 have reference holes 10 at the four corners, through which the reference pins 11 fit smoothly. Figure 1
As shown in (B), reference holes 10 corresponding to the reference marks S at the four corners of the core material 20 are punched. (The fiducial mark S is formed on the inner layer of the core material 20, but the position of the fiducial mark S can be confirmed from the outside by irradiating X-rays.) Then, after applying photoresist to both surfaces,
The reference pin of the hard mask is fitted to the reference pin inserted into the reference hole 10, exposed, developed, and etched to remove the copper foil 20a on the inner layer circuit L 3 side as shown in FIG. 1 (C). Inner layer circuit L
2, and the copper foil 20b on the inner layer circuit L 4 side is the inner layer circuit L 5 .

【0030】次に図1(D) に図示したように、基準ピン
11にそれぞれの基準孔10を嵌合させて、押圧板13上に、
外層用銅箔4, 所望枚数(加圧圧縮された後に所望の層
厚の絶縁層が形成されるような枚数) のプリプレグP,
コア材20, 所望枚数のプリプレグP,外層用銅箔3,押
圧板14をこの順に重ねる。
Next, as shown in FIG. 1D, the reference pin
Fit each reference hole 10 to 11, and on the pressing plate 13,
Outer layer copper foil 4, a desired number of prepregs P (the number of which is such that an insulating layer having a desired layer thickness is formed after being pressed and compressed)
The core material 20, the desired number of prepregs P, the outer layer copper foil 3, and the pressing plate 14 are stacked in this order.

【0031】そして熱プレスにより加熱・加圧を行い、
接着・キュアさせて、図2(A) に示す、内層に内層回路
2 ,L3 ,L4 ,L5 を有し、表面に外層用銅箔3が
張着され、裏面に外層用銅箔4が張着された6層の印刷
配線板とする。
Then, heating / pressurization is performed by a hot press,
After bonding and curing, as shown in FIG. 2 (A), the inner layer has inner layer circuits L 2 , L 3 , L 4 and L 5 , the outer layer copper foil 3 is attached to the front surface, and the outer layer copper is attached to the back surface. The printed wiring board is a six-layer printed circuit board on which the foil 4 is attached.

【0032】次に、図2(B) に図示したように、両面に
フォトレジストを塗布した後に、基準孔10に挿着した基
準ピンにハードマスクの基準孔を嵌合し、露光・現像
し、エッチングして、外層用銅箔3を表面回路Ls に、
外層用銅箔4を裏面回路Lb にして、所望の回路を有す
る6層の多層印刷配線板とする。
Next, as shown in FIG. 2 (B), after applying photoresist on both sides, the reference holes of the hard mask are fitted to the reference pins inserted into the reference holes 10 and exposed and developed. , The copper foil 3 for the outer layer is etched to form the surface circuit Ls,
The outer layer copper foil 4 is used as the back surface circuit Lb to form a 6-layer multilayer printed wiring board having a desired circuit.

【0033】その後はビヤ,スルーホール等を設け、搭
載部品を実装する。本発明方法は上述のようにして、積
層メーカーからコア材20を購入し、その後ピンラミネー
ション方式により6層の多層印刷配線板を製造している
ので、従来のようにすべてをピンラミネーション方式で
行なう製造方法に較べて、装置メーカーが実施する内層
回路形成工程が2内層分だけ節減される。
After that, a via hole, a through hole, etc. are provided and mounting components are mounted. In the method of the present invention, as described above, the core material 20 is purchased from the laminating maker, and then the 6-layer multilayer printed wiring board is manufactured by the pin lamination method. Compared with the manufacturing method, the inner layer circuit forming process performed by the device manufacturer is reduced by two inner layers.

【0034】図3は8層の多層印刷配線板の実施例であ
る。図において、30は、マスラミネーション方式で製造
した3層の第1のコア材、40はマスラミネーション方式
で製造した3層の第2のコア材である。
FIG. 3 shows an embodiment of an 8-layer multilayer printed wiring board. In the figure, 30 is a three-layer first core material manufactured by a mass lamination method, and 40 is a three-layer second core material manufactured by a mass lamination method.

【0035】第1のコア材30は、内部導体層に内層回路
3 が形成され、表裏の両面にそれぞれ銅箔30a,銅箔30
b が張着されている。また、この内層回路L3 が形成さ
れた面の4隅のそれぞれに、基準孔10の内径に等しい円
形の基準マークSを設けてある。
In the first core material 30, the inner layer circuit L 3 is formed in the inner conductor layer, and the copper foil 30a and the copper foil 30 are provided on both front and back surfaces, respectively.
b is attached. Further, circular reference marks S having an inner diameter equal to the inner diameter of the reference hole 10 are provided at each of four corners of the surface on which the inner layer circuit L 3 is formed.

【0036】第2のコア材40は、内部導体層に内層回路
6 が形成され、表裏の両面にそれぞれ銅箔40a,銅箔40
b が張着されている。また、この内層回路L6 が形成さ
れた面の4隅のそれぞれに、基準孔10の内径に等しい円
形の基準マークSを設けてある。
In the second core member 40, the inner layer circuit L 6 is formed in the inner conductor layer, and the copper foil 40a and the copper foil 40 are formed on both the front and back surfaces, respectively.
b is attached. Further, circular reference marks S having an inner diameter equal to the inner diameter of the reference hole 10 are provided at each of four corners of the surface on which the inner layer circuit L 6 is formed.

【0037】このような第1のコア材30及び第2のコア
材40のそれぞれの4隅に、基準マークSに一致する基準
孔10を穿孔する。そして、基準孔10を基準にして第1の
コア材30の表面の銅箔30aをエッチングして内層回路L
2 とし、裏面の銅箔30b をエッチングして内層回路L4
とする。
Reference holes 10 corresponding to the reference marks S are punched at the four corners of each of the first core material 30 and the second core material 40. Then, the copper foil 30a on the surface of the first core member 30 is etched with reference to the reference hole 10 to etch the inner layer circuit L.
2, and the copper foil 30b on the back side is etched to form the inner layer circuit L 4
And

【0038】また、基準孔10を基準にして第2のコア材
40の表面の銅箔40aをエッチングして内層回路L5
し、裏面の銅箔40b をエッチングして内層回路L7 とす
る。次に図3(B) に図示したように、基準ピン11にそれ
ぞれの基準孔10を嵌合させて、押圧板13上に、外層用銅
箔4, 所望枚数(加圧圧縮された後に所望の層厚の絶縁
層が形成されるような枚数) のプリプレグP, 第2のコ
ア材40, 所望枚数のプリプレグP,第1のコア材30, 所
望枚数のプリプレグP,外層用銅箔3,押圧板14をこの
順に重ねる。
Also, the second core material is based on the reference hole 10.
The copper foil 40a on the front surface of 40 is etched to form the inner layer circuit L 5, and the copper foil 40b on the back surface is etched to form the inner layer circuit L 7 . Next, as shown in FIG. 3 (B), the reference holes 10 are fitted into the reference pins 11, and the outer layer copper foil 4, the desired number of sheets (the desired number after being compressed under pressure, are provided on the pressing plate 13. Number of prepregs P, second core material 40, desired number of prepregs P, first core material 30, desired number of prepregs P, outer layer copper foil 3, The pressing plates 14 are stacked in this order.

【0039】そして熱プレスにより加熱・加圧を行い、
接着・キュアさせて、内層に内層回路L2 ,L3
4 ,L5 , L6 ,L7 を有し、表面に外層用銅箔3が
張着され、裏面に外層用銅箔4が張着された多層印刷配
線板とする。
Then, heat and pressure are applied by a hot press,
After bonding and curing, the inner layer circuits L 2 , L 3 ,
A multilayer printed wiring board having L 4 , L 5 , L 6 , and L 7 , the outer layer copper foil 3 being adhered to the front surface, and the outer layer copper foil 4 being adhered to the back surface.

【0040】そして、両面にフォトレジストを塗布した
後に、基準孔10に挿着した基準ピンにハードマスクの基
準孔を嵌合し、露光・現像し、エッチングして、外層用
銅箔3を表面回路Ls に、外層用銅箔4を裏面回路Lb
にして、所望の回路を有する8層の多層印刷配線板とす
る。
After coating the photoresist on both sides, the reference holes of the hard mask are fitted into the reference pins inserted into the reference holes 10, exposed, developed and etched to expose the outer layer copper foil 3 on the surface. The outer layer copper foil 4 is connected to the circuit Ls and the backside circuit Lb is used.
Then, an 8-layer multilayer printed wiring board having a desired circuit is obtained.

【0041】図4は12層の多層印刷配線板の実施例であ
る。図において、50は、マスラミネーション方式で製造
した4層の第1のコア材、60はマスラミネーション方式
で製造した2層の第2のコア材、70は、マスラミネーシ
ョン方式で製造した4層の第3のコア材である。
FIG. 4 shows an example of a 12-layer multilayer printed wiring board. In the figure, 50 is a four-layer first core material manufactured by a mass lamination method, 60 is a two-layer second core material manufactured by a mass lamination method, and 70 is a four-layer mass layer manufactured by a mass lamination method. It is a third core material.

【0042】第1のコア材50は、内部絶縁層の一方の面
に内層回路L3 が形成され、他方の面に内層回路L4
形成されている。そして内層回路L3 の外側の絶縁層の
表面に銅箔50a が張着され、内層回路L4 の外側の絶縁
層の表面に銅箔50b が張着されている。
In the first core material 50, the inner layer circuit L 3 is formed on one surface of the inner insulating layer, and the inner layer circuit L 4 is formed on the other surface. Then the copper foil 50a on the surface of the outer insulating layer of the inner layer circuit L 3 is tensioning copper foil 50b to the surface of the outer insulating layer of the inner layer circuit L 4 are tensioning.

【0043】また、この内層回路L3 と内層回路L4
形成された面の4隅のそれぞれに、基準孔10の内径に等
しい円形の基準マークS(銅箔をエッチングして形成さ
れたマーク)を設けてある。
Further, circular reference marks S (marks formed by etching a copper foil) having the same inner diameter as the reference hole 10 are provided at each of four corners of the surface on which the inner layer circuit L 3 and the inner layer circuit L 4 are formed. ) Is provided.

【0044】第3のコア材70は、内部絶縁層の一方の面
に内層回路L9 が形成され、他方の面に内層回路L10
形成されている。そして内層回路L9 の外側の絶縁層の
表面に銅箔70a が張着され、内層回路L10の外側の絶縁
層の表面に銅箔70b が張着されている。
In the third core member 70, the inner layer circuit L 9 is formed on one surface of the inner insulating layer, and the inner layer circuit L 10 is formed on the other surface. Then, a copper foil 70a is attached to the surface of the outer insulating layer of the inner layer circuit L 9 , and a copper foil 70b is attached to the surface of the outer insulating layer of the inner layer circuit L 10 .

【0045】また、この内層回路L9 と内層回路L10
形成された面の4隅のそれぞれに、基準孔10の内径に等
しい円形の基準マークSを設けてある。第1のコア材5
0, 第3のコア材70の4隅のそれぞれの基準マークSに
一致する基準孔10を穿孔する。
Further, circular reference marks S equal to the inner diameter of the reference hole 10 are provided at each of four corners of the surface on which the inner layer circuit L 9 and the inner layer circuit L 10 are formed. First core material 5
0, the reference holes 10 corresponding to the reference marks S at the four corners of the third core material 70 are punched.

【0046】そして、基準孔10を基準にして第1のコア
材50の表面の銅箔50aをエッチングして内層回路L2
し、裏面の銅箔50b をエッチングして内層回路L5 とす
る。また、基準孔10を基準にして第3のコア材70の表面
の銅箔70aをエッチングして内層回路L8 とし、裏面の
銅箔70b をエッチングして内層回路L11とする。
Then, the copper foil 50a on the front surface of the first core material 50 is etched to form the inner layer circuit L 2 and the copper foil 50b on the back surface is etched to form the inner layer circuit L 5 with reference to the reference hole 10. Further, the inner layer circuit L 8 and the reference hole 10 by etching the copper foil 70a on the surface of the third core member 70 with respect to the inner layer circuit L 11 the back surface of the copper foil 70b is etched.

【0047】一方、基準孔10を基準にして、第2のコア
材60の銅箔をエッチングして、一方の面に内層回路L6
を、他方の面に内層回路L7 を形成する。次に図4(B)
に図示したように、基準ピン11にそれぞれの基準孔10を
嵌合させて、押圧板13上に、外層用銅箔4, 所望枚数の
プリプレグP, 第3のコア材70,所望枚数のプリプレグ
P,第2のコア材60, 所望枚数のプリプレグP,第1の
コア材50, 所望枚数のプリプレグP,外層用銅箔3,押
圧板14をこの順に重ねる。
On the other hand, the copper foil of the second core material 60 is etched with reference to the reference hole 10, and the inner layer circuit L 6 is formed on one surface.
And the inner layer circuit L 7 is formed on the other surface. Next, Fig. 4 (B)
As shown in FIG. 3, the reference holes 11 are fitted into the reference pins 11, and the outer layer copper foil 4, the desired number of prepregs P, the third core material 70, and the desired number of prepregs are provided on the pressing plate 13. P, the second core material 60, the desired number of prepregs P, the first core material 50, the desired number of prepregs P, the outer layer copper foil 3, and the pressing plate 14 are stacked in this order.

【0048】そして熱プレスにより加熱・加圧を行い、
接着・キュアさせて、内層に内層回路L2 ,L3
4 ,L5 , L6 ,L7 ,L8 , L9 ,L10, 11
有し、表面に外層用銅箔3が張着され、裏面に外層用銅
箔4が張着された多層印刷配線板とする。
Then, heat and pressure are applied by a hot press,
After bonding and curing, the inner layer circuits L 2 , L 3 ,
L 4, has a L 5, L 6, L 7 , L 8, L 9, L 10, L 11, outer layer copper foil 3 is tensioning the surface, the outer layer copper foil 4 is tensioning the rear surface Multi-layer printed wiring board.

【0049】そして、両面にフォトレジストを塗布した
後に、基準孔10に挿着した基準ピンにハードマスクの基
準孔を嵌合し、露光・現像し、エッチングして、外層用
銅箔3を表面回路Ls に、外層用銅箔4を裏面回路Lb
にして、所望の回路を有する12層の多層印刷配線板とす
る。
Then, after coating the photoresist on both sides, the reference holes of the hard mask are fitted to the reference pins inserted into the reference holes 10, exposed, developed and etched to expose the outer layer copper foil 3 on the surface. The outer layer copper foil 4 is connected to the circuit Ls and the backside circuit Lb is used.
Thus, a 12-layer multilayer printed wiring board having a desired circuit is obtained.

【0050】[0050]

【発明の効果】以上説明したように本発明は、コア材は
内層回路は既に形成されマスラミネーション方式で積層
した4層以下のものとし、ピンラミネーション方式によ
り上下に外層用銅箔を積層するようにしたことにより、
小径ビア, IVH, 或いは微細パターンを有する6層以
上の多層印刷配線板に適用して、層ずれが殆ど発生する
ことないという効果を有する。
As described above, according to the present invention, the core material has four layers or less in which the inner layer circuit is already formed and laminated by the mass lamination method, and the copper foils for the outer layers are laminated on the upper and lower sides by the pin lamination method. By doing,
When applied to a multilayer printed wiring board having 6 or more layers having a small-diameter via, IVH, or a fine pattern, it has an effect that layer deviation hardly occurs.

【0051】また、コア材を積層メーカーから購入する
ようにすることで、装置メーカーの内層回路形成工程が
節減されるので、納期の短縮が行なわれる。一方、装置
メーカーとしては、マスラミネーション方式の製造設備
を特別に購入する必要がないので、マスラミネーション
方式の設備費分だけ多層印刷配線板が低コストになる。
Further, by purchasing the core material from the laminated maker, the manufacturing process of the inner layer circuit of the device maker can be saved, so that the delivery time can be shortened. On the other hand, as a device maker, it is not necessary to purchase a mass-lamination-type manufacturing facility, so that the cost of the multi-layer printed wiring board is reduced by the cost of the mass-lamination-type facility.

【図面の簡単な説明】[Brief description of drawings]

【図1】 (A) 〜(D) は本発明の実施例の製造工程の前
段を示す図
FIG. 1 (A) to (D) are views showing a former stage of a manufacturing process of an embodiment of the present invention.

【図2】 (A),(B) は本発明の実施例の製造工程の後段
を示す図
2 (A) and 2 (B) are views showing the latter stage of the manufacturing process of the embodiment of the present invention.

【図3】 (A),(B) は本発明の他の実施例の図3A and 3B are views of another embodiment of the present invention.

【図4】 (A),(B) は本発明のさらに他の実施例の図4 (A) and (B) are diagrams of still another embodiment of the present invention.

【図5】 (A) 〜(C) は従来の製造工程の前段を示す図5 (A) to (C) are views showing a former stage of a conventional manufacturing process.

【図6】 (A),(B) は従来の製造工程の後段を示す図6 (A) and 6 (B) are views showing the latter stage of the conventional manufacturing process.

【符号の説明】[Explanation of symbols]

1,2 両面銅張積層板 1a,1B,2a,2b 銅箔 3,4 外層用銅箔 10 基準孔 11 基準ピン 13,14 押圧板 18 IVH 20 コア材 30,50 第1のコア材 40,60 第2のコア材 70 第3のコア材 P プリプレグ S 基準マーク Ls 表面回路 Lb 裏面回路 L2 〜L11 内層回路1,2 Double-sided copper clad laminate 1a, 1B, 2a, 2b Copper foil 3,4 Copper foil for outer layer 10 Reference hole 11 Reference pin 13,14 Pressing plate 18 IVH 20 Core material 30,50 First core material 40, 60 second core member 70 third core material P prepreg S reference mark Ls surface circuit Lb backside circuit L 2 ~L 11 inner layer circuit

───────────────────────────────────────────────────── フロントページの続き (72)発明者 丸山 米蔵 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Maruyama Yonezo 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 マスラミネーション方式で製造した(4)
層の印刷配線板に基準孔(10)を設けてコア材(20)とし、 該コア材(20)の上下にプリプレグ(P)を介してそれぞ
れ外層用銅箔(3,4) を、ピンラミネーション方式により
積層することを特徴とする多層印刷配線板の製造方法。
1. The method of manufacturing by a maslamination method (4)
A reference hole (10) is provided in the printed wiring board of the layer to form a core material (20), and the outer layer copper foils (3, 4) are respectively placed above and below the core material (20) via prepregs (P). A method for manufacturing a multilayer printed wiring board, which comprises laminating the layers by a lamination method.
【請求項2】 マスラミネーション方式で製造した3層
乃至4層の複数の印刷配線板に基準孔(10)を設けてコア
材とし、 それぞれの該コア材間にプリプレグ(P)が介在し、最
上層のコア材の上に他のプリプレグ(P)を介して外層
用銅箔(3) を、最下層のコア材の下に他のプリプレグ
(P)を介して他の外層用銅箔(4) を、ピンラミネーシ
ョン方式により積層することを特徴とする多層印刷配線
板の製造方法。
2. A core material provided with reference holes (10) in a plurality of printed wiring boards of three to four layers manufactured by a maslamination method, and a prepreg (P) is interposed between the core materials, The outer layer copper foil (3) is placed on the uppermost core material through another prepreg (P), and the outer copper foil (3) is placed under the lowermost core material through another prepreg (P). A method for manufacturing a multilayer printed wiring board, characterized in that 4) is laminated by a pin lamination method.
【請求項3】 マスラミネーション方式で製造した少な
くとも一枚の3層乃至4層の印刷配線板と、両面にパタ
ーンが形成された少なくとも一枚の印刷配線板とを有
し、それぞれの該印刷配線板に基準孔(10)を設けてコア
材とし、 それぞれの該コア材間にプリプレグ(P)が介在し、最
上層のコア材の上に他のプリプレグ(P)を介して外層
用銅箔(3) を、最下層のコア材の下に他のプリプレグ
(P)を介して他の外層用銅箔(4) を、ピンラミネーシ
ョン方式により積層することを特徴とする多層印刷配線
板の製造方法。
3. A printed wiring board having at least one three-layer to four-layer printed board manufactured by a maslamination method and at least one printed wiring board having a pattern formed on both surfaces thereof. A plate is provided with reference holes (10) as core materials, prepregs (P) are interposed between the respective core materials, and an outer layer copper foil is provided on the uppermost core material through another prepreg (P). A multilayer printed wiring board characterized in that (3) is laminated with another outer layer copper foil (4) under the core material of the lowermost layer through another prepreg (P) by a pin lamination method. Method.
JP866993A 1993-01-22 1993-01-22 Manufacture of multilayer printed board Withdrawn JPH06224553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP866993A JPH06224553A (en) 1993-01-22 1993-01-22 Manufacture of multilayer printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP866993A JPH06224553A (en) 1993-01-22 1993-01-22 Manufacture of multilayer printed board

Publications (1)

Publication Number Publication Date
JPH06224553A true JPH06224553A (en) 1994-08-12

Family

ID=11699347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP866993A Withdrawn JPH06224553A (en) 1993-01-22 1993-01-22 Manufacture of multilayer printed board

Country Status (1)

Country Link
JP (1) JPH06224553A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020023888A (en) * 2001-12-27 2002-03-29 박종선 Multilayer printed circuit board and manufacturing method
KR100568880B1 (en) * 2005-12-09 2006-04-10 주식회사 영은전자 Printed circuit board having combining structure by etching and the combining method
JP5223926B2 (en) * 2008-09-30 2013-06-26 イビデン株式会社 Method for manufacturing printed wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020023888A (en) * 2001-12-27 2002-03-29 박종선 Multilayer printed circuit board and manufacturing method
KR100568880B1 (en) * 2005-12-09 2006-04-10 주식회사 영은전자 Printed circuit board having combining structure by etching and the combining method
JP5223926B2 (en) * 2008-09-30 2013-06-26 イビデン株式会社 Method for manufacturing printed wiring board

Similar Documents

Publication Publication Date Title
US7223687B1 (en) Printed wiring board and method of fabricating the same
US8863379B2 (en) Methods of manufacturing printed circuit boards using parallel processes to interconnect with subassemblies
WO2010113448A1 (en) Manufacturing method for circuit board, and circuit board
JPWO2008146487A1 (en) Circuit board and manufacturing method thereof
KR101694575B1 (en) Methods of manufacturing printed circuit boards using parallel processes to interconnect with subassemblies
JPH08139454A (en) Manufacturing method of printed-wiring board
JP4206545B2 (en) Manufacturing method of multilayer printed wiring board
JP3231537B2 (en) Method for manufacturing multilayer substrate
JPH06224553A (en) Manufacture of multilayer printed board
KR20010005137A (en) Method of manufacturing multi-layer printed circuit board
JP2740028B2 (en) Multilayer printed wiring board
JP2943767B2 (en) Method for manufacturing multilayer wiring board
KR100222754B1 (en) Fabrication method of rigid-flexible laminate elevation of surface confidence
JP2004214393A (en) Method for producing multilayer wiring board
JP4199957B2 (en) Manufacturing method of multilayer wiring board
JP2000151102A (en) Manufacture of multilayer circuit board
KR101395904B1 (en) Manufacturing multilayer flexible printed circuit board
JP2001237549A (en) Multilayered wiring board and its manufacturing method
JP2002329964A (en) Method of manufacturing multilayer printed wiring board
JPS6247199A (en) Manufacture of inner layer circuit board for multilayer circuit board
KR20180025345A (en) Rigid flexible circuit board manufacturing method
JP3594765B2 (en) Manufacturing method of multilayer printed wiring board
JPH0545079B2 (en)
JP2003124604A (en) Manufacturing method for circuit board
JPH10126058A (en) Manufacture of multilayered printed interconnection board

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20000404